CN114299820A - Array substrate and display panel - Google Patents
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- CN114299820A CN114299820A CN202111642253.5A CN202111642253A CN114299820A CN 114299820 A CN114299820 A CN 114299820A CN 202111642253 A CN202111642253 A CN 202111642253A CN 114299820 A CN114299820 A CN 114299820A
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- 239000002184 metal Substances 0.000 claims description 13
- 230000000694 effects Effects 0.000 abstract description 9
- 239000011295 pitch Substances 0.000 description 41
- 238000000034 method Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 2
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Abstract
The application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate and a plurality of pixel circuit units arranged in an array mode, wherein the pixel circuit units are positioned on one side of the substrate; the orthographic projection areas of the pixel circuit units on the substrate are the same, and the length of the orthographic projection of the pixel circuit units is less than 61 micrometers, and the width of the orthographic projection of the pixel circuit units is less than 61 micrometers; the pixel circuit units arranged in an array form a pixel circuit group, and the pixel circuit groups are arranged in an array; the pitch of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate. The pixel circuit unit can ensure that the arrangement periods of a plurality of pixel circuit groups in the display area are the same under the condition of realizing the tight arrangement of the pixel circuit units, thereby effectively compressing the space and avoiding the moire effect.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In the prior art, in order to realize a narrow frame, part of the pixel circuit area is usually compressed, so as to realize a narrow frame effect.
However, the compression method causes the pixel circuit size in the compressed area to be smaller than that in the normal area, and the pixel circuit size is different, so moire is easily generated, resulting in Mura (uneven display) and further affecting the display screen effect.
Disclosure of Invention
The technical problem that this application mainly solved provides an array substrate and display panel, through the size of compressing each pixel circuit unit to adjust the interval between the inside pixel circuit unit of pixel circuit group and the interval between the adjacent pixel circuit group, can solve among the prior art and realize that narrow frame produces the problem of mole line easily.
In order to solve the above technical problem, a first technical solution adopted by the present application is to provide an array substrate, where the array substrate includes a substrate, and a plurality of pixel circuit units arranged in an array and located on one side of the substrate; the orthographic projection areas of the pixel circuit units on the substrate are the same, and the length of the orthographic projection of the pixel circuit units is less than 61 micrometers, and the width of the orthographic projection of the pixel circuit units is less than 61 micrometers; the pixel circuit units arranged in an array form a pixel circuit group, and the pixel circuit groups are arranged in an array; the pitch of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate.
The distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate along the first direction is smaller than the distance between the orthographic projections of the adjacent pixel circuit groups on the substrate along the first direction; and/or the distance of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate along the second direction is smaller than the distance of the orthographic projection of each adjacent pixel circuit group on the substrate along the second direction; the first direction is a row direction, and the second direction is a column direction.
Wherein, all the pixel circuit groups are arranged at equal intervals.
Wherein, the length of the orthographic projection of the single pixel circuit unit is 51 micrometers, and the width is 51 micrometers.
The array substrate further comprises virtual wires, and orthographic projections of the virtual wires on the substrate are located between orthographic projections of the adjacent pixel circuit groups on the substrate.
Wherein the orthographic projection of the virtual lead on the substrate extends along a second direction; and/or the orthographic projection of the virtual wire on the substrate extends along the first direction.
And only one virtual lead is arranged between every two adjacent pixel circuit groups, so that the distance between the orthographic projection of each pixel circuit group on the substrate and the orthographic projection of the virtual lead on the substrate is equal to the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
A plurality of virtual leads are arranged between every two adjacent pixel circuit groups, and the distance between the orthographic projection of the pixel circuit groups on the substrate and the orthographic projection of the closest virtual lead on the substrate is equal to the distance between the orthographic projections of the adjacent pixel circuit units in the pixel circuit groups on the substrate; the pitch of the orthographic projections of the adjacent virtual wires on the substrate is equal to the pitch of the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
The array substrate comprises a plurality of film layers which are stacked on a substrate, and a virtual lead is arranged on at least one film layer in the plurality of film layers and/or between any two adjacent film layers.
Wherein the multilayer film layer comprises a plurality of metal layers; the virtual lead and at least one metal layer in the multiple metal layers are arranged in the same layer; preferably, the multi-layer metal layer includes a first electrode layer including a plurality of first electrodes, each of the first electrodes is electrically connected to each of the pixel circuit units, and the dummy wire is located between the first electrodes.
The beneficial effect of this application is: being different from the prior art, the application provides an array substrate and a display panel, through keeping the orthographic projection area of all pixel circuits on the base the same, and compress the size of each pixel circuit unit, and make the orthographic projection interval of adjacent pixel circuit unit in each pixel circuit group on the base, be less than the orthographic projection interval of each adjacent pixel circuit group on the base, can realize under the circumstances that pixel circuit unit closely arranges, ensure that the cycle of arranging of a plurality of pixel circuit groups in the display area is the same, thereby effective compression space, in order to avoid the moire effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a top view of a first embodiment of an array substrate according to the present application;
FIG. 2 is a top view of a second embodiment of an array substrate according to the present application;
FIG. 3 is a top view of a third embodiment of an array substrate according to the present application;
fig. 4 is a top view of a fourth embodiment of an array substrate according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Referring to fig. 1, fig. 1 is a top view of a first embodiment of an array substrate according to the present application.
As shown in fig. 1, the array substrate 100 includes a base (not shown), a pixel circuit region 110 located at one side of the base, and the pixel circuit region 110 includes a plurality of pixel circuit units 112 arranged in an array. The orthographic projection area of each pixel circuit unit 112 on the substrate is the same, and the length of the orthographic projection of the pixel circuit unit 112 is less than 61 micrometers, and the width is less than 61 micrometers. The pixel circuit units 112 arranged in an array form a pixel circuit group 111, and the pixel circuit groups 111 are arranged in an array. The pitch of the orthographic projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate.
Specifically, the size of the orthographic projection of the standard circuit on the substrate is generally 61 micrometers in length and 61 micrometers in width, and by compressing the size of each pixel circuit unit 112 to make both the length and the width of the pixel circuit unit smaller than 61 micrometers, the pixel circuit area can be compressed without affecting the display, thereby realizing the narrow frame design.
In a preferred embodiment, the size of the orthographic projection of each pixel circuit cell 112 on the substrate may be compressed to 51 microns in length and 51 microns in width. It can be understood that, by compressing the size of the pixel circuit unit 112 to 51 μm in length and width, the distribution area of the pixel circuit unit 112 can be greatly reduced, thereby optimizing the narrow frame design.
Specifically, the area of each pixel circuit unit 112 is maximally 70% of the standard circuit area, that is, the length and width of each pixel circuit unit 112 can be adjusted within 51-61 micrometers, and in other embodiments, the length and width of the orthographic projection of each pixel circuit unit 112 on the substrate can be set to any value (excluding the end points) within 51-61 micrometers, which is not limited in this application.
As can be appreciated, since the forward projection areas of all the pixel circuit units 112 on the substrate in the display area are the same, uniformity among the pixel circuit units 112 is maintained, and display differences caused by different sizes of the pixel circuit units 112 in different areas are avoided.
Each pixel circuit unit 112 corresponds to a first electrode, if each pixel circuit unit 112 is compressed, and is not grouped, the area of the pixel circuit region 110 formed by all the pixel circuit units 112 is greatly smaller than the area of the first electrode layer 130, the connection lines of the plurality of pixel circuit units 112 and the plurality of first electrodes are crossed, which is not beneficial to wiring. Meanwhile, in order to further compress the pixel circuit region 110, the pitch of the pixel circuit units 112 inside each pixel circuit group 111 is compressed.
In this embodiment, the pitch of the orthographic projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate along the first direction is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate along the first direction. The first direction is a row direction, and the second direction is a column direction.
Specifically, the array substrate 100 includes a plurality of scan lines 122 disposed in parallel and a plurality of data lines 121 disposed in parallel, and the data lines 121 are disposed perpendicular to the scan lines 122. In this embodiment, the array substrate 100 further includes a horizontal enable signal trace (not shown) and a vertical operating voltage trace (not shown), and the scan lines 122, the enable signal trace, the data lines 121 and the operating voltage trace are arranged in a grid shape with the same period.
The row direction is the extending direction of the scan line 122, and the column direction is the extending direction of the data line 121.
In another embodiment, the pitch of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate along the second direction is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate along the second direction. For example, referring to fig. 2, fig. 2 is a top view of a second embodiment of an array substrate according to the present application. As shown in fig. 2, the pitch of the orthographic projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate in the second direction in the array substrate 100 is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate in the second direction.
In yet another embodiment, a pitch of orthographic projections of adjacent pixel circuit units on the substrate in each pixel circuit group along the first direction is smaller than a pitch of orthographic projections of adjacent pixel circuit units on the substrate in the first direction, and a pitch of orthographic projections of adjacent pixel circuit units on the substrate in each pixel circuit group along the second direction is smaller than a pitch of orthographic projections of adjacent pixel circuit units on the substrate in the second direction. Specifically, referring to fig. 3 and 4, fig. 3 is a top view of a third embodiment of an array substrate of the present application, and fig. 4 is a top view of a fourth embodiment of the array substrate of the present application.
As shown in fig. 3 and 4, in the array substrate 100, a pitch of an orthogonal projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate along the first direction is smaller than a pitch of an orthogonal projection of each adjacent pixel circuit group 111 on the substrate along the first direction, and a pitch of an orthogonal projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate along the second direction is smaller than a pitch of an orthogonal projection of each adjacent pixel circuit group on the substrate along the second direction. In fig. 3, each pixel circuit group 111 includes 9 pixel circuit units 112 of 3 × 3 (3 in each row and 3 in each column). In fig. 4, each pixel circuit group 111 includes 16 pixel circuit units 112 of 4 × 4 (4 per row and 4 per column).
In this embodiment, the pixel circuit groups 111 are arranged at equal intervals. Specifically, the pixel circuit groups 111 are arranged at equal intervals in the first direction.
In a specific embodiment, as shown in fig. 1, the pixel circuit groups 111 are arranged at equal intervals along the first direction, and the number of rows in each pixel circuit group 111 is greater than the number of columns, and includes at least two columns of pixel circuit units 112. In another specific embodiment, as shown in fig. 2, the pixel circuit groups 111 are arranged at equal intervals along the second direction, and each pixel circuit group 111 has at least two rows of pixel circuit units 112 and has more columns than rows. In another embodiment, as shown in fig. 3 and 4, the pixel circuit groups 111 are arranged along the first direction and the second direction at the same time, and the number of rows is equal to the number of columns. The pitch in the first direction and the pitch in the second direction may be the same or different, and the present application does not limit this.
It can be understood that the equidistant arrangement enables the circuit arrangement periods of all the pixel circuit groups 111 in the display area to be the same, and because the distance between the adjacent pixel circuit units 112 inside the pixel circuit groups 111 is smaller than the distance between the adjacent pixel circuit groups 111 outside, the routing area of the pixel circuit groups 111 can be effectively compressed, so that the pixel circuit units 112 are closely arranged, thereby compressing the pixel area 110 in the display area to realize the narrow-frame design. Further, since the embodiment compresses the space between the columns and/or rows of the adjacent pixel circuit units 112 in all the regularly arranged pixel circuit groups 111 in the display area, rather than compressing only the pixel circuit areas on the left and right sides or a certain pixel circuit area, it is possible to avoid the moire effect caused by the different arrangement periods of the pixel circuit units 112 between the compressed area and the rest of the non-compressed area, and further avoid the display Mura to improve the display screen effect.
In this embodiment, the gate lines 140 are disposed on both sides of the left and right edges of the pixel circuit region 110.
In the prior art, the position of the first electrode layer corresponds to the position of the pixel circuit region, and the gate circuit is usually disposed outside the first electrode layer, but in the present application, since the pixel circuit region 110 is compressed as a whole, the area of the pixel circuit region 110 is smaller than that of the first anode layer 130, partial regions are left on the left and right sides of the first anode layer 130, and partial gate circuit can be disposed on the portion of the first anode layer 130 that does not correspond to the pixel circuit region 110, thereby further implementing a narrow frame design.
Further, the array substrate 100 further includes dummy conductive lines (not shown), and the orthographic projections of the dummy conductive lines on the substrate are located between the orthographic projections of the adjacent pixel circuit groups 111 on the substrate.
In this embodiment, the orthogonal projection of the dummy conductive line on the substrate extends in the second direction.
Specifically, one or more dummy conductive lines may be disposed between each adjacent pixel circuit group 111 according to the size of the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate.
For example, when the pitch of the orthographic projections of the adjacent row and/or column pixel circuit groups 111 on the substrate is equal to twice the pitch of the orthographic projections of the adjacent row and/or column pixel circuit units 112 on the substrate in the adjacent pixel circuit groups 111, only one virtual lead may be arranged between the adjacent row and/or column pixel circuit groups 111, and the orthographic projections of the virtual lead on the substrate are located between the orthographic projections of the adjacent row and/or column pixel circuit groups 111 on the substrate, so that the pitch of the orthographic projections of the adjacent row and/or column pixel circuit groups 111 on the substrate and the orthographic projections of the virtual lead on the substrate is equal to the pitch of the orthographic projections of the adjacent row and/or column pixel circuit units 112 on the substrate in the adjacent pixel circuit groups 111.
For another example, when the pitch of the orthographic projection of each adjacent row and/or column pixel circuit group 111 on the substrate is equal to at least three times the pitch of the orthographic projection of the adjacent row and/or column pixel circuit unit 112 on the substrate within each pixel circuit group 111, a plurality of virtual wires are arranged between each adjacent row and/or column pixel circuit group 111, and the pitch between the orthographic projection of the pixel circuit group 111 on the substrate and the orthographic projection of the nearest virtual wire on the substrate is equal to the pitch of the orthographic projection of the adjacent row and/or column pixel circuit unit 112 on the substrate within each pixel circuit group 111. The pitch of the orthographic projections of the adjacent virtual wires on the substrate is equal to the pitch of the orthographic projections of the adjacent row and/or column pixel circuit units 112 in each pixel circuit group 111 on the substrate.
It can be understood that the orthographic projection formed by the virtual conductive line is to form a new pitch between the pixel circuit groups 111 of each adjacent row and/or column, that is, the pitch formed by the pixel circuit groups 111 of each adjacent row and/or column and the orthographic projection of the virtual conductive line, when the new pitch is equal to the pitch between the pixel circuit units 112 of adjacent rows and/or columns in each pixel circuit group 111 group, the pitches formed in the row and/or column directions of the pixel circuit units 112 inside and outside the pixel circuit group 111 group can be equal, so as to achieve uniformity of circuit density distribution in the whole display area, avoid crosstalk from affecting the precision and size of the pixel circuit units 112, and avoid crosstalk from affecting key signals, and further avoid moire effect.
In other embodiments, the new pitch formed between the pixel circuit groups 111 of adjacent rows and/or columns may be slightly larger or smaller than the pitch between the pixel circuit units 112 of adjacent rows and/or columns within each pixel circuit group 111, which is not limited in this application.
In this embodiment, the array substrate 100 includes a plurality of layers stacked on a substrate, and the dummy conductive line is disposed on at least one of the plurality of layers and/or between any two adjacent layers.
Wherein the multilayer film layer comprises a plurality of metal layers. The dummy wire and at least one metal layer of the multiple metal layers are arranged in the same layer. Preferably, the multi-layer metal layer includes a first electrode layer 130, the first electrode layer 130 includes a plurality of first electrodes, each first electrode is electrically connected to each pixel circuit unit, and the dummy wire is located between the first electrodes. The first electrode layer 130 is an anode layer.
In particular, when the dummy conductive lines extend only in the first direction or only in the second direction, the dummy conductive lines may be disposed on at least one of the plurality of film layers since there is no crossing between the dummy conductive lines. When the dummy conductive lines extend in the first direction and the second direction at the same time, in order to avoid the dummy conductive lines crossing on the same metal film layer, the dummy conductive lines extending in different directions must be disposed on different film layers.
Different from the prior art, in the embodiment, by keeping the orthographic projection areas of all the pixel circuits on the substrate the same, compressing the size of each pixel circuit unit, and making the orthographic projection distance of the adjacent row and/or column pixel circuit units in each pixel circuit group on the substrate smaller than the orthographic projection distance of the adjacent row and/or column pixel circuit groups on the substrate, the arrangement periods of the pixel circuit groups in the display area can be ensured to be the same under the condition of realizing the close arrangement of the pixel circuit units, so that the space is effectively compressed to avoid the moire effect. In addition, by arranging the virtual lead between the pixel circuit groups of each adjacent row and/or column and enabling the distance between the orthographic projection of each adjacent pixel circuit group and the virtual lead to be equal to the distance between the pixel circuit units in each pixel circuit group, the uniformity of the distribution of the circuit density in the whole display area can be realized, the influence of crosstalk on the precision and the size of the pixel circuit units is avoided, the influence of crosstalk on key signals is avoided, and the Moire effect is further avoided.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. An array substrate comprises a base, a plurality of pixel circuit units arranged in an array mode and located on one side of the base; the pixel circuit unit is characterized in that the orthographic projection areas of the pixel circuit units on the substrate are the same, the length of the orthographic projection of the pixel circuit units is less than 61 micrometers, and the width of the orthographic projection of the pixel circuit units is less than 61 micrometers; the pixel circuit units arranged in an array form a pixel circuit group, and the pixel circuit groups are arranged in an array; the pitch of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the pitch of the orthographic projection of the adjacent pixel circuit groups on the substrate.
2. The array substrate of claim 1, wherein a pitch of orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate along a first direction is smaller than a pitch of orthographic projections of adjacent pixel circuit groups on the substrate along the first direction; and/or the presence of a gas in the gas,
the distance of the orthographic projection of the adjacent pixel circuit units in each pixel circuit group on the substrate along a second direction is smaller than the distance of the orthographic projection of each adjacent pixel circuit group on the substrate along the second direction;
the first direction is a row direction, and the second direction is a column direction.
3. The array substrate of claim 2, wherein the pixel circuit groups are arranged at equal intervals.
4. The array substrate of any one of claims 1 to 3, wherein the orthographic projection of a single pixel circuit unit has a length of 51 microns and a width of 51 microns.
5. The array substrate of claim 4, further comprising dummy conductive lines, wherein orthographic projections of the dummy conductive lines on the substrate are located between orthographic projections of the pixel circuit groups on the substrate.
6. The array substrate of claim 5, wherein an orthographic projection of the dummy conductive line on the substrate extends in the second direction; and/or the orthographic projection of the virtual lead on the substrate extends along the first direction.
7. The array substrate of claim 6, wherein only one of the dummy conductive lines is disposed between each adjacent pixel circuit groups, so that a pitch between an orthographic projection of each pixel circuit group on the substrate and an orthographic projection of the dummy conductive line on the substrate is equal to a pitch between orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate.
8. The array substrate of claim 6, wherein a plurality of the dummy conductive lines are disposed between each adjacent pixel circuit groups, and a pitch between an orthographic projection of the pixel circuit group on the substrate and an orthographic projection of a nearest one of the dummy conductive lines on the substrate is equal to a pitch of orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate; the pitch of orthographic projections of the adjacent virtual wires on the substrate is equal to the pitch of orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
9. The array substrate according to any one of claims 5 to 8, wherein the array substrate comprises a plurality of film layers stacked on the substrate, and the dummy conductive line is disposed on at least one of the plurality of film layers and/or between any two adjacent film layers.
10. The array substrate of claim 9, wherein the multi-layer film layer comprises a plurality of metal layers;
the virtual lead and at least one metal layer in the multiple metal layers are arranged on the same layer;
preferably, the multilayer metal layer includes a first electrode layer including a plurality of the first electrodes, each of the first electrodes is electrically connected to each of the pixel circuit units, and the dummy wire is located between the first electrodes.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512499A (en) * | 2022-01-28 | 2022-05-17 | 昆山国显光电有限公司 | Display panel and display device |
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| CN114299820B (en) | 2024-02-02 |
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