CN114285408A - Double-clock-source switching method and system - Google Patents
Double-clock-source switching method and system Download PDFInfo
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Abstract
The application relates to a double clock source switching method and a double clock source switching system, wherein the method comprises the steps of obtaining operating environment parameters of a circuit board detected by an environment detection circuit, detecting whether the operating environment parameters contain operating signals transmitted by the whole machine, and obtaining a detection result; if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source; and if the detection result is yes, configuring the phase-locked loop circuit to switch and lock the second clock source. The clock source switching method and the clock source switching device are used for solving the problem that the clock source needs to be manually switched at present.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and a system for switching a dual clock source.
Background
In communication networks, existing devices typically design dual clock sources, but different scenarios use different clock sources. For example, when only the circuit board is in a working state, the system clock and the reference clock are not required to be homologous, but when the whole machine is in a working state, the system clock and the reference clock are required to be homologous. However, in the using process, different configuration files need to be manually replaced according to different scenes, so that the corresponding scenes correspond to the corresponding clock sources. However, such manual configuration file replacement is cumbersome and time consuming.
Disclosure of Invention
The application provides a method and a system for switching a double clock source, which are used for solving the problem that the clock source needs to be manually switched in the prior art.
In a first aspect, the present application provides a method for switching a dual clock source, applied to a controller of a circuit board, wherein the circuit board is provided with an environment detection circuit for detecting a self operating environment, a first clock source and a phase-locked loop circuit, a configuration port of the phase-locked loop circuit is connected to the controller, the circuit board can be installed on a host computer in a pluggable manner, the host computer is provided with a second clock source, the first clock source is used for providing a clock signal for the circuit board in a single board operating state, the second clock source is used for providing a clock signal for the circuit board in a complete machine operating state and the host computer, the first clock source and the second clock source can both input the clock signal to the phase-locked loop circuit, the method includes:
acquiring the operating environment parameters of the circuit board detected by the environment detection circuit, detecting whether the operating environment parameters contain operating signals transmitted by the whole machine, and acquiring a detection result;
if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source;
and if the detection result is yes, configuring the phase-locked loop circuit to switch and lock the second clock source.
Optionally, before obtaining the operating environment parameter of the circuit board detected by the environment detection circuit, the method further includes:
the phase-locked loop circuit is configured in advance to lock the first clock source, and a first parameter of a clock pulse signal output by the phase-locked loop circuit is detected;
determining that the first parameter of the output is the same as a parameter of the first clock source, determining that the phase-locked loop circuit has locked the first clock source.
Optionally, if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source, including:
if the detection result is negative, the phase-locked loop circuit is configured to be switched to the first clock source, and a second parameter of a clock pulse signal output by the phase-locked loop circuit is determined;
and judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit is switched and locks the first clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source.
Optionally, the second parameter and the parameter of the first clock source comprise frequency and cycle jitter, respectively;
judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit has switched and locked the first clock source, otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source, including:
judging whether the first frequency of the clock pulse signal output by the phase-locked loop circuit is the same as the frequency of the first clock source or not, and the first period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as the period jitter of the first clock source;
if so, determining that the phase-locked loop circuit is switched and locking the first clock source;
otherwise, the phase-locked loop circuit is reconfigured to switch and lock the first clock source.
Optionally, if the detection result is yes, configuring the phase-locked loop circuit to switch and lock the second clock source includes:
if the detection result is yes, the phase-locked loop circuit is configured to be switched to the second clock source, and a third parameter of the clock pulse signal output by the phase-locked loop circuit is determined;
and judging whether the third parameter output by the phase-locked loop circuit is the same as the parameter of the second clock source, if so, determining that the phase-locked loop circuit is switched and locked the second clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the second clock source.
Optionally, the third parameter and the parameter of the second clock source respectively include frequency and cycle jitter;
judging whether the third parameter output by the phase-locked loop circuit is the same as the parameter of the second clock source, if so, determining that the phase-locked loop circuit has switched and locked the second clock source, otherwise, reconfiguring the phase-locked loop circuit to switch and lock the second clock source, including:
judging whether a second frequency of the clock pulse signal output by the phase-locked loop circuit is the same as the frequency of the second clock source, and a second period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as the period jitter of the second clock source;
if so, determining that the phase-locked loop circuit is switched and locking the second clock source;
otherwise, the phase-locked loop circuit is reconfigured to switch and lock the second clock source.
In a second aspect, the present application provides a dual clock source switching system, including:
the circuit board can be installed on the host in a pluggable mode;
the circuit board is provided with a controller, an environment detection circuit, a phase-locked loop circuit and a first clock source; the host is provided with a second clock source; the configuration port of the phase-locked loop circuit is connected with the controller, and the first clock source provides a clock signal for the circuit board in the running state of the single board and inputs the clock signal to the phase-locked loop circuit; the second clock source provides clock signals for the circuit board and the host in the running state of the whole machine and inputs the clock signals to the phase-locked loop circuit;
the environment detection circuit is used for acquiring the operating environment parameters of the circuit board and transmitting the operating environment parameters to the controller;
the controller is used for acquiring the operating environment parameters of the circuit board detected by the environment detection circuit, detecting whether the operating environment parameters contain operating signals transmitted by the whole machine, and acquiring a detection result; if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source; if the detection result is yes, the phase-locked loop circuit is configured to switch and lock the second clock source;
the phase-locked loop circuit is used for switching and locking the first clock source according to the configuration of the controller, or switching and locking the second clock source according to the configuration of the controller.
Optionally, the controller is further configured to pre-configure the phase-locked loop circuit to lock the first clock source, and detect a first parameter of a clock pulse signal output by the phase-locked loop circuit; determining that the first parameter of the output is the same as a parameter of the first clock source, determining that the phase-locked loop circuit has locked the first clock source.
Optionally, the controller is specifically configured to, if the detection result is negative, configure the phase-locked loop circuit to switch to the first clock source, and determine a second parameter of the clock pulse signal output by the phase-locked loop circuit; and judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit is switched and locks the first clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source.
Optionally, the second parameter and the parameter of the first clock source comprise frequency and cycle jitter, respectively;
the controller is specifically configured to determine whether a first frequency of the clock pulse signal output by the phase-locked loop circuit is the same as a frequency of the first clock source, and a first period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as a period jitter of the first clock source; if so, determining that the phase-locked loop circuit is switched and locking the first clock source; otherwise, the phase-locked loop circuit is reconfigured to switch and lock the first clock source.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the method provided by the embodiment of the application, the operating environment parameters of the circuit board detected by the environment detection circuit are obtained, whether the operating environment parameters contain operating signals transmitted by the whole machine or not is detected, the detection result is obtained, if the detection result is negative, the phase-locked loop circuit is configured to switch and lock the first clock source, if the detection result is positive, the phase-locked loop circuit is configured to switch and lock the second clock source, the first clock source or the second clock source is automatically switched and locked according to the detection result, manual operation is avoided, and the working efficiency is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flow chart of a dual clock source switching method in an embodiment of the present application;
FIG. 2 is a flow chart illustrating an embodiment of a method for pre-configuring a PLL circuit to lock a first clock source;
FIG. 3 is a flow chart illustrating an embodiment of a method for configuring a PLL circuit to switch and lock a first clock source;
FIG. 4 is a schematic flow chart illustrating a configuration of a PLL circuit for switching and locking a second clock source according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating a specific implementation of a dual clock source switching method in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a dual clock source switching system in the embodiment of the present application;
FIG. 7 is a schematic diagram of a circuit board structure according to an embodiment of the present application;
fig. 8 is a schematic diagram of a host structure in the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
A first embodiment of the present application provides a method for switching a dual clock source, where the method is applied to a controller of a circuit board, where the circuit board is provided with an environment detection circuit for detecting a running environment of the circuit board, a first clock source, and a phase-locked loop circuit, a configuration port of the phase-locked loop circuit is connected to the controller, the circuit board can be installed on a host in a pluggable manner, the host is provided with a second clock source, the first clock source is used to provide a clock signal for the circuit board in a single board running state, the second clock source is used to provide a clock signal for the circuit board in a complete machine running state and the host, and both the first clock source and the second clock source can input the clock signal to the phase-locked loop circuit, and specifically, the method is implemented as shown in fig. 1:
the running state of the circuit board in the application refers to the condition that the circuit board is not installed on the host machine and is in the running state, and the running state of the whole machine in the application refers to the condition that the circuit board is installed on the host machine and both the circuit board and the host machine are in the running state.
The operation signal transmitted by the complete machine is a power-on signal of the complete machine or a trigger signal about to start the complete machine.
In a specific embodiment, before obtaining the operating environment parameter of the circuit board detected by the environment detection circuit, the controller needs to pre-configure the phase-locked loop circuit to lock the first clock source, so as to ensure that the circuit board can normally operate, as specifically shown in fig. 2:
Specifically, the first parameter of the clock pulse signal output by the phase-locked loop circuit includes frequency and cycle jitter.
The controller may be a Complex Programmable Logic Device (CPLD), a Micro Controller Unit (MCU), a Central Processing Unit (CPU), or the like.
Specifically, the parameters of the first clock source comprise frequency and cycle jitter, and when the frequency of the first parameter is determined to be the same as the frequency of the parameters of the first clock source and the cycle jitter of the first parameter is determined to be the same as the cycle jitter of the first clock source, it is determined that the phase-locked loop circuit locks the first clock source, and at the moment, the circuit board can normally operate; otherwise, determining that the phase-locked loop circuit is unlocked, outputting a signal abnormity prompt, and reconfiguring the phase-locked loop circuit to lock the first clock source until the circuit board can normally operate.
And 102, if the detection result is negative, configuring a phase-locked loop circuit to switch and lock the first clock source.
In a specific embodiment, if the detection result is negative, a specific implementation process of switching and locking the first clock source by the phase-locked loop circuit is configured, as shown in fig. 3:
and step 301, if the detection result is negative, configuring the phase-locked loop circuit to switch to the first clock source, and determining a second parameter of the clock pulse signal output by the phase-locked loop circuit.
Specifically, the controller does not obtain the operation parameters transmitted by the complete machine through the environment detection circuit, configures the phase-locked loop circuit to switch to the first clock source, and receives and determines second parameters of the clock pulse signal of the first clock source output through the phase-locked loop circuit, where the second parameters include: the frequency and period of the clock pulse signal are dithered.
In one embodiment, the controller determines whether a first frequency of the clock pulse signal output by the phase-locked loop circuit is the same as a frequency of the first clock source, and a first period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as a period jitter of the first clock source; if yes, determining that the phase-locked loop circuit is switched and locks the first clock source, and enabling the circuit board to normally operate at the moment; otherwise, determining that the phase-locked loop circuit is unlocked, outputting a signal abnormity prompt, reconfiguring the phase-locked loop circuit to switch and lock the first clock source until the circuit board can normally operate.
And 103, if the detection result is yes, configuring the phase-locked loop circuit to switch and lock the second clock source.
In a specific embodiment, if the detection result is yes, a specific implementation process of switching and locking the second clock source by the phase-locked loop circuit is configured, as shown in fig. 4:
Specifically, the controller acquires the operation parameters transmitted by the complete machine through the environment detection circuit, configures the phase-locked loop circuit to switch to the second clock source, and receives and determines a third parameter of the clock pulse signal of the second clock source output by the phase-locked loop circuit, where the third parameter includes: the frequency and period of the clock pulse signal are dithered.
In a specific embodiment, the controller determines whether a second frequency of the clock pulse signal output by the phase-locked loop circuit is the same as a frequency of the second clock source, and a second period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as a period jitter of the second clock source; if yes, determining that the phase-locked loop circuit is switched and locking a second clock source, and at the moment, the circuit board and the complete machine commonly use the second clock source and normally operate; otherwise, determining that the phase-locked loop circuit is unlocked, outputting a signal abnormity prompt, reconfiguring the phase-locked loop circuit to switch and lock the second clock source until the whole machine and the circuit board can normally operate.
Specifically, when the second frequency of the clock pulse signal output by the phase-locked loop circuit is the same as the frequency of the second clock source, and the second period jitter of the clock pulse signal output by the phase-locked loop circuit is different from the period jitter of the second clock source, determining that the phase-locked loop circuit is unlocked and outputting a signal abnormal prompt; or when the second frequency of the clock pulse signal output by the phase-locked loop circuit is different from the frequency of the second clock source and the second period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as the period jitter of the second clock source, determining that the phase-locked loop circuit is unlocked and outputting a signal abnormal prompt; or when the second frequency of the clock pulse signal output by the phase-locked loop circuit is different from the frequency of the second clock source, and the second period jitter of the clock pulse signal output by the phase-locked loop circuit is different from the period jitter of the second clock source, determining that the phase-locked loop circuit is unlocked and outputting a signal abnormal prompt.
When any one of the two conditions is different or both conditions are different, the clock pulse signal is invalid, the phase-locked loop circuit is determined to be unlocked, the output signal is abnormally prompted, and the phase-locked loop circuit is reconfigured to switch and lock the second clock source until the whole machine and the circuit board can normally operate.
Specifically, the overall description of the dual clock source switching method is performed with reference to fig. 5, which specifically includes the following steps:
And step 505, prompting that the second clock source is invalid and continuing to detect.
And step 507, the whole machine enters an operating state.
In step 509, it is detected whether the phase-locked loop circuit is in a locked state, if so, step 510 is executed, otherwise, step 511 is executed.
According to the method provided by the embodiment of the application, the operating environment parameters of the circuit board detected by the environment detection circuit are obtained, whether the operating environment parameters contain operating signals transmitted by the whole machine or not is detected, the detection result is obtained, if the detection result is negative, the phase-locked loop circuit is configured to switch and lock the first clock source, if the detection result is positive, the phase-locked loop circuit is configured to switch and lock the second clock source, the first clock source or the second clock source is automatically switched and locked according to the detection result, manual operation is avoided, and the working efficiency is improved.
A second embodiment of the present application provides a dual clock source switching system, and specific implementation of the system may refer to the description of the method embodiment, and repeated details are not repeated, as shown in fig. 6, the system includes: a circuit board 601 and a host 602, the circuit board 601 being capable of being removably mounted to the host 602.
Specifically, as shown in fig. 7, the circuit board 601 includes: the controller 701, the environment detection circuit 702, the phase-locked loop circuit 703 and the first clock source 704, the controller 701, the environment detection circuit 702, the phase-locked loop circuit 703 and the first clock source 704 are disposed on the circuit board 601, a configuration port of the phase-locked loop circuit 703 is connected to the controller 701, the first clock source 704 provides a clock signal for the circuit board 601 in the single board running state and inputs the clock signal to the phase-locked loop circuit 703, as shown in fig. 8, the host 602 is provided with a second clock source 801, and the second clock source 801 provides a clock signal for the circuit board 601 in the complete machine running state and the host 602 and inputs the clock signal to the phase-locked loop circuit 703;
the environment detection circuit 702 is configured to acquire an operating environment parameter of the circuit board 601 and transmit the operating environment parameter to the controller 701;
the controller 701 is configured to acquire an operating environment parameter of the circuit board 601 detected by the environment detection circuit 702, detect whether the operating environment parameter includes an operating signal transmitted by the whole device, and acquire a detection result; if the detection result is negative, the pll 703 switches and locks the first clock source 704; if the detection result is yes, the phase-locked loop circuit 703 is configured to switch and lock the second clock source 801;
the phase-locked loop circuit 703 is configured to switch and lock the first clock source 704 according to the configuration of the controller 701, or switch and lock the second clock source 801 according to the configuration of the controller.
In a specific embodiment, the controller 701 is further configured to pre-configure the phase-locked loop circuit 703 to lock the first clock source 704, and detect a first parameter of a clock pulse signal output by the phase-locked loop circuit 703; determining that the output first parameter is the same as the parameter of the first clock source 704, it is determined that the phase-locked loop circuit 703 has locked the first clock source 704.
In an embodiment, the controller 701 is specifically configured to, if the detection result is negative, configure the pll circuit 703 to switch to the first clock source 704, and determine a second parameter of the clock pulse signal output by the pll circuit 703; judging whether the second parameter output by the pll 703 is the same as the parameter of the first clock source 704, if so, determining that the pll 703 has switched and locked the first clock source 704, otherwise, reconfiguring the pll 703 to switch and lock the first clock source 704.
In one embodiment, the second parameter and the parameter of the first clock source 704 include frequency and cycle jitter, respectively;
the controller 701 is specifically configured to determine whether a first frequency of the clock pulse signal output by the phase-locked loop circuit 703 is the same as a frequency of the first clock source 704, and a first period jitter of the clock pulse signal output by the phase-locked loop circuit 703 is the same as a period jitter of the first clock source 704; if yes, it is determined that the pll 703 has switched and locked the first clock source 704; otherwise, the reconfigured phase-locked loop circuit 703 switches and locks the first clock source 704.
Specifically, when the second frequency of the clock pulse signal output by the phase-locked loop circuit 703 is the same as the frequency of the second clock source 704, and the second period jitter of the clock pulse signal output by the phase-locked loop circuit 703 is different from the period jitter of the second clock source 704, it is determined that the phase-locked loop circuit 703 is out of lock, and a signal abnormal prompt is output; or, when the second frequency of the clock pulse signal output by the phase-locked loop circuit 703 is different from the frequency of the second clock source 704, and the second period jitter of the clock pulse signal output by the phase-locked loop circuit 703 is the same as the period jitter of the second clock source 704, determining that the phase-locked loop circuit is unlocked, and outputting a signal abnormal prompt; or, when the second frequency of the clock pulse signal output by the phase-locked loop circuit 703 is different from the frequency of the second clock source 704, and the second period jitter of the clock pulse signal output by the phase-locked loop circuit 703 is different from the period jitter of the second clock source 704, it is determined that the phase-locked loop circuit 703 is out of lock, and an abnormal signal prompt is output.
That is, when the second frequency of the clock pulse signal output by the pll circuit 703 is different from the frequency of the second clock source 704, and the second period jitter of the clock pulse signal output by the pll circuit 703 is different from the period jitter of the second clock source 704, both of these two conditions are different, which indicates that the clock pulse signal is invalid, it is determined that the pll circuit 703 is out of lock, and the output signal is abnormal, and the pll circuit 703 is reconfigured to switch and lock the second clock source until the whole device and the circuit board 601 can operate normally.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A double clock source switching method is characterized in that the method is applied to a controller of a circuit board, wherein the circuit board is provided with an environment detection circuit for detecting the running environment of the circuit board, a first clock source and a phase-locked loop circuit, a configuration port of the phase-locked loop circuit is connected with the controller, the circuit board can be installed on a host in a pluggable manner, the host is provided with a second clock source, the first clock source is used for providing clock signals for the circuit board in a single-board running state, the second clock source is used for providing clock signals for the circuit board in a complete machine running state and the host, and the first clock source and the second clock source can input the clock signals to the phase-locked loop circuit, the method comprises the following steps:
acquiring the operating environment parameters of the circuit board detected by the environment detection circuit, detecting whether the operating environment parameters contain operating signals transmitted by the whole machine, and acquiring a detection result;
if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source;
and if the detection result is yes, configuring the phase-locked loop circuit to switch and lock the second clock source.
2. The method according to claim 1, wherein before obtaining the operating environment parameters of the circuit board detected by the environment detection circuit, the method further comprises:
the phase-locked loop circuit is configured in advance to lock the first clock source, and a first parameter of a clock pulse signal output by the phase-locked loop circuit is detected;
determining that the first parameter of the output is the same as a parameter of the first clock source, determining that the phase-locked loop circuit has locked the first clock source.
3. The method according to claim 2, wherein if the detection result is negative, configuring the pll circuit to switch and lock the first clock source comprises:
if the detection result is negative, the phase-locked loop circuit is configured to be switched to the first clock source, and a second parameter of a clock pulse signal output by the phase-locked loop circuit is determined;
and judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit is switched and locks the first clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source.
4. A dual clock source switching method according to claim 3, wherein the second parameter and the parameter of the first clock source respectively include frequency and cycle jitter;
judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit has switched and locked the first clock source, otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source, including:
judging whether the first frequency of the clock pulse signal output by the phase-locked loop circuit is the same as the frequency of the first clock source or not, and the first period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as the period jitter of the first clock source;
if so, determining that the phase-locked loop circuit is switched and locking the first clock source;
otherwise, the phase-locked loop circuit is reconfigured to switch and lock the first clock source.
5. The method according to claim 2, wherein if the detection result is yes, configuring the pll circuit to switch and lock the second clock source comprises:
if the detection result is yes, the phase-locked loop circuit is configured to be switched to the second clock source, and a third parameter of the clock pulse signal output by the phase-locked loop circuit is determined;
and judging whether the third parameter output by the phase-locked loop circuit is the same as the parameter of the second clock source, if so, determining that the phase-locked loop circuit is switched and locked the second clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the second clock source.
6. The dual clock source switching method according to claim 5, wherein the third parameter and the parameter of the second clock source respectively comprise frequency and period jitter;
judging whether the third parameter output by the phase-locked loop circuit is the same as the parameter of the second clock source, if so, determining that the phase-locked loop circuit has switched and locked the second clock source, otherwise, reconfiguring the phase-locked loop circuit to switch and lock the second clock source, including:
judging whether a second frequency of the clock pulse signal output by the phase-locked loop circuit is the same as the frequency of the second clock source, and a second period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as the period jitter of the second clock source;
if so, determining that the phase-locked loop circuit is switched and locking the second clock source;
otherwise, the phase-locked loop circuit is reconfigured to switch and lock the second clock source.
7. A dual clock source switching system, comprising:
the circuit board can be installed on the host in a pluggable mode;
the circuit board is provided with a controller, an environment detection circuit, a phase-locked loop circuit and a first clock source; the host is provided with a second clock source; the configuration port of the phase-locked loop circuit is connected with the controller, and the first clock source provides a clock signal for the circuit board in the running state of the single board and inputs the clock signal to the phase-locked loop circuit; the second clock source provides clock signals for the circuit board and the host in the running state of the whole machine and inputs the clock signals to the phase-locked loop circuit;
the environment detection circuit is used for acquiring the operating environment parameters of the circuit board and transmitting the operating environment parameters to the controller;
the controller is used for acquiring the operating environment parameters of the circuit board detected by the environment detection circuit, detecting whether the operating environment parameters contain operating signals transmitted by the whole machine, and acquiring a detection result; if the detection result is negative, configuring the phase-locked loop circuit to switch and lock the first clock source; if the detection result is yes, the phase-locked loop circuit is configured to switch and lock the second clock source;
the phase-locked loop circuit is used for switching and locking the first clock source according to the configuration of the controller, or switching and locking the second clock source according to the configuration of the controller.
8. The dual clock source switching system of claim 7, wherein the controller is further configured to pre-configure the phase-locked loop circuit to lock the first clock source, and detect a first parameter of a clock pulse signal output by the phase-locked loop circuit; determining that the first parameter of the output is the same as a parameter of the first clock source, determining that the phase-locked loop circuit has locked the first clock source.
9. The system according to claim 8, wherein the controller is specifically configured to, if the detection result is negative, configure the pll circuit to switch to the first clock source, and determine a second parameter of the clock pulse signal output by the pll circuit; and judging whether the second parameter output by the phase-locked loop circuit is the same as the parameter of the first clock source, if so, determining that the phase-locked loop circuit is switched and locks the first clock source, and otherwise, reconfiguring the phase-locked loop circuit to switch and lock the first clock source.
10. The dual clock source switching system of claim 9, wherein the second parameter and the parameter of the first clock source comprise frequency and cycle jitter, respectively;
the controller is specifically configured to determine whether a first frequency of the clock pulse signal output by the phase-locked loop circuit is the same as a frequency of the first clock source, and a first period jitter of the clock pulse signal output by the phase-locked loop circuit is the same as a period jitter of the first clock source; if so, determining that the phase-locked loop circuit is switched and locking the first clock source; otherwise, the phase-locked loop circuit is reconfigured to switch and lock the first clock source.
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