CN114284374B - Application of zinc titanate in crystalline silicon solar cell - Google Patents

Application of zinc titanate in crystalline silicon solar cell Download PDF

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CN114284374B
CN114284374B CN202111597591.1A CN202111597591A CN114284374B CN 114284374 B CN114284374 B CN 114284374B CN 202111597591 A CN202111597591 A CN 202111597591A CN 114284374 B CN114284374 B CN 114284374B
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crystalline silicon
film layer
transparent conductive
zinc titanate
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CN114284374A (en
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钟思华
王广一
张文春
焦泽栋
贾保平
毛日骏
岳宗毅
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Jiangsu Ocean University
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Abstract

The invention relates to a crystalline silicon solar cell, in particular to application of zinc titanate in the crystalline silicon solar cell. The zinc titanate film is used as an electron selection layer in the crystalline silicon solar cell, the zinc titanate film has an energy band structure matched with a crystalline silicon substrate, and has a small conduction band step and a large valence band step when being contacted with the crystalline silicon, so that electrons and blocking holes can be effectively selected on a contact interface, zinc titanate/crystalline silicon heterogeneous contact is realized, and excellent electron selection performance is shown. The zinc titanate film also has a lower work function, and when the zinc titanate film is contacted with the crystalline silicon substrate, the crystalline silicon energy band is induced to bend, so that the transmission of electrons from the crystalline silicon to the zinc titanate direction is facilitated.

Description

Application of zinc titanate in crystalline silicon solar cell
Technical Field
The invention relates to a crystalline silicon solar cell, in particular to application of zinc titanate in the crystalline silicon solar cell.
Background
Carrier selective contact is a research hotspot of Gao Xiaojing silicon solar cells, aiming at achieving efficient separation and collection of photogenerated electron-hole pairs. Thus, the performance of carrier selective contact directly affects the performance of the solar cell. Carrier-selective contacts include electron-selective contacts that facilitate electron transport but block hole transport and hole-selective contacts that are the opposite.
Currently, the electronic selective contact of crystalline silicon solar cells is realized mainly by heavy doping. Comprising (1) a passivated emitter and backside (PERC) cell: and carrying out high-temperature phosphorus diffusion in the crystalline silicon substrate to form an n-type heavily doped crystalline silicon thin layer, wherein the high-temperature phosphorus diffusion area is used as electron selective contact. (2) intrinsic thin layer Heterojunction (HIT) cells: the method mainly uses a heavily doped n-type amorphous silicon film grown on the surface of the crystalline silicon as an electron selective contact. (3) tunneling oxide passivation contact cell (TOPCon): the ultra-thin silicon oxide is grown on the surface of the crystalline silicon to serve as a tunneling layer, and meanwhile, the ultra-thin silicon oxide is matched with a heavily doped n-type microcrystalline silicon or polycrystalline silicon film to serve as electron selective contact.
The above battery structures all need to rely on heavily doped amorphous silicon, polycrystalline silicon or microcrystalline silicon to realize electron selective contact, and although the battery structures all show higher photoelectric conversion efficiency, the battery structures have higher defect state density and narrower forbidden band width no matter the amorphous silicon film, the polycrystalline silicon film or the microcrystalline silicon film, so that obvious parasitic light absorption is easy to cause, the improvement of spectral response is restricted, the photo-generated current of the device is reduced, and further the conversion efficiency is influenced. In addition, the doping process also needs high temperature and highly toxic gases (borane, phosphane and silane) for growth, and has complex process and high cost.
Based on the above-mentioned problems, it is necessary to provide an electron selective contact material for crystalline silicon solar cells.
Disclosure of Invention
The invention aims to provide application of zinc titanate in a crystalline silicon solar cell so as to solve the technical problems.
According to one of the technical schemes of the invention, zinc titanate is applied to a crystalline silicon solar cell.
Further, zinc titanate is used as an electron selection layer in the crystalline silicon solar cell.
Further, the electron selection layer has a thickness of 1-100nm.
According to the second technical scheme, the crystalline silicon solar cell sequentially comprises a lower metal electrode layer (500 nm-1 mu m), a lower transparent conductive film layer (10-100 nm), a zinc titanate electron selection layer (1-100 nm), a lower passivation film layer (0.5-10 nm), a crystalline silicon substrate (10-300 mu m), an upper passivation film layer (0.5-10 nm), a hole selection layer (1-100 nm), an upper transparent conductive film layer (10-100 nm) and an upper metal electrode layer (500-1 mu m) from bottom to top.
The transparent conductive film has high light transmittance and high electrical conductivity, and simultaneously has the function of reducing light reflection. The electron (hole) selection layer can selectively only allow electrons (holes) to pass through and block holes (electrons) from passing through, so that carrier separation is better realized; the passivation layer is used for inhibiting surface defects of the crystalline silicon substrate.
Further, the lower passivation film layer covers the lower surface of the whole crystalline silicon substrate, the zinc titanate electron selection layer covers the whole lower passivation film layer, the lower transparent conductive film layer covers the whole zinc titanate electron selection layer, and the lower metal electrode layer covers the whole lower transparent conductive film; the upper passivation film layer covers the upper surface of the whole crystalline silicon substrate, the hole selection layer covers the whole upper passivation film layer, the upper transparent conductive film layer covers the upper surface of the whole hole selection layer, and the upper metal electrode layer partially covers the upper transparent conductive film.
Further, the crystal silicon substrate is N-type or P-type crystal silicon, and the thickness is 10-300 mu m;
further, the lower passivation film layer and the upper passivation film layer are the same or different and are selected from any one or two of the following films: a silicon oxide film, a hydrogenated amorphous silicon film, an aluminum oxide film, and a silicon nitride film; the thickness of the lower passivation film layer and the upper passivation film layer is 0.5-10nm; the lower passivation film layer mainly plays a role in passivating the surface defects of the crystalline silicon.
Further, the hole selection layer is made of molybdenum oxide, heavily doped P-type amorphous silicon, microcrystalline silicon or silicon carbide, and the thickness is 1-100nm;
further, the thickness of the zinc titanate electron selection layer is 1-100nm;
further, the lower transparent conductive film layer and the upper transparent conductive film layer are the same or different and are selected from any one or two of the following films: the thickness of the lower transparent conductive film layer and the upper transparent conductive film layer is 10-100nm;
further, the lower metal electrode layer is an aluminum electrode or a silver electrode, and the upper metal electrode layer is an aluminum electrode or a silver electrode.
According to a third technical scheme, the preparation method of the crystalline silicon solar cell comprises the following steps: cleaning the crystal silicon substrate, then, surface texturing, and then, sequentially depositing a lower passivation film layer, a zinc titanate electron selection layer, a lower transparent conductive film layer and a lower metal electrode layer on the lower surface of the crystal silicon substrate; and sequentially depositing an upper passivation film layer, a hole selection layer, an upper transparent conductive film layer and an upper metal electrode layer on the upper surface of the crystalline silicon substrate.
Further, the preparation of the lower metal electrode layer, the lower transparent conductive film layer, the zinc titanate electron selection layer, the lower passivation film layer, the upper passivation film layer, the hole selection layer, the upper transparent conductive film layer and the upper metal electrode layer adopts any one or more of the following methods: thermal evaporation, solution process, vapor deposition process, and magnetron sputtering process.
Compared with the prior art, the invention has the beneficial effects that:
zinc titanate is used as an electron selective contact material, and firstly has a wide optical band gap (Eg >3 eV), so that parasitic absorption is reduced, and photo-generated current is increased. And secondly, the carrier has a lower work function (Eg is less than 4.2 eV), better energy band matching is obtained, and better carrier transmission is realized. Finally, the excellent electron selection function can be realized by simple preparation (such as thermal evaporation or solution spin coating), and the preparation cost and the dangers in the preparation process are low.
According to the invention, zinc titanate is used as an electron selection layer in the crystalline silicon solar cell, the zinc titanate film has an energy band structure matched with a crystalline silicon substrate, a small conduction band step and a large valence band step are formed when the zinc titanate film is contacted with the crystalline silicon, the small conduction band step can better promote electron transmission for excellent electron selective contact, and the large valence band step can better block hole transmission, so that the zinc titanate is used as the electron selection layer in the crystalline silicon solar cell, electrons can be effectively selected and holes can be blocked on a contact interface (shown in figure 1), and zinc titanate/crystalline silicon heterogeneous contact is realized and excellent electron selection performance is shown. The zinc titanate film also has a lower work function (WF < 4.2 eV), and when the zinc titanate film is contacted with a crystalline silicon substrate, the crystalline silicon energy band is induced to bend, so that the transmission of electrons from the crystalline silicon to the zinc titanate direction is facilitated.
Unlike the traditional method of heavily doping silicon to realize carrier selective transmission, the zinc titanate film has lower work function and larger valence band order compared with a crystalline silicon substrate, can effectively select electrons and block holes on a contact interface, can realize better separation of photon-generated carriers, and has wide band gap, thereby reducing parasitic light absorption and improving photoelectric conversion efficiency.
Drawings
FIG. 1 is a schematic diagram of the contact energy band of a zinc titanate film and a crystalline silicon substrate.
Fig. 2 is a schematic structural diagram of a crystalline silicon solar cell according to embodiment 1 of the present invention, wherein 1 is a crystalline silicon substrate, 2 is a lower passivation film, 3 is a zinc titanate electron selection layer, 4 is a lower transparent conductive film, 5 is a lower metal electrode layer, 6 is an upper passivation film layer, 7 is a hole selection layer, 8 is an upper transparent conductive film, and 9 is an upper metal electrode layer.
Fig. 3 is a current-voltage characteristic curve of the crystalline silicon/zinc titanate thin film/metal contact and the crystalline silicon/metal contact of the crystalline silicon solar cell prepared in example 4 and example 5 of the present invention.
Detailed Description
Various exemplary embodiments of the invention will now be described in detail, which should not be considered as limiting the invention, but rather as more detailed descriptions of certain aspects, features and embodiments of the invention.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In addition, for numerical ranges in this disclosure, it is understood that each intermediate value between the upper and lower limits of the ranges is also specifically disclosed. Every smaller range between any stated value or stated range, and any other stated value or intermediate value within the stated range, is also encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although only preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention. All documents mentioned in this specification are incorporated by reference for the purpose of disclosing and describing the methods and/or materials associated with the documents. In case of conflict with any incorporated document, the present specification will control.
It will be apparent to those skilled in the art that various modifications and variations can be made in the specific embodiments of the invention described herein without departing from the scope or spirit of the invention. Other embodiments will be apparent to those skilled in the art from consideration of the specification of the present invention. The specification and examples of the present invention are exemplary only.
As used herein, the terms "comprising," "including," "having," "containing," and the like are intended to be inclusive and mean an inclusion, but not limited to.
Example 1
The schematic structural diagram of the crystalline silicon solar cell prepared in this embodiment is shown in fig. 2, in which:
1 is a crystalline silicon substrate, in particular an N-type crystalline silicon substrate (the P type has the same technical effect), and the thickness is 300 mu m;
2 is a lower passivation film which covers the lower surface of the whole crystalline silicon substrate and has the thickness of 10nm;
3 is a zinc titanate electron selection layer which covers the whole lower passivation film and has the thickness of 100nm;
4 is a lower transparent conductive film, which covers the whole zinc titanate electron selection layer and has a thickness of 80nm;
5 is a lower metal electrode layer which covers the whole lower transparent conductive film and has the thickness of 500nm;
6 is an upper passivation film layer which covers the upper surface of the whole crystalline silicon substrate and has the thickness of 10nm;
7 is a hole selection layer which covers the whole upper passivation film layer and has the thickness of 100nm;
8 is an upper transparent conductive film which covers the whole hole selection layer, and the surface thickness is 80nm;
9 is an upper metal electrode layer, and the thickness of the transparent conductive film on the covered part is 500nm.
The preparation method comprises the following steps:
(1) Preprocessing the N-type crystalline silicon substrate by a wet chemical method, including polishing, cleaning and texturing; the method comprises the following specific steps: firstly, placing a silicon wafer into a NaOH solution with the concentration of 10%, cleaning for 15min at the temperature of 80 ℃, and removing a damaged layer of the silicon wafer, namely polishing; secondly, placing the silicon wafer with the damage layer removed in 3% KOH alkaline solution, wherein the soaking time is 10min, and carrying out surface random pyramid texturing by utilizing the difference of alkaline solution on different crystal face corrosion rates to form pyramid textured surfaces which are randomly distributed; finally, adopting RCA cleaning process to put the silicon wafer into the mixed aqueous solution of hydrochloric acid and hydrogen peroxide, wherein the solution ratio is HCl: H 2 O 2 :H 2 O=1:1:5, soaking at 80 ℃ for 10min, and removing metal ions.
(2) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the back surface of an N-type crystalline silicon substrate as a reaction gas (specifically provided that the chamber background vacuum is better than 5×10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 deg.C) as the lower passivation film layer.
(3) And (3) growing zinc titanate by using a solution method, and preparing the zinc titanate electron selection layer by controlling the concentration of the zinc titanate precursor solution to be 2mol/L, the spin coating speed to be 8000rmp, the spin coating thickness to be 100nm, the annealing temperature to be 400 ℃ and the annealing time to be 10min, and spin-coating the zinc titanate precursor solution on the intrinsic hydrogenated amorphous silicon film.
(4) Using a magnetron sputtering system with Ar, H 2 As a reaction gas, an 80nm indium tin oxide film was deposited on a zinc titanate film as a lower transparent conductive film (specific conditions are that the chamber background vacuum was better than 7X 10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ) And preparing a metal aluminum electrode on the indium tin oxide film as a lower metal electrode (specifically, a thermal evaporation electrode is used, and the vacuum degree of the chamber is better than 7 multiplied by 10 -4 Pa, at a rate of 0.5 nm/s).
(5) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the N-type crystalline silicon substrate as a reaction gas (specifically, the condition is that the chamber background vacuum is better than 5 multiplied by 10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 ℃ as an upper passivation film layer; preparing molybdenum oxide film on front surface of N-type crystal silicon substrate by thermal evaporation as hole selection layer of the cell structure (specific condition is that vacuum degree of cavity is better than 7×10 -4 Pa, at a rate of 0.1 nm/s).
(6) Preparation of indium tin oxide film (upper transparent conductive film) on molybdenum oxide film (specific condition chamber background vacuum is better than 7×10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ).
(7) The silver paste was printed and sintered to prepare an upper metal electrode partially covered with a transparent conductive film, see fig. 2.
Example 2
(1) Preprocessing the P-type crystalline silicon substrate by a wet chemical method, including polishing, cleaning and texturing; the method comprises the following specific steps: firstly, placing a silicon wafer into a NaOH solution with the concentration of 10%, cleaning for 15min at the temperature of 80 ℃, and removing a damaged layer of the silicon wafer, namely polishing; secondly, placing the silicon wafer with the damage layer removed in 3% KOH alkaline solution, wherein the soaking time is 10min, and carrying out surface random pyramid texturing by utilizing the difference of alkaline solution on different crystal face corrosion rates to form pyramid textured surfaces which are randomly distributed; finally, adopting RCA cleaning process to put the silicon wafer into the mixed aqueous solution of hydrochloric acid and hydrogen peroxide, wherein the solution ratio is HCl: H 2 O 2 :H 2 O=1:1:5, soaking at 80 ℃ for 10min, and removing metal ions.
(2) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the back surface of an N-type crystalline silicon substrate as a reaction gas (specifically provided that the chamber background vacuum is better than 5×10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 deg.C) as the lower passivation filmAnd (3) a film layer.
(3) And (3) growing zinc titanate by using a solution method, and preparing the zinc titanate electron selection layer by controlling the concentration of the zinc titanate precursor solution to be 2mol/L, the spin coating speed to be 8000rmp, the spin coating thickness to be 100nm, the annealing temperature to be 400 ℃ and the annealing time to be 10min, and spin-coating the zinc titanate precursor solution on the intrinsic hydrogenated amorphous silicon film.
(4) Using a magnetron sputtering system with Ar, H 2 As a reaction gas, an 80nm indium tin oxide film was deposited on a zinc titanate film as a lower transparent conductive film (specific conditions are that the chamber background vacuum was better than 7X 10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ) And preparing a metal aluminum electrode on the indium tin oxide film as a lower metal electrode (specifically, a thermal evaporation electrode is used, and the vacuum degree of the chamber is better than 7 multiplied by 10 -4 Pa, at a rate of 0.5 nm/s).
(5) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the N-type crystalline silicon substrate as a reaction gas (specifically, the condition is that the chamber background vacuum is better than 5 multiplied by 10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 ℃ as an upper passivation film layer; preparing molybdenum oxide film on front surface of N-type crystal silicon substrate by thermal evaporation as hole selection layer of the cell structure (specific condition is that vacuum degree of cavity is better than 7×10 -4 Pa, at a rate of 0.1 nm/s).
(6) Preparation of indium tin oxide film (upper transparent conductive film) on molybdenum oxide film (specific condition chamber background vacuum is better than 7×10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ).
(7) Printing silver paste and sintering to prepare an upper metal electrode, wherein the upper metal electrode is partially covered with a transparent conductive film.
Example 3
(1) Preprocessing the N-type crystalline silicon substrate by a wet chemical method, including polishing, cleaning and texturing; the method comprises the following specific steps: firstly, placing a silicon wafer into a NaOH solution with the concentration of 10%, cleaning for 15min at the temperature of 80 ℃, and removing a damaged layer of the silicon wafer, namely polishing; second, the first one is a first one,placing the silicon wafer with the damage layer removed in 3% KOH alkaline solution, soaking for 10min, and carrying out surface random pyramid texturing by utilizing the difference of alkaline solution on corrosion rates of different crystal faces to form pyramid textured surfaces which are randomly distributed; finally, adopting RCA cleaning process to put the silicon wafer into the mixed aqueous solution of hydrochloric acid and hydrogen peroxide, wherein the solution ratio is HCl: H 2 O 2 :H 2 O=1:1:5, soaking at 80 ℃ for 10min, and removing metal ions.
(2) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the back surface of an N-type crystalline silicon substrate as a reaction gas (specifically provided that the chamber background vacuum is better than 5×10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 deg.C) as the lower passivation film layer.
(3) Zinc titanate is grown by using thermal evaporation process, and the vacuum degree of the chamber is better than 6 multiplied by 10 -5 Pa, at a rate of 0.01nm/s. Zinc titanate powder is evaporated on the intrinsic hydrogenated amorphous silicon film to prepare a zinc titanate electron selection layer.
(4) Using a magnetron sputtering system with Ar, H 2 As a reaction gas, an 80nm indium tin oxide film was deposited on a zinc titanate film as a lower transparent conductive film (specific conditions are that the chamber background vacuum was better than 7X 10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ) And preparing a metal aluminum electrode on the indium tin oxide film as a lower metal electrode (specifically, a thermal evaporation electrode is used, and the vacuum degree of the chamber is better than 7 multiplied by 10 -4 Pa, at a rate of 0.5 nm/s).
(5) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the N-type crystalline silicon substrate as a reaction gas (specifically, the condition is that the chamber background vacuum is better than 5 multiplied by 10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 ℃ as an upper passivation film layer; preparing molybdenum oxide film on front surface of N-type crystal silicon substrate by thermal evaporation as hole selection layer of the cell structure (specific condition is that vacuum degree of cavity is better than 7×10 -4 Pa, at a rate of 0.1 nm/s).
(6) Preparation of indium tin oxide film (upper transparent conductive film) on molybdenum oxide film (specific condition chamber background vacuum is better than 7×10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ).
(7) Printing silver paste and sintering to prepare an upper metal electrode, wherein the upper metal electrode is partially covered with a transparent conductive film.
Example 4
(1) Preprocessing the N-type crystalline silicon substrate by a wet chemical method, including polishing and cleaning; the method comprises the following specific steps: firstly, placing a silicon wafer into a NaOH solution with the concentration of 10%, cleaning for 15min at the temperature of 80 ℃, and removing a damaged layer of the silicon wafer, namely polishing; secondly, adopting an RCA cleaning process, putting the silicon wafer into a mixed aqueous solution of hydrochloric acid and hydrogen peroxide, wherein the solution ratio is HCl: H 2 O 2 :H 2 O=1:1:5, soaking at 80 ℃ for 10min, and removing metal ions.
(2) Zinc titanate is grown by using thermal evaporation process, and the vacuum degree of the chamber is better than 6 multiplied by 10 -5 Pa, at a rate of 0.01nm/s. Zinc titanate powder is evaporated on a crystalline silicon substrate to prepare a zinc titanate electron selective layer.
(3) Preparing metal aluminum electrode on zinc titanate film, and matching with mask plate as lower metal electrode (specific condition is that using thermal evaporation to evaporate electrode, vacuum degree of chamber is better than 7×10 -4 Pa, at a rate of 0.5 nm/s).
(4) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the N-type crystalline silicon substrate as a reaction gas (specifically, the condition is that the chamber background vacuum is better than 5 multiplied by 10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 ℃ as an upper passivation film layer; preparing molybdenum oxide film on front surface of N-type crystal silicon substrate by thermal evaporation as hole selection layer of the cell structure (specific condition is that vacuum degree of cavity is better than 7×10 -4 Pa, at a rate of 0.1 nm/s).
(5) Preparation of indium tin oxide film (upper transparent conductive film) on molybdenum oxide film (specific condition chamber background vacuum is better than 7×10 -5 Pa, working pressure of 1.5Pa, sputtering workThe rate was 100W for 30min. ).
(6) Printing silver paste and sintering to prepare an upper metal electrode, wherein the upper metal electrode is partially covered with a transparent conductive film.
Example 5
(1) Preprocessing the N-type crystalline silicon substrate by a wet chemical method, including polishing and cleaning; the method comprises the following specific steps: firstly, placing a silicon wafer into a NaOH solution with the concentration of 10%, cleaning for 15min at the temperature of 80 ℃, and removing a damaged layer of the silicon wafer, namely polishing; secondly, adopting an RCA cleaning process, putting the silicon wafer into a mixed aqueous solution of hydrochloric acid and hydrogen peroxide, wherein the solution ratio is HCl: H 2 O 2 :H 2 O=1:1:5, soaking at 80 ℃ for 10min, and removing metal ions.
(2) Directly preparing a metal aluminum electrode on a crystalline silicon substrate, and matching a mask plate as a lower metal electrode (specifically, using a thermal evaporation electrode, wherein the vacuum degree of a cavity is better than 7×10 -4 Pa, at a rate of 0.5 nm/s).
(3) SiH using Plasma Enhanced Chemical Vapor Deposition (PECVD) 4 、H 2 Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the N-type crystalline silicon substrate as a reaction gas (specifically, the condition is that the chamber background vacuum is better than 5 multiplied by 10 -4 Pa, working pressure 60Pa, radio frequency power 30W, substrate temperature 200 ℃ as an upper passivation film layer; preparing molybdenum oxide film on front surface of N-type crystal silicon substrate by thermal evaporation as hole selection layer of the cell structure (specific condition is that vacuum degree of cavity is better than 7×10 -4 Pa, at a rate of 0.1 nm/s).
(4) Preparation of indium tin oxide film (upper transparent conductive film) on molybdenum oxide film (specific condition chamber background vacuum is better than 7×10 -5 Pa, the working pressure is 1.5Pa, the sputtering power is 100W, and the time is 30min. ).
(5) Printing silver paste and sintering to prepare an upper metal electrode, wherein the upper metal electrode is partially covered with a transparent conductive film.
The current-voltage characteristic curve was measured using TLM (rectangular transmission line method), and the crystalline silicon/zinc titanate thin film/metal contact of the crystalline silicon solar cell prepared in example 4 and example 5 was measuredAnd comparing the current-voltage characteristic curves of the direct contact with the crystalline silicon/metal. The current-voltage curve is shown in FIG. 3, and the crystalline silicon/zinc titanate film/metal contact prepared in the example has good ohmic contact and contact resistivity as low as 16mΩ cm 2 Since low contact resistivity is a necessary condition for forming excellent electron selectivity, a zinc titanate thin film is very promising as an excellent electron selective contact layer for crystalline silicon solar cells.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims (7)

1. The application of zinc titanate in the crystalline silicon solar cell is characterized in that the zinc titanate is used as an electron selection layer in the crystalline silicon solar cell.
2. The use according to claim 1, wherein the electron selection layer has a thickness of 1-100nm.
3. The crystalline silicon solar cell is characterized by sequentially comprising a lower metal electrode layer, a lower transparent conductive film layer, a zinc titanate electron selection layer, a lower passivation film layer, a crystalline silicon substrate, an upper passivation film layer, a hole selection layer, an upper transparent conductive film layer and an upper metal electrode layer from bottom to top.
4. The crystalline silicon solar cell of claim 3, wherein the lower passivation film layer covers the entire lower surface of the crystalline silicon substrate, the zinc titanate electron selection layer covers the entire lower passivation film layer, the lower transparent conductive film layer covers the entire zinc titanate electron selection layer, and the lower metal electrode layer covers the entire lower transparent conductive film; the upper passivation film layer covers the upper surface of the whole crystalline silicon substrate, the hole selection layer covers the whole upper passivation film layer, the upper transparent conductive film layer covers the upper surface of the whole hole selection layer, and the upper metal electrode layer partially covers the upper transparent conductive film.
5. The crystalline silicon solar cell according to claim 3, wherein the crystalline silicon substrate is N-type or P-type crystalline silicon, and has a thickness of 10-300 μm;
the lower passivation film layer and the upper passivation film layer are the same or different and are selected from any one or two of the following films: a silicon oxide film, a hydrogenated amorphous silicon film, an aluminum oxide film, and a silicon nitride film; the thickness of the lower passivation film layer and the upper passivation film layer is 0.5-10nm;
the cavity selection layer is made of molybdenum oxide, heavily doped P-type amorphous silicon, microcrystalline silicon or silicon carbide, and the thickness of the cavity selection layer is 1-100nm; the lower transparent conductive film layer and the upper transparent conductive film layer are the same or different and are selected from any one or two of the following films: the thickness of the lower transparent conductive film layer and the upper transparent conductive film layer is 10-100nm; the lower metal electrode layer is an aluminum electrode or a silver electrode, and the upper metal electrode layer is an aluminum electrode or a silver electrode.
6. A method of manufacturing a crystalline silicon solar cell according to any one of claims 2 to 5, comprising the steps of: cleaning the crystal silicon substrate, then, surface texturing, and then, sequentially depositing a lower passivation film layer, a zinc titanate electron selection layer, a lower transparent conductive film layer and a lower metal electrode layer on the lower surface of the crystal silicon substrate; and sequentially depositing an upper passivation film layer, a hole selection layer, an upper transparent conductive film layer and an upper metal electrode layer on the upper surface of the crystalline silicon substrate.
7. The method for preparing a crystalline silicon solar cell according to claim 6, wherein the preparation of the lower metal electrode layer, the lower transparent conductive film layer, the zinc titanate electron selection layer, the lower passivation film layer, the upper passivation film layer, the hole selection layer, the upper transparent conductive film layer, and the upper metal electrode layer is performed by any one or more of the following methods: thermal evaporation, solution process, vapor deposition process, and magnetron sputtering process.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111900228A (en) * 2020-08-08 2020-11-06 江苏海洋大学 Electron selective contact for crystalline silicon solar cell
CN112970123A (en) * 2018-10-31 2021-06-15 韩国生产技术研究院 Charge selective contact junction silicon solar cell and manufacturing method thereof
CN113270549A (en) * 2021-04-19 2021-08-17 厦门大学 Perovskite solar cell with modified layer structure and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112970123A (en) * 2018-10-31 2021-06-15 韩国生产技术研究院 Charge selective contact junction silicon solar cell and manufacturing method thereof
CN111900228A (en) * 2020-08-08 2020-11-06 江苏海洋大学 Electron selective contact for crystalline silicon solar cell
CN113270549A (en) * 2021-04-19 2021-08-17 厦门大学 Perovskite solar cell with modified layer structure and preparation method thereof

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