CN114284354A - Fin type field effect transistor with stepped negative capacitance layer and preparation method thereof - Google Patents
Fin type field effect transistor with stepped negative capacitance layer and preparation method thereof Download PDFInfo
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- CN114284354A CN114284354A CN202111485216.8A CN202111485216A CN114284354A CN 114284354 A CN114284354 A CN 114284354A CN 202111485216 A CN202111485216 A CN 202111485216A CN 114284354 A CN114284354 A CN 114284354A
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Abstract
The application relates to a fin field effect transistor with a stepped negative capacitance layer and a preparation method thereof. The transistor includes: the semiconductor substrate, cover in the buried oxide layer of semiconductor substrate upper surface, the fin active region that is located buried oxide layer top, fin formula active region is protruding from the first direction on buried oxide layer surface, the length of fin formula active region is the same with the length of semiconductor substrate, the width of fin formula active region is less than the semiconductor substrate width, fin formula active region includes source region, channel region and drain region, the gate oxide has been covered to the upper surface and the left and right sides surface in the first direction of the channel region between the source region and the drain region in fin formula active region, cover three-way negative capacitance layer on the gate oxide, the thickness of three-way negative capacitance layer is the echelonment bodiness or the attenuation along the first direction, covered the metal level on the three-way negative capacitance layer. The improved current in the saturation region and the reduced sub-threshold swing, thereby reducing the power consumption of the transistor and improving the performance of the transistor.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a fin type field effect transistor with a stepped negative capacitance layer and a manufacturing method of the fin type field effect transistor.
Background
With the continuous expansion of the technology scale, the next generation of low power consumption circuits and systems requires new semiconductor devices that can overcome the boltzmann limit and have 60mV/dec below the theoretical limit at room temperature. Negative capacitance fin field effect transistors (finfets) are becoming powerful devices to achieve this breakthrough. However, the amplification effect of the negative-capacitance FinFET on the gate voltage is consistent at the source end and the drain end, and the control capability of the gate on the channel is weak, so that the improvement of the sub-threshold characteristic of the transistor or the reduction of the static power consumption is limited, and the performance improvement of the transistor is limited.
Disclosure of Invention
Therefore, it is necessary to provide a stepped negative capacitor layer fin field effect transistor and a manufacturing method thereof, which can enable the gate voltage to be linearly amplified in the fin channel generation region through the three-way negative capacitor layer, improve the gate control energy recording of the fin field effect transistor, reduce the subthreshold swing of the device, and improve the current in the saturation region.
The utility model provides a ladder negative capacitance layer fin field effect transistor, the transistor includes semiconductor substrate (1), cover in the buried oxide layer (2) of semiconductor substrate (1) upper surface, be located the fin active area of buried oxide layer (2) top, the fin active area is followed fin arch in the first direction on buried oxide layer (2) surface, the length of fin active area with the length of semiconductor substrate (1) is the same, the width of fin active area is less than semiconductor substrate (1) width, the fin active area includes source region (5), channel region and drain region (6), gate oxide (4) have been covered to two side surfaces about the upper surface of the channel region between source region (5) and the drain region (6) of fin active area and the first direction, gate oxide (4) are covered with three-dimensional negative capacitance layer (7), the thickness of the three-way negative capacitance layer is increased or reduced in a step mode along the first direction, and the three-way negative capacitance layer is covered with a metal layer (8).
In one embodiment, the three-way negative capacitance layer (7) is a negative capacitance material.
In one embodiment, the thickness step number of the three-way negative capacitance layer (7) is n, wherein n is more than or equal to 2.
In one embodiment, the metal layer (8) covers the three-way negative capacitor layer (7) and extends to two sides of the buried oxide layer (2) in a second direction perpendicular to the first direction to form a strip-shaped metal layer (8) in the second direction.
A manufacturing method of a stepped negative capacitance layer fin type field effect transistor comprises the following steps:
forming a three-layer structure with a substrate, a buried oxide layer and a top layer by using an intelligent stripping technology;
etching the top layer by using a self-aligned dual-imaging technology, reserving the top layer material which is protruded along the first direction on the surface of the buried oxide layer in a fin-shaped manner, and removing the top layer material except the top layer material which is protruded in the fin-shaped manner;
forming uniform silicon dioxide as a gate oxide layer on the middle section of the fin-shaped protrusion by an in-situ oxidation growth method, wherein the fin-shaped protrusion is divided into three sections;
protecting a gate oxide layer region by using photoresist, and implanting ions with large dose into the surfaces of the other two sections of fin-type bulges in the unprotected region of the gate oxide layer photoresist to form a source region at one section and a drain region at the other section;
protecting the area except the surface of the gate oxide layer by a mask, and depositing a negative capacitance material on the surface of the whole gate oxide layer by utilizing a chemical vapor deposition, atomic layer deposition or sputtering process to form a negative capacitance material layer;
dividing the negative capacitance material layer into a first area and a second area, protecting the area except the second area on the surface of the negative capacitance material layer through a mask, and depositing the negative capacitance material again in the first area by utilizing a chemical vapor deposition, atomic layer deposition or sputtering process to ensure that the thickness of the negative capacitance material layer in the second area is thicker than that of the negative capacitance material layer in the first area, so as to obtain a three-way negative capacitance layer which is thickened or thinned in a stepped manner along the first direction;
and preparing a metal layer on the three-dimensional negative capacitor layer by utilizing a physical vapor deposition process, wherein the metal layer extends to two sides of the oxygen burying layer in a second direction perpendicular to the first direction to form a strip-shaped metal layer in the second direction.
The stepped negative capacitor layer fin field effect transistor comprises a semiconductor substrate (1), a buried oxide layer (2) covering the upper surface of the semiconductor substrate (1), and a fin active region positioned above the buried oxide layer (2), wherein the fin active region protrudes from the surface of the buried oxide layer (2) in a fin mode in the first direction, the length of the fin active region is the same as that of the semiconductor substrate (1), the width of the fin active region is smaller than that of the semiconductor substrate (1), the fin active region comprises a source region (5), a channel region and a drain region (6), the upper surface of the channel region between the source region (5) and the drain region (6) of the fin active region and the left side surface and the right side surface in the first direction cover a gate oxide layer (4), and the gate oxide layer (4) covers a three-way negative capacitor layer (7), the thickness of the three-way negative capacitance layer is increased or reduced in a step mode along the first direction, and the three-way negative capacitance layer is covered with a metal layer (8). According to the transistor, the gate oxide layer is covered with the negative capacitor layer with the step thickness, the gate voltage is variably amplified in different regions and then applied to the surface and two sides of the gate oxide layer by utilizing different voltage amplification effects of the negative capacitor layers with different thicknesses, so that the control capability of the fin field effect transistor on the gate voltage and the channel is improved, the current in a saturation region is improved, the subthreshold swing is reduced, the power consumption of the transistor is reduced, and the performance of the transistor is improved.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a stepped negative capacitance layer FinFET in three dimensional configuration;
FIG. 2 is a cross-sectional view and voltage amplification schematic of an embodiment of a stepped negative capacitor layer FinFET cut vertically down along the middle of a Fin-type active region;
FIG. 3 is a cross-sectional view and voltage amplification of an embodiment of a stepped negative capacitance layer FinFET cut from front to back along a vertical middle portion of a fin active region;
FIG. 4 is a schematic diagram of an alternate embodiment of a 3-step negative capacitor layer FinFET in three dimensional configuration;
FIG. 5 is a schematic perspective view of the step 1 after completion of the step in the method for fabricating a FinFET of an embodiment;
FIG. 6 is a schematic perspective view of the step-negative-capacitance-layer FinFET after step 2 is completed in one embodiment of a method for fabricating a stepped negative-capacitance-layer FinFET;
FIG. 7 is a schematic perspective view of the step-negative-capacitance-layer FinFET after step 3 is performed in the method of fabricating a stepped negative-capacitance-layer FinFET according to an embodiment;
FIG. 8 is a schematic perspective view of the step-negative-capacitance-layer FinFET after step 4 is performed in one embodiment of a method for fabricating a stepped negative-capacitance-layer FinFET;
FIG. 9 is a schematic perspective view of the step-negative-capacitance-layer FinFET after step 5 is performed in one embodiment of a method for fabricating a stepped negative-capacitance-layer FinFET;
fig. 10 is a schematic perspective view of the step-negative-capacitance-layer finfet after step 6 is performed in the method of manufacturing the same according to an embodiment;
fig. 11 is a schematic perspective view of the step-negative-capacitance-layer finfet after step 7 is completed in the method for fabricating the same according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, a stepped negative capacitance layer finfet comprises a semiconductor substrate 1, a buried oxide layer 2 covering an upper surface of the semiconductor substrate 1, wherein:
the gate oxide layer 4 is covered on the gate oxide layer 4, the thickness of the three-way negative capacitor layer 7 is increased or decreased in a stepped manner along the first direction, and the three-way negative capacitor layer is covered with a metal layer 8.
As shown in fig. 2 and 3, a stepped negative capacitance layer (i.e., a three-way negative capacitance layer 7 that is gradually thickened or thinned along a first direction) is disposed on the gate oxide layer 4, and an external electric field causes the negative capacitance layer to generate a polarization characteristic, so as to adjust a voltage amplification characteristic by using different thicknesses. A voltage V is applied to the metal layer 8GThen, through the stepped negative capacitance layer, the voltage from V can be realized at the interface of the gate oxide layer 4 and the three-way negative capacitance layer 7GLChange to VGHThe surface and both sides of the channel region 9 of the fin type can obtain amplified voltage distribution, thereby improving the control capability of the gate voltage.
According to the stepped negative capacitor layer fin type field effect transistor, the three-way negative capacitor layers 7 are arranged above the fin type channels and on the surfaces of the two sides of the fin type channels, the thickness of the three-way negative capacitor layers 7 is changed, so that the amplification effect of different regions on grid voltage is different, and the variable voltage amplification effect can be realized. Linear amplified voltages are formed on the surface and two sides of the fin-type channel region 9 at the same time, the control capability of the grid voltage is greatly improved, the sub-threshold swing amplitude is lower than the theoretical limit value, and the current of a saturation region is greatly improved. Therefore, the power consumption of the transistor is reduced, the performance of the transistor is improved, and meanwhile, the short-channel effect is effectively inhibited.
In one embodiment, the three-way negative capacitance layer 7 is a negative capacitance material.
The negative capacitance material can be hafnium oxide-based ferroelectric, organic ferroelectric, layered bismuth-based ferroelectric, lead zirconate titanate ferroelectric, perovskite-type ferroelectric, lithium niobate-type ferroelectric, tungsten bronze-type ferroelectric, or bismuth-layered perovskite-structure ferroelectric.
In one embodiment, the three-way negative capacitance layer 7 has a thickness step number n, wherein n ≧ 2.
The negative capacitance finned field effect transistor of the three-way negative capacitance layer 7 with 3-level steps (steps 7-1, 7-2 and 7-3 respectively) in fig. 4 can further optimize the voltage amplification effect, and it can be understood that the larger the number of steps of the three-way negative capacitance layer 7 is, the better the voltage amplification effect is, but the larger the number of steps is, the more the number of masks is, the higher the process complexity is, and the number of steps n is preferably less than 5.
In one embodiment, the metal layer 8 covers the three-way negative capacitor layer 7 and extends to two sides of the buried oxide layer 2 in a second direction perpendicular to the first direction to form a strip-shaped metal layer 8 in the second direction.
In one embodiment, the semiconductor substrate 1 and the fin bump are made of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide or indium phosphide.
In one embodiment, the material of the metal layer 8 is aluminum, copper, silver, gold, polysilicon, titanium nitride, tantalum nitride, or the like.
In one embodiment, a method for manufacturing a stepped negative capacitance layer fin field effect transistor comprises the following steps:
And 2, etching the top layer 3 by using a self-aligned dual imaging technology, reserving the top layer material 3 protruding in a fin mode along the first direction of the surface 2 of the buried oxide layer, and removing the top layer material except the top layer material 3 protruding in the fin mode to obtain the structure shown in the figure 6.
And 3, forming uniform silicon dioxide on the middle section of the fin-shaped protrusion as a gate oxide layer 4 by an in-situ oxidation growth method, wherein the fin-shaped protrusion is divided into three sections, so that the structure shown in the figure 7 is obtained.
And 4, protecting the gate oxide layer region by using photoresist, implanting ions with large dose into the surfaces of the other two sections of the fin-type bulges in the photoresist unprotected region of the gate oxide layer 4 to form a source region 5 at one section and a drain region 6 at one section, and obtaining the structure shown in the figure 8.
And 5, protecting the area except the surface of the gate oxide layer 4 through a mask, and depositing a negative capacitance material on the surface of the whole gate oxide layer 4 by utilizing a chemical vapor deposition, atomic layer deposition or sputtering process to form a negative capacitance material layer 7-1 to obtain the structure shown in the figure 9.
And 7, preparing a metal layer 8 on the three-dimensional negative capacitance layer 7 by using a physical vapor deposition process, wherein the metal layer 8 extends to two sides of the buried oxide layer 2 in a second direction perpendicular to the first direction to form a strip-shaped metal layer 8 in the second direction, so that the structure shown in fig. 11 is obtained.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (5)
1. A stepped negative capacitance layer fin field effect transistor comprises a semiconductor substrate (1), a buried oxide layer (2) covering the upper surface of the semiconductor substrate (1), and is characterized in that:
the gate structure comprises a fin active region located above a buried oxide layer (2), wherein the fin active region protrudes in a fin mode from the first direction of the surface of the buried oxide layer (2), the length of the fin active region is the same as that of a semiconductor substrate (1), the width of the fin active region is smaller than that of the semiconductor substrate (1), the fin active region comprises a source region (5), a channel region and a drain region (6), the upper surface of the channel region between the source region (5) and the drain region (6) of the fin active region and the left side surface and the right side surface in the first direction cover a gate oxide layer (4), the gate oxide layer (4) covers a three-way negative capacitor layer (7), the thickness of the three-way negative capacitor layer is thickened or thinned in a stepped mode along the first direction, and a metal layer (8) covers the three-way negative capacitor layer.
2. Transistor according to claim 1, characterized in that said three-way negative capacitance layer (7) is a negative capacitance material.
3. Transistor according to claim 2, characterized in that the three-way negative capacitance layer (7) has a thickness step number n, where n ≧ 2.
4. The transistor of claim 1, wherein the metal layer (8) overlies the three-way negative capacitor layer (7) and extends in a second direction perpendicular to the first direction to two sides of the buried oxide layer (2) to form a stripe-shaped metal layer (8) in the second direction.
5. A method for manufacturing a stepped negative capacitance layer fin type field effect transistor is characterized by comprising the following steps:
forming a three-layer structure with a substrate, a buried oxide layer and a top layer by using an intelligent stripping technology;
etching the top layer by using a self-aligned dual-imaging technology, reserving the top layer material which is protruded along the first direction on the surface of the buried oxide layer in a fin-shaped manner, and removing the top layer material except the top layer material which is protruded in the fin-shaped manner;
forming uniform silicon dioxide as a gate oxide layer on the middle section of the fin-shaped protrusion by an in-situ oxidation growth method, wherein the fin-shaped protrusion is divided into three sections;
protecting a gate oxide layer region by using photoresist, and implanting ions with large dose into the surfaces of the other two sections of fin-type bulges in the unprotected region of the gate oxide layer photoresist to form a source region at one section and a drain region at the other section;
protecting the area except the surface of the gate oxide layer by a mask, and depositing a negative capacitance material on the surface of the whole gate oxide layer by utilizing a chemical vapor deposition, atomic layer deposition or sputtering process to form a negative capacitance material layer;
dividing the negative capacitance material layer into a first area and a second area, protecting the area except the second area on the surface of the negative capacitance material layer through a mask, and depositing the negative capacitance material again in the first area by utilizing a chemical vapor deposition, atomic layer deposition or sputtering process to ensure that the thickness of the negative capacitance material layer in the second area is thicker than that of the negative capacitance material layer in the first area, so as to obtain a three-way negative capacitance layer which is thickened or thinned in a stepped manner along the first direction;
and preparing a metal layer on the three-dimensional negative capacitor layer by utilizing a physical vapor deposition process, wherein the metal layer extends to two sides of the oxygen burying layer in a second direction perpendicular to the first direction to form a strip-shaped metal layer in the second direction.
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