CN114268563A - Method for accurately measuring time-triggered Ethernet transparent clock - Google Patents
Method for accurately measuring time-triggered Ethernet transparent clock Download PDFInfo
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Abstract
The invention discloses a method for accurately measuring a time-triggered Ethernet transparent clock, which divides the transparent clock in the time-triggered Ethernet into three parts for measurement, namely time delay inside a PCF frame sender, time delay inside a PCF frame receiver and one-way link time delay between the PCF frame sender and the PCF frame receiver; and adding the three parts of delay time which are respectively measured to obtain the transparent clock. The method can accurately measure ns level of the key parameter transparent clock required by clock synchronization in the Time Triggered Ethernet (TTE); meanwhile, because the one-way time delay is measured, the method can be applied no matter whether the PHY chips of the sender and the receiver are the same or not.
Description
Technical Field
The invention relates to a method for measuring a transparent clock, in particular to a method for accurately measuring a time-triggered Ethernet transparent clock, and belongs to the field of time-triggered Ethernet communication.
Background
Time triggered ethernet (TTE for short) is a high-precision, high-fault-tolerant real-time ethernet. The SAE AS6802 clock synchronization protocol is used for establishing and maintaining a fault-tolerant clock synchronization strategy for a data Terminal equipment DTE (data Terminal Equipment) and a switch in a TTE network. Meanwhile, the SAE AS6802 clock synchronization protocol also defines algorithms such AS clock synchronization, cluster detection, cold start, restart and the like, and provides an ns-level fault-tolerant self-stabilization mechanism for the TTE network.
A PCF Frame (Protocol Control Frame) is a standard ethernet Frame defined by SAE AS6802 Protocol and dedicated to synchronous services, and is used to transfer key data such AS clock information and link delay between nodes. The transparent clock is the most important information in the PCF frame, the transmission delay from the sender to the receiver of the PCF frame is recorded, and each node carries out a curing algorithm, a compression algorithm and a clock calibration algorithm according to the transparent clock and the arrival time point of the PCF frame to obtain a clock synchronous with the whole network. The precise measurement of the transparent clock has a critical effect on whether the nodes can synchronize and the impact of the synchronization accuracy.
The patent of Hua Shi technology Limited company 'a link delay detection method' (application No. 200510079986.7 publication No. CN100387003C) discloses a method for obtaining the bidirectional delay of a segmented link through loop test of detection messages, and then dividing the bidirectional delay by 2 to obtain the delay of the segmented link. The main disadvantage of the invention is that it can only be used in the case that the ethernet Media Access Controller (MAC) and the physical interface transceiver (PHY) of the sender and the receiver are the same, and is not suitable for the case that the network devices are not symmetrical.
Disclosure of Invention
In view of this, the present invention provides a method for accurately measuring a time-triggered ethernet transparent clock, which uses PCF frame transceiving for a TTE network, and realizes accurate measurement of the ethernet transparent clock by accurate measurement of the one-way link delay from a sender to a receiver, and is suitable for delay measurement between any two TTE nodes (including data terminal equipment DTE or switch).
The technical scheme of the invention is as follows: the method for accurately measuring the time-triggered Ethernet transparent clock divides the transparent clock in the time-triggered Ethernet into three parts for measurement, namely the time delay in the PCF frame sender, the time delay in the PCF frame receiver and the one-way link time delay between the PCF frame sender and the PCF frame receiver; and adding the three parts of delay time which are respectively measured to obtain the transparent clock.
As a preferred mode of the present invention, the method for measuring the one-way link delay between the PCF frame sender and the PCF frame receiver comprises:
when a PCF frame sender sends data to a PHY chip of a PCF frame receiver through the PHY chip, a time reference pulse signal is triggered at the sending time point and is transmitted to the PCF frame receiver through a time reference line;
the time difference between the time point when the receiver of PCF frame receives PCF frame and the time point when the receiver of PCF frame receives the time reference pulse signal is the time delay of the unidirectional link.
As a preferred mode of the invention, the PCF frame sender and the PCF frame receiver are both internally provided with an FPGA and a PHY chip; the PCF frame sender and the PCF frame receiver carry out data transmission through a communication network cable;
the FPGA is internally provided with a PCF frame sending module, a PCF frame receiving module, a PCFControl _ Tx module, a PCFControl _ Rx module, a Wire _ Delay _ Tx module, a Wire _ Delay _ Rx module and an Ethernet MAC module; based on this, the measurement process of the transparent clock is as follows:
the method comprises the following steps: the PCF frame sending module of the PCF frame sender sends PCF frames to the PCFControl _ Tx module of the PCF frame sender, and the PCFControl _ Tx module carries out framing and format conversion on the received PCF frames and provides the PCFControl _ Tx module with the PCF frames for the Ethernet MAC module of the PCF frame sender; the PCF frame sender measures the delay t1 of PCF frame passing through the PCFControl _ Tx module by an internal preset program;
step two: the Ethernet MAC module of the PCF frame sender carries out format conversion after receiving the PCF frame and then sends the PCF frame to the PHY chip of the Ethernet MAC module; the PCF frame sender measures the delay t2 of the PCF frame passing through the Ethernet MAC module by an internal preset program;
meanwhile, the Ethernet MAC module sends an enabling signal to a Wire _ Delay _ Tx module, and the Wire _ Delay _ Tx module triggers a time reference pulse signal to be transmitted to a Wire _ Delay _ Rx module of the PCF frame receiver through a time reference line after receiving the enabling signal;
step three: the PCF frame is sent to a PHY chip of a PCF frame receiver through a communication network line by a PHY chip and then further sent to an Ethernet MAC module of the PCF frame receiver, and the PCF frame receiver measures the delay t4 of the PCF frame passing through the Ethernet MAC module by an internal program;
meanwhile, the PHY chip sends the time point for receiving the PCF frame to a Wire _ Delay _ Rx module of the PHY chip;
step four: the Ethernet MAC module of the PCF frame receiver sends PCF frames to the PCFControl _ Rx module, the PCFControl _ Rx module analyzes and converts the received PCF frames, and the FPGA of the PCF frame receiver measures the delay t5 of the PCF frames passing through the PC FControl _ Rx module by an internal preset program;
step five: the PCF frame receiver measures the time difference T3 between the time point when the own Wire _ Delay _ Rx module receives the PCF frame and the time reference pulse signal;
step six: the Transparent Clock Transparent _ Clock is T1+ T2+ T3+ T4+ T5.
As a preferred mode of the present invention, the PHY chips of the PCF frame sender and the PCF frame receiver are different.
As a preferred mode of the present invention, a communication network line between the PCF frame sender and the PCF frame receiver adopts a cat.6 type non-shielded network line.
Has the advantages that:
the method can accurately measure ns level of the key parameter transparent clock required by clock synchronization in the Time Triggered Ethernet (TTE); meanwhile, because the one-way time delay is measured, the method can be applied no matter whether the PHY chips of the sender and the receiver are the same or not.
Drawings
FIG. 1 is a general block diagram of the present invention;
FIG. 2 is a diagram of SM node to CM node transparent clock measurements;
fig. 3 is a CM node to SM node transparent clock measurement diagram.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1:
the embodiment provides a method for accurately measuring a transparent clock for a Time Triggered Ethernet (TTE) SAE AS6802 clock synchronization protocol, and the method has the advantages of high measurement accuracy, wide application range, simplicity and convenience in measurement and the like.
The PCF frame is short for protocol control frame, and its format is as shown in table 1:
table 1PCF frame format
The transparent clock is the most important information in the PCF frame, and stores the transmission delay of the PCF frame from the sender to the receiver.
The SAE AS6802 protocol divides network devices in a Synchronization process into three types, namely, a Synchronization Master (SM), a Synchronization Slave (SC) and a Compression Master (CM), according to functions.
The implementation block diagram of the measurement method provided in this embodiment is shown in fig. 1, and the sender and the receiver of the PCF frame are made to be a synchronization master SM and a compression master CM in the network device. (any one of the network devices in the synchronization process can be configured to act as either a sender or a receiver)
The SM and the CM have the same structure composition, and are internally provided with an FPGA and a PHY chip; the FPGA is internally provided with a PCF frame sending module, a PCF frame receiving module, a PCFControl _ Tx module, a PCFControl _ Rx module, a Wire _ Delay _ Tx module, a Wire _ Delay _ Rx module and an Ethernet MAC module.
Wherein, the PCF frame sending module is used for sending PCF frames and sending the PCF frames to the PCFControl _ Tx module;
the PCFControl _ Tx module is used for framing the received PCF frame, realizing the conversion of the data format, converting the PCF frame into AXI bus data and interfacing with the Ethernet MAC module.
The Ethernet MAC module further performs format conversion on the received data to realize data exchange with the PHY chip and realize the functions of a media access control sublayer and a logical link control sublayer.
The PCFControl _ Rx module is used for analyzing the received PCF frame, realizing the conversion of data format, converting the AXI bus data received by the Ethernet MAC module into serial data and providing the serial data to the PCF frame receiving module.
The PCF frame receiving module is used for receiving the PCF frame.
The Wire _ Delay _ Tx module receives the Ethernet MAC module transmission enable signal and triggers a time reference pulse signal to the receiver (the Wire _ Delay _ Tx module is connected to the Ethernet MAC module itself and to the counterpart Wire _ Delay _ Rx module).
And the Wire _ Delay _ Rx module (connected with the Ethernet MAC module) obtains the one-way link Delay between the two transmission nodes according to the time difference between the received PCF frame receiving time point and the time point of receiving the time reference pulse signal.
The PCF frame is sent by a PCF frame sending module as a sender, is subjected to PCFControl _ Tx module framing and format conversion, is provided for an Ethernet MAC module, is further subjected to format conversion by the Ethernet MAC module, and is sent to a PHY chip of a receiver through a CAT.6 network cable after being subjected to the PHY chip; the receiving party enters the PCF frame receiving module through the Ethernet MAC module and the analysis and conversion of the PCFControl _ Rx module, and the PHY chip sends the receiving time point to the Wire _ Delay _ Rx module. The Wire _ Delay _ Tx module triggers a time reference pulse signal at the PCF frame sending time point, and transmits the time reference pulse signal to the receiving party Wire _ Delay _ Rx module through a time reference line. The Wire _ Delay _ Rx module calculates a one-way link Delay value through a receiving time point and a receiving time reference pulse signal time point sent by the PHY chip.
Example 2:
in this embodiment, specifically, the FPGA chip is xc7z035ffg676-2 chip of Xilinx corporation; the PHY chip 1 is 88E1518 chip of MARVELL company, and the PHY chip 2 is RTL8211FD chip of RELTEK company (namely, the physical interface transceivers PHY of the receiver and the sender are different); the communication network cable selects CAT.6 six-type non-shielding network cable; the PCF frame is specifically a CS frame (cold start frame); the actual measurement results are as follows:
as shown in fig. 2, the SM-to-CM transparent clock measurement flow is that, at this time, the SM node is a sender, and the CM node is a receiver, specifically:
PCF frame sending module of SM node sends PCF frame to PCFControl _ Tx module, PCFControl _ Tx module carries out framing and format conversion to received PCF frame, and provides it to Ethernet MAC module; the FPGA of the SM node measures the delay t1 of the PCF frame sent by the PCF frame sending module passing through the PCFControl _ Tx module of the SM node as 50s through an internal program;
the Ethernet MAC module carries out format conversion after receiving the PCF frame, and realizes data exchange with the PHY chip; the FPGA of the SM node measures the time delay t2 of the PCF frame passing through the SM node Ethernet MAC module to be 48s through an internal program;
meanwhile, the Ethernet MAC module sends an enabling signal to the Wire _ Delay _ Tx module, and the Wire _ Delay _ Tx module triggers a time reference pulse signal to the Wire _ Delay _ Rx module of the CM node after receiving the enabling signal;
after the PCF frame is sent to the PHY chip of the CM node through a CAT.6 network cable by the PHY chip, the PCF frame is further sent to an Ethernet MAC module of the CM node for format conversion, and the FPGA of the CM node measures the time delay t4 of the PCF frame passing through the Ethernet MAC module of the CM node to be 48s through an internal program;
meanwhile, the PHY chip sends the time point for receiving the PCF frame to a Wire _ Delay _ Rx module;
the Ethernet MAC module sends PCF frames to a PCFControl _ Rx module, the PCFControl _ Rx module analyzes and converts the received PCF frames, and the FPGA of the CM node measures the time delay t5 of the PCF frames passing through the PC FControl _ Rx module of the CM node as 62s through an internal program;
the FPGA of the CM node measures a time difference T3 between the time point when the CM node Wire _ Delay _ Rx module receives the PCF frame and the time reference pulse signal, which is 75 s.
Calculating the SM-to-CM transparent clock by the FPGA of the CM node: parent _ Clock ═ T1+ T2+ T3+ T4+ T5 ═ 283s example 3:
as shown in fig. 3, the CM-to-SM transparent clock measurement flow is that, at this time, the SM node is a sender, and the CM node is a receiver, specifically:
a. measuring the delay t1 of PCFControl _ Tx module of PCF frame passing through CM node (50 s);
b. measuring the time delay t2 of PCF frame passing through the CM node Ethernet MAC module as 48 s;
c. measuring the time delay t4 of PCF frame passing through SM node Ethernet MAC module as 48 s;
d. measuring the time delay t5 of the PCF frame passing through the PCFControl _ Rx module of the SM node as 62 s;
e. and measuring the time difference t3 between the PCF frame receiving time point and the time reference pulse signal receiving time t3 of the SM node Wire _ Delay _ Rx module to be 43 s.
f. Compute CM to SM transparent clock: parent _ Clock is t1+ t2+ t3+ t4+ t5 is 251s
It can be seen that with different PHY chips, the two measurements of one-way delay are different.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (5)
1. The method for accurately measuring the time to trigger the Ethernet transparent clock is characterized in that: dividing a transparent clock in the time-triggered Ethernet into three parts for measurement, namely time delay inside a PCF frame sender, time delay inside a PCF frame receiver and one-way link time delay between the PCF frame sender and the PCF frame receiver; and adding the three parts of delay time which are respectively measured to obtain the transparent clock.
2. The method of accurately measuring a time-triggered ethernet transparent clock according to claim 1, wherein: the method for measuring the time delay of the unidirectional link between the PCF frame sender and the PCF frame receiver comprises the following steps:
when a PCF frame sender sends data to a PHY chip of a PCF frame receiver through the PHY chip, a time reference pulse signal is triggered at the sending time point and is transmitted to the PCF frame receiver through a time reference line;
the time difference between the time point when the receiver of PCF frame receives PCF frame and the time point when the receiver of PCF frame receives the time reference pulse signal is the time delay of the unidirectional link.
3. The method of accurately measuring a time-triggered ethernet transparent clock according to claim 1 or 2, characterized in that: the PCF frame sender and the PCF frame receiver are internally provided with an FPGA and a PHY chip; the PCF frame sender and the PCF frame receiver carry out data transmission through a communication network cable;
the FPGA is internally provided with a PCF frame sending module, a PCF frame receiving module, a PCFControl _ Tx module, a PCFControl _ Rx module, a Wire _ Delay _ Tx module, a Wire _ Delay _ Rx module and an Ethernet MAC module; based on this, the measurement process of the transparent clock is as follows:
the method comprises the following steps: the PCF frame sending module of the PCF frame sender sends PCF frames to the PCFControl _ Tx module of the PCF frame sender, and the PCFControl _ Tx module carries out framing and format conversion on the received PCF frames and provides the PCFControl _ Tx module with the PCF frames for the Ethernet MAC module of the PCF frame sender; the PCF frame sender measures the delay t1 of PCF frame passing through the PCFControl _ Tx module by an internal preset program;
step two: the Ethernet MAC module of the PCF frame sender carries out format conversion after receiving the PCF frame and then sends the PCF frame to the PHY chip of the Ethernet MAC module; the PCF frame sender measures the delay t2 of the PCF frame passing through the Ethernet MAC module by an internal preset program;
meanwhile, the Ethernet MAC module sends an enabling signal to a Wire _ Delay _ Tx module, and the Wire _ Delay _ Tx module triggers a time reference pulse signal to be transmitted to a Wire _ Delay _ Rx module of the PCF frame receiver through a time reference line after receiving the enabling signal;
step three: the PCF frame is sent to the PHY chip of the PCF frame receiver through the PHY chip and the communication network line, and then is further sent to the Ethernet MAC module of the PCF frame receiver, and the PCF frame receiver measures the delay t4 of the PCF frame passing through the Ethernet MAC module by an internal program;
meanwhile, the PHY chip sends the time point for receiving the PCF frame to a Wire _ Delay _ Rx module of the PHY chip;
step four: the Ethernet MAC module of the PCF frame receiver sends PCF frames to the PCFControl _ Rx module, the PCFControl _ Rx module analyzes and converts the received PCF frames, and the FPGA of the PCF frame receiver measures the delay t5 of the PCF frames passing through the PC FControl _ Rx module by an internal preset program;
step five: the PCF frame receiver measures the time difference T3 between the time point of receiving the PCF frame received by the Wire _ Delay _ Rx module and the time point of receiving the time reference pulse signal;
step six: the Transparent Clock Transparent _ Clock is T1+ T2+ T3+ T4+ T5.
4. The method of accurately measuring a time-triggered ethernet transparent clock according to claim 3, wherein: the PHY chip of the PCF frame sender is different from that of the PCF frame receiver.
5. The method of accurately measuring a time-triggered ethernet transparent clock according to claim 3, wherein: and the communication network line between the PCF frame sender and the PCF frame receiver adopts CAT.6 six-type non-shielded network line.
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| CN115189793A (en) * | 2022-06-01 | 2022-10-14 | 北京控制工程研究所 | System and method for accurately measuring time-triggered Ethernet transparent transmission clock |
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| CN107425936A (en) * | 2017-06-15 | 2017-12-01 | 西安微电子技术研究所 | A kind of transparent clock measurement apparatus |
| CN108322280A (en) * | 2017-12-12 | 2018-07-24 | 北京时代民芯科技有限公司 | A kind of distributed computer network (DCN) clock synchronizing relay compensation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107425936A (en) * | 2017-06-15 | 2017-12-01 | 西安微电子技术研究所 | A kind of transparent clock measurement apparatus |
| CN108322280A (en) * | 2017-12-12 | 2018-07-24 | 北京时代民芯科技有限公司 | A kind of distributed computer network (DCN) clock synchronizing relay compensation method |
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| CN115189793A (en) * | 2022-06-01 | 2022-10-14 | 北京控制工程研究所 | System and method for accurately measuring time-triggered Ethernet transparent transmission clock |
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