CN115189793A - System and method for accurately measuring time-triggered Ethernet transparent transmission clock - Google Patents
System and method for accurately measuring time-triggered Ethernet transparent transmission clock Download PDFInfo
- Publication number
- CN115189793A CN115189793A CN202210617884.XA CN202210617884A CN115189793A CN 115189793 A CN115189793 A CN 115189793A CN 202210617884 A CN202210617884 A CN 202210617884A CN 115189793 A CN115189793 A CN 115189793A
- Authority
- CN
- China
- Prior art keywords
- delay
- physical layer
- sending
- time
- data frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A time-triggered Ethernet transparent transmission clock accurate measurement system and method is characterized in that a measurement framework comprises a local clock control module, a time synchronization state machine module, a PCF frame sending and scheduling module, a physical layer data frame sending and intercepting module and a physical layer data frame receiving and intercepting module, the transparent transmission clock value is accurately measured and comprises physical layer delay overhead, MAC layer delay overhead and hardware delay overhead between an MAC layer and a physical layer, corresponding hardware circuits are added to record corresponding time points for accurate measurement, and finally the accurate transparent transmission clock value is obtained.
Description
Technical Field
The invention relates to a system and a method for accurately measuring a time-triggered Ethernet transparent transmission clock, belonging to the technical research field of time-triggered Ethernet.
Background
In the process of developing a time-triggered Ethernet system, an end system and a switch realize time synchronization in the system through an interactive Protocol Control Frame (PCF), the interaction of the PCF frame needs to realize a time synchronization curing function, and when the time curing function calculates a curing time point, time delay information of a data frame on a data link is needed, namely, the time delay information is called a transparent transmission clock. The high-precision transparent transmission clock is the basis for constructing a high-precision time synchronization system, and if the transparent transmission clock generates larger deviation, the synchronization precision of the whole time-triggered Ethernet system is reduced, and the system reliability is seriously influenced.
Disclosure of Invention
The technical problem solved by the invention is as follows: the system and the method for accurately measuring the time-triggered Ethernet transparent transmission clock are provided for solving the problem that the existing transparent transmission clock measuring method in the prior art is easy to generate larger deviation so as to cause the reduction of the synchronization accuracy of a time-triggered Ethernet system.
The technical scheme for solving the technical problems is as follows:
a time-triggered Ethernet transparent transmission clock accurate measurement system comprises a local clock control module, a time synchronization state machine module, a PCF frame sending and scheduling module, a physical layer data frame sending and intercepting module and a physical layer data frame receiving and intercepting module, wherein:
the local clock control module is used for maintaining local time and calculating high-precision local time according to nanosecond time granularity;
the time synchronization state machine module is used for realizing a time synchronization protocol, controlling PCF frame sending and receiving of the MAC layer and the physical layer, calculating data frame sending delay of the MAC layer and data frame sending delay of the physical layer according to the PCF frame sending time point information of the MAC layer and the physical layer, and calculating a transparent transmission clock value according to the obtained data;
the PCF frame sending and scheduling module is used for monitoring the PCF frame sending signal of the MAC layer sent by the time synchronization state machine module and recording the PCF frame sending time point information of the MAC layer;
the physical layer data frame sends and listens the module: intercepting PCF frame sending signal of physical layer sent by PCF frame sending scheduling module, writing current local time into sending time point register, and then obtaining PCF frame sending time point information of physical layer for calculating sending delay, and at the same time generating effective data frame receiving signal;
and the physical layer data frame receiving and intercepting module is used for intercepting a data frame receiving effective signal provided by the physical layer and recording the receiving processing time delay of the physical layer.
The PCF frame sending and scheduling module monitors PCF frame signals of the MAC layer sent by the time synchronization state machine module, writes the current local time Sys _ clk into a dispatching time point register, and obtains PCF frame sending time point information dispatch _ pit _ reg of the MAC layer for calculating sending delay.
The physical layer data frame sending and monitoring module monitors PCF frame signals of the physical layer, writes the current local time Sys _ clk into a sending time point register, and obtains PCF frame sending time point information send _ pit _ reg of the physical layer for calculating sending delay.
The physical layer data frame receiving and intercepting module intercepts a data frame receiving effective signal ETH _ RX _ DV output by the physical layer data frame sending and intercepting module, writes the current local time Sys _ clk into a receiving time point register to obtain physical layer intercepting receiving time information recv _ pit _ reg for calculating the physical layer processing delay.
In the dynamic capturing process of the transparent transmission clock value, the calculation formula of the transparent transmission clock value is specifically as follows:
transparent_delay＝send_delay+phy_delay；
in the formula, send _ delay represents a MAC layer data frame transmission delay, and phy _ delay represents a physical layer data frame transmission delay.
The calculation formula of the sending delay send _ delay of the data frame of the MAC layer is specifically:
send_delay＝send_pit_reg-dispatch_pit_reg。
calculating the physical layer data frame sending delay phy _ delay, specifically:
phy_delay＝(recv_pit_reg-send_pit_reg)/2。
a method for accurately measuring a time-triggered Ethernet transparent transmission clock comprises the following steps:
determining the delay overhead of an end system MAC layer;
determining the delay overhead of a physical layer of an end system;
and determining hardware delay overhead between a physical layer and an MAC layer of the end system, and finishing accurate measurement of the transparent transmission clock.
When the system sends PCF frame to physical layer, it monitors the PCF frame sending time point information of physical layer, and records the sending time point information of PCF frame to physical layer.
And determining the hardware delay cost between the MAC layer and the physical layer of the end system, and calculating the hardware delay cost of the MAC layer and the physical layer according to the time point information of the delay cost of the MAC layer of the end system and the delay cost of the physical layer of the end system.
Compared with the prior art, the invention has the advantages that:
the invention provides a system and a method for accurately measuring a time-triggered Ethernet transparent transmission clock, aiming at delay overhead generated between a physical layer, an MAC layer and the MAC layer, the accurate measurement is carried out by adding a corresponding hardware circuit to record a corresponding time point, a high-precision transparent transmission clock value can be obtained through a fine-grained nanosecond-level time reference, the time synchronization precision of the system is improved, and meanwhile, compared with the existing method for measuring the transparent transmission clock by software, the nanosecond-level transparent transmission clock value can be obtained through a simple hardware circuit, the frame precision is improved, the method is simple, convenient and easy to implement, and the method is easy to popularize.
Drawings
FIG. 1 is a diagram of a system for accurately measuring a transparent transmission clock provided by the invention;
FIG. 2 is a diagram of a system for accurately measuring a transparent transmission clock provided by the invention;
Detailed Description
A time-triggered Ethernet pass-through clock accurate measurement system and method, aiming at the delay overhead generated between a physical layer, an MAC layer and the MAC layer, the accurate measurement is carried out by adding corresponding hardware circuits to record corresponding time points, and finally, an accurate pass-through clock value is obtained, wherein the measurement framework specifically comprises the following steps:
the local clock control module is used for maintaining local time, calculating high-precision local time, realizing nanosecond-level time granularity and improving the accuracy of calculation of the transparent transmission clock;
the time synchronization state machine module realizes a time synchronization protocol, controls the sending and receiving of PCF frames and realizes the dynamic capture of real-time transparent transmission clock values;
controlling PCF frame sending and receiving of the MAC layer and the physical layer, calculating data frame sending delay of the MAC layer and data frame sending delay of the physical layer according to PCF frame sending time point information of the MAC layer and the physical layer, and calculating a transparent transmission clock value according to the obtained data;
the PCF frame sending and scheduling module is used for monitoring the PCF frame sending signal of the MAC layer sent by the time synchronization state machine module, and recording the PCF frame sending time point information of the MAC layer if the PCF frame sending signal is monitored; if not, then carrying out signal interception again;
a physical layer data frame sending and monitoring module which monitors the physical layer PCF frame sending signal sent by the PCF frame sending and scheduling module, writes the current local time into a sending time point register and then obtains the PCF frame sending time point information of the physical layer for the calculation of sending delay and simultaneously generates a data frame receiving effective signal; if not, then the signal monitoring is carried out again;
and the physical layer data frame receiving and intercepting module is used for intercepting the data frame receiving effective signal provided by the physical layer, recording the receiving processing time delay of the physical layer, and if the data frame receiving effective signal is not intercepted, re-intercepting the signal.
The local clock control module maintains a local time Sys _ clk for calculating a high-precision local time; the PCF frame sending and scheduling module monitors PCF frame signals of an MAC layer sent by the time synchronization state machine module, writes the current local time Sys _ clk into a dispatching time point register, and obtains PCF frame sending time point information dispatch _ pit _ reg of the MAC layer for calculating sending delay; the physical layer data frame sending and monitoring module monitors PCF frame signals of a physical layer, writes the current local time Sys _ clk into a sending time point register, and acquires PCF frame sending time point information send _ pit _ reg of the physical layer for calculating sending delay; the physical layer data frame receiving and intercepting module intercepts a data frame receiving effective signal ETH _ RX _ DV output by the physical layer data frame sending and intercepting module, writes the current local time Sys _ clk into a receiving time point register to obtain physical layer intercepting and receiving time information recv _ pit _ reg for calculating the physical layer processing delay;
in the dynamic capturing process of the transparent transmission clock value, the calculation formula of the transparent transmission clock value is specifically as follows:
transparent_delay＝send_delay+phy_delay
wherein, send _ delay is the MAC layer data frame transmission delay, and phy _ delay is the physical layer data frame transmission delay;
the calculation formula of the data frame sending delay send _ delay is specifically as follows:
send_delay＝send_pit_reg-dispatch_pit_reg
the transmission delay phy _ delay assuming that the physical layer chip transmission delay phy _ send _ delay is equal to the physical layer chip reception delay phy _ recv _ delay.
phy_delay＝(recv_pit_reg-send_pit_reg)/2
The method for accurately measuring the time-triggered Ethernet transparent transmission clock comprises the following steps:
determining the delay overhead of an MAC layer of the end system;
determining the delay overhead of a physical layer of an end system;
determining hardware delay overhead between a physical layer and an MAC layer of the end system, and finishing accurate measurement of a transparent transmission clock;
determining delay overhead of an MAC layer of the end system, recording sending time point information of a PCF frame through a register when the MAC layer sends the PCF frame signal, determining delay overhead of a physical layer of the end system, monitoring the sending time point information of the PCF frame of the physical layer when the end system sends the PCF frame to the physical layer, and recording the sending time point information of the PCF frame when the PCF frame is sent to the physical layer through the register;
determining the hardware delay cost between the MAC layer and the physical layer of the end system, and calculating the hardware delay cost of the MAC layer and the physical layer according to the time point information of the delay cost of the MAC layer and the delay cost of the physical layer of the end system.
The following is further illustrated according to specific examples:
in the present embodiment, a transparent transmission clock accurate measurement system diagram is shown in fig. 1, and includes a local clock control module, a time synchronization state machine module, a PCF frame sending and scheduling module, a physical layer data frame sending and intercepting module, and a physical layer data frame receiving and intercepting module, and the main functions are as follows:
the nanosecond time granularity is designed, and the accuracy of calculation of the transparent transmission clock is improved;
a time synchronization state machine module is designed to realize a time synchronization protocol and control the sending and receiving of PCF frames;
a PCF frame sending and dispatching module is designed, a PCF _ comma signal sent by a time synchronization state machine module is monitored, and the current local time Sys _ clk is written into a dispatch time point register dispatch _ pit _ reg and is used for calculating sending delay;
designing a physical layer data frame sending and intercepting module, intercepting an ETH _ TX _ EN signal sent by a PCF frame sending and scheduling module, and writing the current local time Sys _ clk into a sending time point register send _ pit _ reg for calculating sending delay;
a physical layer data frame receiving and intercepting module is designed, an ETH _ RX _ DV signal provided by a physical layer chip is intercepted, and the current local time Sys _ clk is written into a receiving time point register recv _ pit _ reg and is used for calculating the processing delay of the physical layer.
As shown in fig. 2, a flow chart of the accurate measurement of the transparent transmission clock provided by the present invention mainly includes the following processes:
the local clock control module periodically updates the local time count to realize high-precision nanosecond time granularity and is used for acquiring a high-precision transparent transmission clock value;
the time synchronization state machine module controls PCF frame sending, and enables PCF _ command signal sending PCF frame when reaching PCF frame sending time point;
the PCF frame sending and scheduling module monitors a PCF _ command signal sent by the time synchronization state machine module, and writes the current local time Sys _ clk into a dispatch time point register dispatch _ pit _ reg;
the physical layer data frame sending and intercepting module listens an ETH _ TX _ EN signal sent by a PCF frame sending and scheduling module, and writes the current local time Sys _ clk into a sending time point register send _ pit _ reg, wherein:
the data frame transmission delay send _ delay is calculated according to the following formula:
send_delay＝send_pit_reg-dispatch_pit_reg
the physical layer chip works in a self-loop mode, the physical layer data frame receiving and monitoring module monitors an ETH _ RX _ DV signal sent by the physical layer chip, and writes the current local time Sys _ clk into a sending time point register recv _ pit _ reg;
calculating the data frame sending delay phy _ delay according to the following formula, and assuming that the physical layer chip sending delay phy _ send _ delay is equal to the physical layer chip receiving delay phy _ recv _ delay;
phy_delay＝(recv_pit_reg-send_pit_reg)/2：
the formula for calculating the transparent transmission clock value is as follows:
transparent_delay＝send_delay+phy_delay。
although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make possible variations and modifications of the present invention using the method and the technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention are all within the scope of the present invention.
Those skilled in the art will appreciate that the details of the invention not described in detail in this specification are well within the skill of those in the art.
Claims (10)
1. The utility model provides a time trigger ethernet passes through accurate measurement system of transmission clock which characterized in that:
the system comprises a local clock control module, a time synchronization state machine module, a PCF frame sending and scheduling module, a physical layer data frame sending and intercepting module and a physical layer data frame receiving and intercepting module, wherein:
the local clock control module is used for maintaining local time and calculating high-precision local time according to nanosecond time granularity;
the time synchronization state machine module is used for realizing a time synchronization protocol, controlling PCF frame sending and receiving of the MAC layer and the physical layer, calculating data frame sending delay of the MAC layer and data frame sending delay of the physical layer according to the PCF frame sending time point information of the MAC layer and the physical layer, and calculating a transparent transmission clock value according to the obtained data;
the PCF frame sending and scheduling module is used for monitoring the PCF frame sending signal of the MAC layer sent by the time synchronization state machine module and recording the PCF frame sending time point information of the MAC layer;
the physical layer data frame sends and listens the module: monitoring a physical layer PCF frame sending signal sent by a PCF frame sending scheduling module, writing the current local time into a sending time point register, acquiring PCF frame sending time point information of a physical layer for calculating sending delay, and generating a data frame receiving effective signal;
and the physical layer data frame receiving and intercepting module is used for intercepting the data frame receiving effective signal provided by the physical layer and recording the receiving processing time delay of the physical layer.
2. The system according to claim 1, wherein the system comprises:
the PCF frame sending and scheduling module monitors PCF frame signals of an MAC layer sent by the time synchronization state machine module, writes the current local time Sys _ clk into a dispatching time point register, and obtains PCF frame sending time point information dispatch _ pit _ reg of the MAC layer for calculating sending delay.
3. The system of claim 2, wherein the system comprises:
the physical layer data frame sending and monitoring module monitors PCF frame signals of the physical layer, writes the current local time Sys _ clk into a sending time point register, and obtains PCF frame sending time point information send _ pit _ reg of the physical layer for calculating sending delay.
4. The system according to claim 3, wherein the system comprises:
the physical layer data frame receiving and intercepting module intercepts a data frame receiving effective signal ETH _ RX _ DV output by the physical layer data frame sending and intercepting module, writes the current local time Sys _ clk into a receiving time point register to obtain physical layer intercepting receiving time information recv _ pit _ reg for calculating the physical layer processing delay.
5. The system according to claim 4, wherein the system comprises:
in the dynamic capturing process of the transparent transmission clock value, the calculation formula of the transparent transmission clock value is specifically as follows:
transparent_delay＝send_delay+phy_delay；
in the formula, send _ delay represents a MAC layer data frame transmission delay, and phy _ delay represents a physical layer data frame transmission delay.
6. The system of claim 5, wherein the system comprises:
the calculation formula of the sending delay send _ delay of the data frame of the MAC layer is specifically:
send_delay＝send_pit_reg-dispatch_pit_reg。
7. the system according to claim 6, wherein the system comprises:
calculating the physical layer data frame sending delay phy _ delay, specifically:
phy_delay＝(recv_pit_reg-send_pit_reg)/2。
8. the method for accurately measuring the time-triggered ethernet transparent clock according to claim 7, comprising:
determining the delay overhead of an end system MAC layer;
determining the delay overhead of a physical layer of an end system;
and determining hardware delay overhead between a physical layer and an MAC layer of the end system, and finishing accurate measurement of the transparent transmission clock.
9. The method for accurately measuring the time-triggered ethernet pass-through clock according to claim 8, wherein:
when the PCF frame is sent to the physical layer by the end system, the delay overhead of the physical layer is determined, the sending time point information of the PCF frame is intercepted, and the sending time point information of the PCF frame is recorded by the register.
10. The method for accurately measuring the time-triggered ethernet transparent transmission clock according to claim 9, wherein:
and determining the hardware delay cost between the MAC layer and the physical layer of the end system, and calculating the hardware delay cost of the MAC layer and the physical layer according to the calculated time point information of the delay cost of the MAC layer and the delay cost of the physical layer of the end system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210617884.XA CN115189793A (en) | 2022-06-01 | 2022-06-01 | System and method for accurately measuring time-triggered Ethernet transparent transmission clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210617884.XA CN115189793A (en) | 2022-06-01 | 2022-06-01 | System and method for accurately measuring time-triggered Ethernet transparent transmission clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115189793A true CN115189793A (en) | 2022-10-14 |
Family
ID=83513268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210617884.XA Pending CN115189793A (en) | 2022-06-01 | 2022-06-01 | System and method for accurately measuring time-triggered Ethernet transparent transmission clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115189793A (en) |
-
2022
- 2022-06-01 CN CN202210617884.XA patent/CN115189793A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10707984B2 (en) | Techniques for synchronizing slave devices | |
| US20240103995A1 (en) | Recording processor instruction execution cycle and non-cycle count trace events | |
| US10863469B2 (en) | System and method for accurate timestamping of virtual reality controller data | |
| US9927883B1 (en) | Mouse resolution estimation | |
| CN103309397B (en) | Based on the synchronous sampling method of the data acquisition equipment of USB | |
| CN103248471B (en) | Clock synchronizing method based on PTP protocol Yu Reflective memory network | |
| US8170165B2 (en) | Clock calibration in sleep mode | |
| US10560780B2 (en) | Phase alignment in an audio bus | |
| CN112782640A (en) | Method and device for calibrating intelligent electric energy meter | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| CN103595588A (en) | Method for accurately measuring asynchronous Ethernet circuit time delay | |
| CN113518309B (en) | TDOA estimation method and system for ultra-wideband indoor positioning | |
| CN113960413A (en) | Time synchronization method for collecting unit and collecting unit in fault indicator | |
| CN116932333B (en) | AXI bus real-time performance monitoring method for post-silicon verification | |
| CN115189793A (en) | System and method for accurately measuring time-triggered Ethernet transparent transmission clock | |
| CN108983036B (en) | Traveling wave distance measurement system based on electronic transformer | |
| CN100334846C (en) | High precision network delay measuring method based on universal PC | |
| US9229841B2 (en) | Systems and methods for detecting errors and recording actions on a bus | |
| WO2016183955A1 (en) | Speech synchronization method and device | |
| CN113055113A (en) | Clock time synchronization method, device, equipment and storage medium | |
| CN113259037B (en) | Time synchronization method, medium, and apparatus based on sensor time synchronization system | |
| CN115102453A (en) | Position control system and method | |
| CN108628156A (en) | A kind of high precision computation machine serial ports time service method | |
| CN111865467A (en) | Clock synchronization system and method between distributed chassis board cards for time delay test | |
| CN112558685A (en) | Time synchronization method for power distribution terminal modules |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |