CN113055113A - Clock time synchronization method, device, equipment and storage medium - Google Patents
Clock time synchronization method, device, equipment and storage medium Download PDFInfo
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- CN113055113A CN113055113A CN201911371412.5A CN201911371412A CN113055113A CN 113055113 A CN113055113 A CN 113055113A CN 201911371412 A CN201911371412 A CN 201911371412A CN 113055113 A CN113055113 A CN 113055113A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
Abstract
The application provides a clock time synchronization method, a device, equipment and a storage medium, wherein the method comprises the following steps: transmitting a delay determination signal to a signal transceiving port in the slave node; acquiring a time delay feedback signal from the slave node; determining a master-slave time difference according to the time delay feedback signal and the time delay determination signal; and sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference. According to the technical scheme of the embodiment of the application, the master-slave time difference of the signals between the master node and the slave node is determined through the time delay determination signal and the time delay feedback signal, the clock time is compensated according to the master-slave time difference, the accuracy of clock time synchronization is improved, the time error caused by an asymmetric transmission path is reduced, and the stability of the service can be improved.
Description
Technical Field
The present application relates to wired communication networks, and in particular, to a clock time synchronization method, apparatus, system, and storage medium.
Background
The existing clock time synchronization method in a communication network is mainly based on a PTP1588 technology, one of two connected nodes serves as a master node, the other node serves as a slave node, under normal conditions, the slave node synchronizes clocks of the master node, the same clock is equally used between the nodes, a master node and the slave node communicate through 1588 messages to receive and send data packets to achieve clock time synchronization between the nodes, time consumption exists when the 1588 messages are transmitted inside the master node and the slave node in the clock time synchronization mode, time difference exists between the master node and the slave node when the clock time synchronization is conducted, the precision of clock time is poor, and synchronization time mutation easily occurs when the state of the nodes changes, so that service is affected.
Disclosure of Invention
The application provides a clock time synchronization method, a clock time synchronization device, clock time synchronization equipment and a storage medium.
The embodiment of the application provides a clock time synchronization method, which is applied to a main node and comprises the following steps:
transmitting a delay determination signal to a signal transceiving port in the slave node; acquiring a time delay feedback signal from the slave node; determining a master-slave time difference according to the time delay feedback signal and the time delay determination signal; and sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference.
The embodiment of the application provides a clock time synchronization method, which is applied to a slave node and comprises the following steps:
receiving a time delay determination signal from a signal transceiving port in a main node; sending a time delay feedback signal to the main node; and receiving the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and performing clock time synchronization with the master node according to the master-slave time difference.
The embodiment of the application provides a clock time synchronization device, which is applied to a main node and comprises:
the information sending module is used for sending a time delay determination signal to a signal receiving and sending port in the slave node; a signal receiving module, configured to obtain a time delay feedback signal from the slave node; the time delay determining module is used for determining master-slave time difference according to the time delay feedback signal and the time delay determining signal; and the clock synchronization module is used for sending the master-slave time difference to the slave node and carrying out clock time synchronization with the slave node according to the master-slave time difference.
The embodiment of the application provides a clock time synchronization device, which is applied to a slave node and comprises:
the signal receiving module is used for receiving the time delay determination signal from a signal receiving and transmitting port in the main node; the signal feedback module is used for sending a time delay feedback signal to the main node; and the clock synchronization module is used for receiving the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal and carrying out clock time synchronization with the master node according to the master-slave time difference.
An embodiment of the present application provides an apparatus, including:
one or more processors; a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a method of clock time synchronization as described in any of the embodiments of the present application.
The present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement a clock time synchronization method according to any one of the embodiments of the present application.
According to the technical scheme, the time delay determining signal is sent to the slave node, the time delay feedback signal of the slave node is obtained to determine the time deviation between the master node and the slave node, time synchronization is carried out on the slave node according to the time deviation, the time error caused by time consumption in internal transmission is reduced, the accuracy of the synchronous clock time of the master node and the slave node can be improved, the time mutation problem caused by node state change is solved, and the service influence is reduced.
With regard to the above embodiments and other aspects of the present application and implementations thereof, further description is provided in the accompanying drawings description, detailed description and claims.
Drawings
Fig. 1 is a flowchart of a clock time synchronization method provided in an embodiment of the present application;
fig. 2 is a topology structure diagram of a network element according to an embodiment of the present application;
fig. 3 is a flowchart of a clock time synchronization method according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a host node according to an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating a method for clock time synchronization according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a clock time synchronization method according to an embodiment of the present application;
fig. 7 is a flowchart of a clock time synchronization method according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a clock time synchronization apparatus according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a clock time synchronization apparatus according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an apparatus provided in an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Fig. 1 is a flowchart of a clock time synchronization method provided in an embodiment of the present application, where the embodiment of the present application may be applied to a situation of synchronizing a clock time of a network element in a communication network, and the method may be executed by a clock time synchronization apparatus in the embodiment of the present application, where the apparatus may be implemented in a software and/or hardware manner, and may be generally integrated in a master node of a network element device, referring to fig. 1, the clock time synchronization method in the embodiment of the present application includes:
The master node may be a network element node that transmits clock time when performing clock synchronization, the slave node may be a network element node that receives clock time when performing clock synchronization, and the master node and the slave node may be connected in a wired or wireless manner. Fig. 2 is a topology structure diagram of a network element according to an embodiment of the present application, and referring to fig. 2, when a network element a sends a clock time to a network element B for clock synchronization, the network element a may be a master node, and the network element B may be a slave node; when the network element B sends the clock time to the network element C for clock synchronization, the network element B may be a master node and the network element C may be a slave node.
Specifically, the information transceiving port may be a port for receiving a signal from inside a slave node, and specifically may be an optical monitoring port on an interface board in a network element, the master node may send a delay determination signal to the signal transceiving port of the slave node to obtain a time error inside the master node and the slave node, where the delay determination signal may be a service signal transmitted between the master node and the slave node, and specifically may be a GE optical signal or a 10GE signal, and the delay determination signal may be transmitted between the master node and the slave node, and may be used to determine the time error inside the network element such as the master node and the slave node.
And 102, acquiring a time delay feedback signal from the slave node.
The delay feedback signal may be a traffic signal transmitted from the slave node to the master node, and specifically may be a GE optical signal or a 10GE signal, and the delay feedback signal may include custom-coded TOD information, the TOD information may be composed of a transmission time and a reception time of the delay determination signal and a transmission time and a reception time of the delay feedback information, and the delay feedback signal may include a reception time of the delay determination information at the slave node and a transmission time of the delay feedback signal at the slave node.
In this embodiment of the present application, a delay feedback signal sent by a slave node may be obtained, and specifically, an optical monitoring port in an interface board of the slave node may be monitored to obtain the delay feedback signal sent by the slave node.
And 103, determining a master-slave time difference according to the time delay feedback signal and the time delay determination signal.
The master-slave time difference may be an error time of clocks of the master node and the slave node, and the master-slave time difference may be a time deviation of the master node and the slave node due to transmission processing inside the network element node.
Specifically, the time consumed by the message in the master node and the time consumed by the message in the slave node can be determined according to the time delay feedback signal and the time delay determination signal receiving time and the time delay determination signal sending time, so that the time deviation caused by internal time consumption is reduced when the master node and the slave node perform clock synchronization. The time delay determination signal can be analyzed, the message sending time and the message receiving time of the master node in the time delay determination signal can be obtained, the time delay feedback signal can be analyzed, the message sending time and the message receiving time of the slave node can be obtained, the internal time deviation of the master node sending message and the receiving message and the internal time deviation of the slave node sending message and the receiving message can be determined according to the message sending time and the message receiving time of the master node and the slave node, and the master-slave time difference between the master node clock time and the slave node clock time can be determined according to the deviation.
And step 104, sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference.
Specifically, the master node may send the master-slave time difference to the slave node, and the slave node may compensate the local clock time of the slave node according to the master-slave time difference, for example, the time of the local clock of the slave node plus the master-slave time difference may be used as a new time, or the master node may compensate the synchronized clock time when performing clock synchronization, and the slave node may use the acquired clock time as the clock time of the slave node.
According to the technical scheme of the embodiment of the application, the time delay determining signal is sent to the slave node, the time delay feedback signal of the slave node is obtained, the master-slave time difference between the master node and the slave node is determined through the time delay determining signal and the time delay feedback information, clock synchronization is carried out according to the master-slave time difference, time errors caused by time consumption in internal transmission are reduced, the accuracy of clock time is improved, the problem of time mutation caused by node state change can be solved, and the stability of services is enhanced.
Fig. 3 is a flowchart of a clock time synchronization method provided in an embodiment of the present application, in order to further improve the precision of clock time, in the embodiment of the present application, a master node determines a master-slave time difference of data using a clock at an interface board as a standard, and referring to fig. 3, the clock time synchronization method according to the embodiment of the present application includes:
The slave node may include an interface board, a master control board, and a service board, where the board number may identify information of the interface board, the master control board, and the service board, the interface board may include one or more optical monitoring ports, and the port number may identify different optical monitoring ports.
Specifically, an optical monitoring port in the slave node may be determined in advance by a single board number and a port number, and the port may be used as an access point for determining a master-slave time difference between the master node and the slave node. For example, a port status flag may be automatically or manually set in the optical monitoring port, when the port status flag in the optical monitoring port is 1, the optical monitoring port may be identified as belonging to the master node, and when the port status flag in the optical monitoring port is 0, the optical monitoring port may be identified as belonging to the slave node.
The interface board optical monitoring port may be a port in the host node that transmits the delay determination signal.
In this embodiment, the master node may establish a connection with a predetermined signal transceiving port from an optical port of the interface board, and may send the delay determination signal to the transceiving port through the interface optical monitoring port. Further, fig. 4 is a schematic structural diagram of a master node according to an embodiment of the present application, and referring to fig. 4, because a delay determining signal is generated in the master controller and the delay determining signal is sent at an interface board optical monitoring port in the master node, in order to reduce an error of a master-slave time difference, a timestamp may be added to the delay determining signal at the interface board optical monitoring port, and the time of the timestamp may be time of an FPGA in the interface board.
The first sending time may be a time when the delay determination signal is sent from an optical monitoring port of an interface board of the host node, the first sending time may be added to the delay determination signal for sending, and the first sending time may also be stored in the host node.
Specifically, when the delay determination signal is sent at the optical monitoring port of the interface board, a timestamp of the delay determination signal may be generated, and a time corresponding to the timestamp may be used as a first sending time of the delay determination signal. For example, fig. 4 is a schematic structural diagram of a master node according to an embodiment of the present application, and referring to fig. 4, because a delay determining signal is generated in the master controller and the delay determining signal is sent at an interface board optical monitoring port in the master node, in order to reduce an error of a master-slave time difference, a timestamp may be added to the delay determining signal at the interface board optical monitoring port, and a time of the timestamp may be a time of an FPGA in the interface board.
In one embodiment, the determining a first transmission time of the latency determination signal at the optical supervisory port of the interface board includes:
acquiring a first entering clock phase of the time delay determination signal entering a signal processing device in the optical monitoring port of the interface board; acquiring a first output clock phase of the time delay determination signal output from the signal processing device; and taking the phase difference between the first output clock phase and the first incoming clock phase as the first transmission compensation time of the delay determination signal, and determining the first transmission time according to the port clock of the optical monitoring port of the interface board and the first transmission compensation time.
In the embodiment of the present invention, because the received delay determining signal needs to be processed in the network element, and the accurate receiving time of the packet can be obtained only after the processing, the time for processing the delay determining signal needs to be compensated to improve the accuracy of the clock, wherein the signal processing device may specifically be a serdes, and may record the phase of the system clock of the master node when the delay determining signal enters the signal processing device as the first entering clock phase, may record the phase of the system clock output by the delay determining signal from the signal processing device as the first output clock phase, may calculate the phase difference between the first output clock phase and the first entering clock phase, may use the time length corresponding to the phase difference as the first transmission compensation time for processing the delay determining signal, and may add the first transmission compensation time on the basis that the master node obtains the first transmission time, the actual transmission time of the signal may be determined by the transmission delay in the master node.
And step 204, receiving the delay feedback signal sent by the signal transceiving port of the slave node through an interface board optical monitoring port.
In this embodiment of the present application, the interface board optical monitoring port of the master node may monitor the transceiver port of the slave node, and when the slave node transmits the delay feedback signal from the transceiver port, the delay feedback signal in the transceiver port may be obtained, where the delay feedback signal may include time when the slave node receives the delay determination information.
The second receiving time may be a time when the master node receives the delay feedback signal, and may be determined by an FPGA in the interface board.
Specifically, when receiving the delay feedback signal, the master node may generate a timestamp for identifying a second receiving time of the delay feedback signal, and the determination of the timestamp may be performed by an FPGA in the master node interface board. Furthermore, since the time delay feedback signal can only determine the message receiving time after passing through the signal processing device of the optical monitoring port, the processing time can be determined by the clock phase difference between the time delay feedback signal entering and outputting from the signal processing device, and the processing time can be subtracted on the basis of the second receiving time, so that the real second receiving time of the master node for receiving the time delay feedback signal can be obtained.
Specifically, the first sending time and the second receiving time may be stored in the master node, for example, in an FPGA of the interface board, and when the master-slave time difference is determined, the first sending time and the second receiving time may be sent from the interface board to the master of the master node.
Specifically, the latency feedback information may include a first receiving time and a second sending time of the latency determination signal received from the node, and it is understood that the first receiving time and the second sending time may be times at the optical monitoring port of the interface board in the node.
And 208, determining a master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time.
Specifically, a difference between the first receiving time and the first sending time may be used as the transmission time of the delay determination signal, and a difference between the second receiving time and the second sending time may be used as the transmission time of the delay feedback signal.
And 209, sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference.
In one embodiment, the master-slave time difference is encapsulated into a transmission signal of a preset format; sending the transmission signal to the slave node to enable the slave node to synchronize clock time according to the master-slave time difference.
Specifically, the master-slave time difference may be encapsulated according to a preset format, for example, the master-slave time difference may be encapsulated as TOD information, each TOD information may include 4 time information, which may be a first sending time, a first receiving time, a second sending time, and a second receiving time, and each time information is 10 bytes, 2 CRCs, and 8 bytes of reserved information. The TOD information with the frequency of 1000 times or more can be sent every second, so that the master node and the slave node can acquire the time error in the network element in time, and the slave node can realize the accurate time synchronization of the master node and the slave node according to the master-slave time difference. In the technical scheme of the embodiment of the application, a signal transceiving port is determined by obtaining a board number and a port number of a slave node, a delay determination signal is sent to the information transceiving port from a receiving board optical monitoring port, first sending time of the delay determination signal at an interface board optical monitoring port is determined, second receiving time of a delay feedback signal at the interface board optical monitoring port is determined, the delay feedback signal is analyzed to obtain the first receiving time of the delay determination signal and the second sending time of the delay feedback signal, determining a master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time, sending the master-slave time difference to the slave node, and according to the master-slave time difference, clock time synchronization is carried out with the slave node, so that accurate synchronization of the clock time is realized, errors caused by asymmetry of transmission paths are reduced, and the stability of services is improved.
For example, fig. 5 is an exemplary diagram of a clock time synchronization method provided in this embodiment of the present application, and referring to fig. 5, a delay feedback signal may specifically be a GE signal 0, the GE signal 0 recovered and processed by an optical monitoring port of an interface board may be modified, a custom coded TOD signal 1 is added, the TOD signal may be sent periodically, TOD information with a frequency of 1000 times or more may be sent every second, each TOD information may include 4 time information, which may be sending time and receiving time of a delay determination signal and sending time and receiving time of a delay feedback signal, each time information is 10 bytes, 2 CRCs, 8 bytes of reserved information, and custom coded TOD information is generated at reference numeral 5 in fig. 5. A serdes pin can be introduced for a GE signal, a 250M system clock can be used as a reference clock 2, serdes of an FPGA can extract a 125M CDR clock from an accessed GE signal 0 and divide the frequency to be sent to an SEC chip as a possible clock source 4, a phase difference (a phase difference Δ p of a clock edge) between the 250M system clock 2 and the 125M CDR clock 4 is measured, a phase relationship between the system clock 2 and an edge of a sent GE signal is measured inside the FPGA, a delay from the GE signal 0 of a serdes input pin 5 to a received internal GE signal 6 is measured, a delay from the sent GE signal 8 to a GE signal 7 of a serdes output pin is measured, the delays belong to variation values, and the variation values of the parts can be compensated by measuring the variation values. For sampling using serdes, a 250M system clock can be used as the serdes reference clock, the 125M signal is treated as the sampled signal, so that the DATA of serdes RX is a 250M RX _ GE _ CLK clock plus 32bit wide DATA, note that here the 250M clock RX _ GE _ CLK and 250M system clock are synchronous but out of phase, RX _ GE _ CLK can be provided internally by the FPGA, one normal signal and one DATA GE _ RX _ DATA can be derived by an algorithm from the DATA of RX _ GE _ CLK and 32bit to represent the sampled GE signal, while one RX _ GE _ OFFSET signal is generated to represent the OFFSET of the actual position of the GE signal relative to the rising edge of RX _ GE _ CLK. RX _ GE _ CLK is added to the normal signal to get a recovered clock with 125M clock equal to GE. The logic calculates the phase difference between RX _ GE _ CLK and the 250M system clock, and then calculates the phase difference between the GE signal and the 250M system clock according to RX _ GE _ OFFSET.
Fig. 6 is a flowchart of a clock time synchronization method provided in an embodiment of the present application, where the embodiment of the present application may be applied to a situation of synchronizing a clock time of a network element in a communication network, and the method may be executed by a clock time synchronization apparatus in the embodiment of the present application, where the apparatus may be implemented in a software and/or hardware manner, and may be generally integrated in a slave node of a network element device, referring to fig. 6, the clock time synchronization method in the embodiment of the present application includes:
The signal receiving and transmitting port can be an optical monitoring port in a host node interface board, can be identified with the slave node in advance in a single board number and port number mode, and can be identified with the signal receiving and transmitting port in advance when the slave node receives and transmits signals with the host node.
Specifically, the slave node may monitor the signal transceiving port, and acquire a delay determination signal sent by the master node through the signal transceiving port, where the delay determination signal may be used to determine a communication delay between the master node and the slave node.
In this embodiment of the application, the slave node may further send a delay feedback signal to the master node, where the delay feedback signal may be used to determine transmission time from the slave node to the master node.
And 303, receiving a master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and performing clock time synchronization with the master node according to the master-slave time difference.
Specifically, the slave node may receive a master-slave time difference between a master node and a delay feedback signal according to a delay determination signal and a delay feedback signal, because time consumed by internal processing of a network element node is long, a deviation exists between a synchronized clock time and a real clock time, a time error of a signal processed by the internal processing of the master node and the slave node can be determined by the delay determination signal and the delay feedback signal, and a time difference exists between the master node and the slave node due to the deviation of the internal time.
According to the technical scheme of the embodiment of the application, the time delay determination signal is received through the signal receiving and transmitting port of the slave master node, the time delay feedback signal is sent to the master node, the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal is received, and clock synchronization is carried out with the master node according to the master-slave time difference, so that high-precision synchronization of the clock time of the master node and the clock time of the slave node are achieved, errors caused by time consumption during internal transmission are reduced, and the stability of service is enhanced.
Fig. 7 is a flowchart of a clock time synchronization method provided in an embodiment of the present application, which embodies the clock time for determining a master-slave time difference, and with reference to fig. 7, the clock time synchronization method according to the embodiment of the present application includes:
Specifically, an optical monitoring port in the master node may be determined in advance by a single board number and a port number, and the port may be used as an access point for determining a master-slave time difference between the master node and the slave node.
Specifically, the interface board corresponding to the master node may be searched for according to the board number, the optical monitoring port corresponding to the port number may be determined in the searched interface board, the optical monitoring port may be used as a signal transceiving port for performing signal transmission with the slave node in the master node, and the slave node may monitor the signal transceiving port to obtain the communication signal.
In this embodiment of the present application, the slave node may monitor a signal transceiving port on an interface board in the master node, and acquire a delay determination signal sent by the master node, where the delay determination signal may include time sent by an optical monitoring port in the slave node.
Specifically, the interface board optical monitoring port of the slave node may receive a delay determination signal sent by the master node, and when receiving the delay determination signal, the slave node may determine a first receiving time according to a clock at the interface board of the slave node, where the first receiving time may be a time when the slave node receives the delay determination signal, and the clock time at the interface board is used as the first receiving time, so that accuracy of clock time synchronization between the master node and the slave node may be further improved.
In one embodiment, the determining a first receiving time for receiving the delay determination signal from an interface board optical supervisory port of a node comprises:
acquiring a second incoming clock phase of the time delay determination signal entering the signal processing device in the optical monitoring port of the interface board; acquiring a second output clock phase of the time delay determination signal output from the signal processing device; and taking the phase difference between the second output clock phase and the second incoming clock phase as a first receiving compensation time of the delay determination signal, and determining the first receiving time according to the port clock of the optical monitoring port of the interface board and the first receiving compensation time.
In the embodiment of the present invention, because the received delay determining signal needs to be processed in the network element, and the accurate receiving time of the packet can be obtained only after the processing, the time for processing the delay determining signal needs to be compensated to improve the accuracy of the clock, wherein the signal processing device may specifically be a serdes, and may record the phase of the system clock of the slave node when the delay determining signal enters the signal processing device as the second entering clock phase, may record the phase of the system clock output by the delay determining signal from the signal processing device as the second output clock phase, may calculate the phase difference between the second output clock phase and the second entering clock phase, may use the time length corresponding to the phase difference as the first receiving compensation time for the slave node to process the delay determining signal, and may subtract the first receiving compensation time on the basis that the master node obtains the first receiving time, the time delay received from the node determines the true time of reception of the signal.
Specifically, the delay feedback signal may be a signal that determines a signal transmission time from the slave node to the master node, the delay feedback signal may be sent to the master node by an interface board optical monitoring port of the slave node, and the master node may receive the delay feedback signal through the signal transceiving port.
And step 406, determining a second sending time of the delay feedback signal at the optical monitoring port of the interface board.
In this embodiment of the present application, when the slave node sends the delay feedback signal, a second sending time of the optical monitoring port of the interface board may be determined, where the second sending time may specifically be a clock time output from the node interface board. Further, the second transmission time may be added to the delay feedback signal in the form of timestamp information and transmitted together, or the second transmission time may be separately transmitted to the master node.
Furthermore, since the time delay feedback signal can be transmitted to the slave node only after passing through the signal processing device of the optical monitoring port, the determined transmission time of the time delay feedback signal is earlier than the time for transmitting the time delay feedback signal from the slave node, the processing time can be determined by the clock phase difference between the input and output of the time delay feedback signal from the signal processing device, the processing time can be added on the basis of the second transmission time, and the real time for transmitting the time delay feedback signal from the slave node can be obtained.
Specifically, the slave node may receive a master-slave time difference between a master node determination signal and a delay feedback signal according to a delay, because of an asymmetry problem in communication transmission between the master node and the slave node, a communication delay from the master node to the slave node and a communication delay from the slave node to the master node may be respectively determined by the delay determination signal and the delay feedback signal, the master-slave time difference may be determined by communication delays in two directions at the master node, and the slave node may perform compensation according to the master-slave time difference on the basis of a clock time transmitted from the master node when performing synchronization according to the clock time of the master node.
According to the technical scheme of the embodiment of the application, by obtaining the single plate number and the port number of the main node, determining the optical monitoring port in the main node as a signal transceiving port according to the single plate number and the port number, receiving a delay determination signal sent by the signal transceiving port, determining first receiving time for receiving the delay determination signal, sending a delay feedback signal to the main node, determining second sending time for sending the delay feedback signal, receiving a master-slave time difference determined by the main node according to the delay determination signal and the delay feedback signal, and performing clock time synchronization according to the master-slave time difference, high-precision synchronization of clock time of the main node and the slave node is achieved, time errors caused by signal processing and transmission in a network element are reduced, and service stability is improved.
Fig. 8 is a schematic structural diagram of a clock time synchronization apparatus provided in an embodiment of the present application, which is applicable to a situation of network element clock time synchronization, and is capable of executing a clock time synchronization method provided in any embodiment of the present application, and has corresponding functional modules and beneficial effects of the execution method. The apparatus may be implemented by software and/or hardware, and may be integrated in a master node of a network element, referring to fig. 8, where the apparatus in this embodiment specifically includes: the device comprises an information sending module 501, a signal receiving module 502, a time delay determining module 503 and a clock synchronization module 504.
An information sending module 501, configured to send the delay determining signal to a signal transceiving port in the slave node.
A signal receiving module 502, configured to obtain the time delay feedback signal from the slave node.
A delay determining module 503, configured to determine a master-slave time difference according to the delay feedback signal and the delay determining signal.
A clock synchronization module 504, configured to send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.
According to the technical scheme of the embodiment of the application, the information sending module sends the time delay determination signal to the slave node, the signal receiving module obtains the time delay feedback signal of the slave node, the time delay determination module determines the master-slave time difference between the master node and the slave node through the time delay determination signal and the time delay feedback information, and the clock synchronization module carries out time synchronization according to the master-slave time difference, so that the time difference caused by uncertain time inside the master node is reduced, the accuracy of clock time is improved, the problem of time mutation caused by node state change can be solved, and the stability of service is enhanced.
In one implementation, the apparatus of the embodiment of the present application further includes:
and the port determining module is used for determining a signal receiving and transmitting port according to the acquired single board number and the port number of the slave node.
In one embodiment, the information sending module 501 includes:
and the signal sending unit is used for sending the time delay determination signal from the optical monitoring port of the interface board to the signal transceiving port.
And the sending time unit is used for determining the first sending time of the delay determination signal at the optical monitoring port of the interface board.
In one embodiment, the transmission time unit is specifically configured to:
acquiring a first entering clock phase of the time delay determination signal entering a signal processing device in the optical monitoring port of the interface board; acquiring a first output clock phase of the time delay determination signal output from the signal processing device; and taking the phase difference between the first output clock phase and the first incoming clock phase as the first transmission compensation time of the delay determination signal, and determining the first transmission time according to the port clock of the optical monitoring port of the interface board and the first transmission compensation time.
In one embodiment, the signal receiving module 502 includes:
and the signal receiving unit is used for receiving the time delay feedback signal sent by the signal receiving and sending port of the slave node through an optical monitoring port of an interface board.
And the receiving time unit is used for determining the second receiving time of the delay feedback signal at the optical monitoring port of the interface board.
In one embodiment, the delay determination module 503 includes:
and the time acquisition unit is used for acquiring the first sending time of the time delay determination signal and the second receiving time of the time delay feedback signal in the main node.
And the signal analysis unit is used for analyzing the time delay feedback signal to obtain a first receiving time of the time delay determination signal and a second sending time of the time delay feedback signal.
And the master-slave time difference unit is used for determining the master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time.
In one embodiment, the clock synchronization module 504 includes:
and the signal packaging unit is used for packaging the master-slave time difference into a transmission signal with a preset format.
And the signal sending unit is used for sending the transmission signal to the slave node so that the slave node synchronizes the clock time according to the master-slave time difference.
Fig. 9 is a schematic structural diagram of a clock time synchronization apparatus provided in an embodiment of the present application, which is applicable to a situation of network element clock time synchronization, and is capable of executing a clock time synchronization method provided in any embodiment of the present application, and has corresponding functional modules and beneficial effects of the execution method. The apparatus may be implemented by software and/or hardware, and may be integrated in a slave node of a network element, referring to fig. 9, where the apparatus in this embodiment specifically includes: a signal receiving module 601, a signal feedback module 602 and a clock synchronization module 603.
The signal receiving module 601 is configured to receive a delay determining signal from a signal transceiving port in the host node.
A signal feedback module 602, configured to send a delay feedback signal to the master node.
A clock synchronization module 603, configured to receive a master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.
According to the technical scheme, the signal receiving module receives the time delay determination signal from the signal receiving and transmitting port of the master node, the signal feedback module sends the time delay feedback signal to the master node, the clock synchronization module receives the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and performs clock synchronization with the master node according to the master-slave time difference, so that high-precision synchronization of clock time of the master node and the slave node is achieved, errors caused by internal transmission time consumption are reduced, and the stability of a service can be enhanced.
In one implementation, an apparatus provided in an embodiment of the present application further includes: a port determination module, specifically configured to: acquiring a single board number and a port number of the main node; and taking the optical monitoring port corresponding to the veneer number and the port number in the main node as a signal receiving and transmitting port.
In one embodiment, the signal receiving module 601 includes:
and the delay signal unit is used for receiving the time delay determination signal sent by the signal transceiving port.
And the delay time unit is used for determining the first receiving time of the time delay determination signal received from the optical monitoring port of the interface board of the node.
In one embodiment, the delay time unit is specifically configured to:
acquiring a second incoming clock phase of the time delay determination signal entering the signal processing device in the optical monitoring port of the interface board; acquiring a second output clock phase of the time delay determination signal output from the signal processing device; and taking the phase difference between the second output clock phase and the second incoming clock phase as a first receiving compensation time of the delay determination signal, and determining the first receiving time according to the port clock of the optical monitoring port of the interface board and the first receiving compensation time.
In one embodiment, the signal feedback module 602 includes:
and the feedback signal unit is used for sending the time delay feedback signal from the optical monitoring port of the interface board to the signal transceiving port.
And the feedback time unit is used for determining the second sending time of the delay feedback signal at the optical monitoring port of the interface board.
In one embodiment, the clock synchronization module 603 includes:
and the signal receiving unit is used for receiving the transmission signal with the preset format sent by the main node.
And the signal extraction unit is used for extracting the master-slave time difference in the transmission signals.
And the clock synchronization unit is used for synchronizing the local clock time of the slave node according to the master-slave time difference.
Fig. 10 is a schematic structural diagram of an apparatus provided in an embodiment of the present application, and as shown in fig. 10, the apparatus includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of processors 50 in the device may be one or more, and one processor 50 is taken as an example in fig. 10; the device processor 50, the memory 51, the input device 52 and the output device 53 may be connected by a bus or other means, and the bus connection is exemplified in fig. 10.
The memory 51 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as modules corresponding to the clock time synchronization apparatus in the embodiment of the present application (the information sending module 501, the signal receiving module 502, the delay determining module 503, and the clock synchronization module 504, or the signal receiving module 601, the signal feedback module 602, and the clock synchronization module 603). The processor 50 executes various functional applications of the device and data processing by running software programs, instructions and modules stored in the memory 51, i.e. implements the clock time synchronization method described above.
The memory 51 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 51 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 51 may further include memory located remotely from the processor 50, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 52 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the apparatus. The output device 53 may include a display device such as a display screen.
Embodiments of the present application also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method of clock time synchronization, the method comprising:
transmitting a delay determination signal to a signal transceiving port in the slave node;
acquiring a time delay feedback signal from the slave node;
determining a master-slave time difference according to the time delay feedback signal and the time delay determination signal;
and sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference.
Alternatively, the first and second electrodes may be,
receiving a time delay determination signal from a signal transceiving port in a main node;
sending a time delay feedback signal to the main node;
and receiving the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and performing clock time synchronization with the master node according to the master-slave time difference.
Of course, the storage medium provided in the embodiments of the present application contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the clock time synchronization method provided in any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods described in the embodiments of the present application.
It should be noted that, in the embodiment of the clock time synchronization apparatus, each unit and each module included in the embodiment are only divided according to functional logic, but are not limited to the above division as long as the corresponding function can be implemented; in addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the application.
The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application.
It will be clear to a person skilled in the art that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a car mounted mobile station.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.
Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), optical storage devices and systems (digital versatile disks, DVDs, or CD discs), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as but not limited to general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.
The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the following drawings and the appended claims without departing from the scope of the invention. Therefore, the proper scope of the invention is to be determined according to the claims.
Claims (17)
1. A clock time synchronization method is applied to a master node and comprises the following steps:
transmitting a delay determination signal to a signal transceiving port in the slave node;
acquiring a time delay feedback signal from the slave node;
determining a master-slave time difference according to the time delay feedback signal and the time delay determination signal;
and sending the master-slave time difference to the slave node, and performing clock time synchronization with the slave node according to the master-slave time difference.
2. The method of claim 1, further comprising:
and determining a signal transceiving port according to the acquired single board number and port number of the slave node.
3. The method of claim 1, wherein said transmitting a delay determination signal to a signal transceiving port within a slave node comprises:
sending the time delay determination signal from an optical monitoring port of an interface board to the signal transceiving port;
and determining the first sending time of the time delay determination signal at the optical monitoring port of the interface board.
4. The method of claim 3, wherein said determining a first transmission time of said latency determination signal at said interface board optical supervisory port comprises:
acquiring a first entering clock phase of the time delay determination signal entering a signal processing device in the optical monitoring port of the interface board;
acquiring a first output clock phase of the time delay determination signal output from the signal processing device;
and taking the phase difference between the first output clock phase and the first incoming clock phase as the first transmission compensation time of the delay determination signal, and determining the first transmission time according to the port clock of the optical monitoring port of the interface board and the first transmission compensation time.
5. The method of claim 1, wherein the obtaining the time-delayed feedback signal from the slave node comprises:
receiving the time delay feedback signal sent by the signal transceiving port of the slave node through an interface board optical monitoring port;
and determining the second receiving time of the time delay feedback signal at the optical monitoring port of the interface board.
6. The method of claim 1, wherein determining a master-slave time difference from the time delay feedback signal and the time delay determination signal comprises:
acquiring first sending time of the time delay determination signal and second receiving time of the time delay feedback signal in a main node;
analyzing the time delay feedback signal to obtain a first receiving time of the time delay determination signal and a second sending time of the time delay feedback signal;
and determining a master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time.
7. The method of claim 1, wherein the sending the master-slave time difference to the slave node and the clock time synchronization with the slave node according to the master-slave time difference comprises:
packaging the master-slave time difference into a transmission signal with a preset format;
sending the transmission signal to the slave node to enable the slave node to synchronize clock time according to the master-slave time difference.
8. A clock time synchronization method is applied to a slave node and comprises the following steps:
receiving a time delay determination signal from a signal transceiving port in a main node;
sending a time delay feedback signal to the main node;
and receiving the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and performing clock time synchronization with the master node according to the master-slave time difference.
9. The method of claim 8, wherein prior to receiving the delay determination signal from the signal transceiving port within the master node, further comprising:
acquiring a single board number and a port number of the main node;
and taking the optical monitoring port corresponding to the veneer number and the port number in the main node as a signal receiving and transmitting port.
10. The method of claim 8, wherein receiving the delay determination signal from a signal transceiving port within the master node comprises:
receiving the time delay determination signal sent by the signal transceiving port;
a first reception time for receiving the delay determination signal from an interface board optical supervisory port of a node is determined.
11. The method of claim 10, wherein determining a first receive time for receiving the delay determination signal from an interface board optical supervisory port of a node comprises:
acquiring a second incoming clock phase of the time delay determination signal entering the signal processing device in the optical monitoring port of the interface board;
acquiring a second output clock phase of the time delay determination signal output from the signal processing device;
and taking the phase difference between the second output clock phase and the second incoming clock phase as a first receiving compensation time of the delay determination signal, and determining the first receiving time according to the port clock of the optical monitoring port of the interface board and the first receiving compensation time.
12. The method of claim 8, wherein the sending a time delayed feedback signal to the master node comprises:
sending the time delay feedback signal from an optical monitoring port of an interface board to the signal transceiving port;
and determining the second sending time of the time delay feedback signal at the optical monitoring port of the interface board.
13. The method of claim 8, wherein the receiving a master-slave time difference determined by the master node based on the delay determination signal and the delay feedback signal and performing clock time synchronization with the master node based on the master-slave time difference comprises:
receiving a transmission signal in a preset format sent by the main node;
extracting a master-slave time difference in the transmission signal;
and synchronizing the local clock time of the slave nodes according to the master-slave time difference.
14. A clock time synchronization device applied to a master node comprises:
the information sending module is used for sending a time delay determination signal to a signal receiving and sending port in the slave node;
a signal receiving module, configured to obtain a time delay feedback signal from the slave node;
the time delay determining module is used for determining master-slave time difference according to the time delay feedback signal and the time delay determining signal;
and the clock synchronization module is used for sending the master-slave time difference to the slave node and carrying out clock time synchronization with the slave node according to the master-slave time difference.
15. A clock time synchronization apparatus applied to a slave node, comprising:
the signal receiving module is used for receiving the time delay determination signal from a signal receiving and transmitting port in the main node;
the signal feedback module is used for sending a time delay feedback signal to the main node;
and the clock synchronization module is used for receiving the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal and carrying out clock time synchronization with the master node according to the master-slave time difference.
16. An apparatus, comprising:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the clock time synchronization method of any of claims 1-13.
17. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out a method for clock time synchronization according to any one of claims 1 to 13.
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| CN201911371412.5A CN113055113A (en) | 2019-12-26 | 2019-12-26 | Clock time synchronization method, device, equipment and storage medium |
| PCT/CN2020/139083 WO2021129755A1 (en) | 2019-12-26 | 2020-12-24 | Clock time synchronization method, apparatus and device, and storage medium |
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|---|---|---|---|---|
| CN117240428A (en) * | 2023-11-15 | 2023-12-15 | 北京航天晨信科技有限责任公司 | Clock synchronization method, clock synchronization device, electronic equipment and computer readable storage medium |
| CN117394972A (en) * | 2023-10-23 | 2024-01-12 | 合芯科技有限公司 | Transmission delay determining method, system and processing chip |
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| CN101515831B (en) * | 2008-02-22 | 2013-08-28 | 杭州华三通信技术有限公司 | Method, system and device for time synchronous transfer |
| CN103078699B (en) * | 2012-12-28 | 2015-08-05 | 华为技术有限公司 | Method and the network equipment of time synchronized is carried out based on precision time protocol |
| CN107579793A (en) * | 2016-07-04 | 2018-01-12 | 中兴通讯股份有限公司 | The optimization method of time synchronized, device and equipment between a kind of communication network device |
| CN109818701B (en) * | 2019-02-19 | 2021-03-02 | 烽火通信科技股份有限公司 | High-precision clock synchronization method and system for communication equipment |
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- 2019-12-26 CN CN201911371412.5A patent/CN113055113A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117394972A (en) * | 2023-10-23 | 2024-01-12 | 合芯科技有限公司 | Transmission delay determining method, system and processing chip |
| CN117240428A (en) * | 2023-11-15 | 2023-12-15 | 北京航天晨信科技有限责任公司 | Clock synchronization method, clock synchronization device, electronic equipment and computer readable storage medium |
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