CN114267678A

CN114267678A - Memory device

Info

Publication number: CN114267678A
Application number: CN202111574820.8A
Authority: CN
Inventors: 詹益旺; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-09-04
Filing date: 2020-09-04
Publication date: 2022-04-01
Also published as: CN112018080B; CN112018080A

Abstract

The invention provides a memory. By forming the side wall nitride layer on at least part of the side wall of the bit line, the problem of bit line oxidation can be avoided under the isolation protection of the side wall nitride layer. Especially, when the bit line comprises the metal material layer, the side wall metal nitride layer can be formed on the side wall of the metal material layer, so that the problem that the metal material layer is oxidized can be prevented, and the electric conduction performance of the bit line can be further improved to ensure the electric conduction performance of the bit line.

Description

Memory device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory.

Background

As the semiconductor industry enters a new era of high performance and multi-function integrated circuits, the size of the semiconductor devices in the integrated circuits is gradually reduced to meet the increasing trend of the density of the integrated circuits. As the size of conductive parts for realizing electrical transmission in semiconductor devices is continuously reduced, how to ensure the conductive performance is still an important issue in the field.

Disclosure of Invention

The present invention provides a memory device for ensuring the electrical conductivity of bit lines. The present invention provides a memory, comprising: a substrate having a plurality of active regions defined therein; a plurality of bit line contacts in the substrate and electrically connected to the plurality of active regions; the bit lines cover the bit line contact parts and comprise bottom polycrystalline silicon layers, metal material layers and dielectric material shielding layers which are sequentially stacked, and the side walls of the metal material layers are provided with side wall metal nitride layers; and the insulating cover layer covers the dielectric material cover layer, the side wall metal nitride layer on the side wall of the metal material layer and the bottom layer polycrystalline silicon layer.

Optionally, the bit line further includes a thin film metal nitride layer, the thin film metal nitride layer is located below the metal material layer, and the bottom of the sidewall metal nitride layer on the sidewall of the metal material layer is connected to the sidewall of the thin film metal nitride layer.

Optionally, the bottom polysilicon layer is located on the bit line contact, and a sidewall of the bottom polysilicon layer has a sidewall silicon nitride layer.

Optionally, the material of the bit line contact portion includes polysilicon, and a sidewall of the bit line contact portion has a sidewall silicon oxide layer, the sidewall silicon oxide layer is located between the insulating cover layer and the polysilicon material of the bit line contact portion, and a thickness of the sidewall silicon oxide layer is greater than a thickness of the sidewall silicon nitride layer.

Optionally, the sidewall of the bit line contact has a first sidewall oxide layer, and the first sidewall oxide layer is in direct contact with the bit line contact.

Optionally, the thickness of the sidewall metal nitride layer is greater than that of the first sidewall oxide layer.

Optionally, the memory further includes an insulating cap layer, the insulating cap layer continuously covers the bit line and the bit line contact, and a dielectric constant of the first sidewall oxide layer is lower than a dielectric constant of the insulating cap layer.

Optionally, the substrate has a plurality of bit line contacts, at least the bottoms of the bit line contacts expose the active region, the bit line contacts are in one-to-one correspondence with the bit line contacts, and at least part of the bottoms of the first sidewall oxide layers contact the active region.

Optionally, the bit line contact window exceeds the active region in the width direction of the active region to laterally extend into the adjacent isolation region, and the first sidewall oxide layer laterally extends from the active region into the isolation region, so that the bottom of the first sidewall oxide layer also contacts the inner wall of the trench in the isolation region.

In the memory provided by the invention, the sidewall nitride layer is also formed on at least part of the sidewall of the bit line, so that the problem of oxidation of the bit line can be avoided under the isolation protection of the sidewall nitride layer, and the electrical conductivity of the bit line is ensured. Particularly, when the bit line comprises the metal material layer, the sidewall metal nitride layer can be formed on the sidewall of the metal material layer, so that the problem that the metal material layer is oxidized can be prevented, and the electrical conductivity of the bit line can be further improved.

Drawings

FIG. 1 is a diagram illustrating a memory structure according to an embodiment of the present invention;

FIG. 2a is a schematic diagram of a memory device according to an embodiment of the present invention, further illustrating a structure of an insulating capping layer;

FIG. 2b is an enlarged view of a portion of area A of the schematic structure shown in FIG. 2 a;

FIG. 3 is a flow chart illustrating a method for forming a memory according to an embodiment of the invention;

fig. 4a to 4f are schematic structural diagrams illustrating a method for forming a memory device according to an embodiment of the invention during a manufacturing process thereof.

Wherein the reference numbers are as follows:

100-a substrate;

110-trench isolation structures;

120-bit line contact windows;

200-bit line contacts;

200 a-a first sidewall oxide layer;

210-a bit line contact material layer;

300-bit lines;

310-a bottom polysilicon layer;

310 a-sidewall silicon oxide layer;

320-a thin film metal nitride layer;

330-a metallic material layer;

330 a-sidewall metal nitride layer;

340-a dielectric material shielding layer;

400-insulating capping layer;

500-second sidewall oxide layer;

600-isolating layer.

Detailed Description

The memory proposed by the present invention is further explained in detail below with reference to the drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a schematic structural diagram of a memory according to an embodiment of the invention, fig. 2a is a schematic structural diagram of an insulating capping layer of the memory according to an embodiment of the invention, and fig. 2b is a partially enlarged view of a region a in the schematic structural diagram shown in fig. 2 a.

With particular reference to fig. 1 and 2b, the memory comprises: a substrate 100 and a bit line formed on the substrate 100. The bit line includes a bit line 300 and a bit line contact 200 formed under the bit line 300 and electrically connected to the bit line 300.

Specifically, a plurality of active regions AA are formed in the substrate 100, and an isolation region may be formed between adjacent active regions AA to separate adjacent active regions AA from each other. In this embodiment, a plurality of trench isolation structures 110 are formed in the substrate 100, and the trench isolation structures 110 surround the periphery of the active area AA and are used for isolating adjacent active areas AA. It will also be appreciated that the active area AA is defined by forming the trench isolation structure 110.

Further, the active area AA has a first source/drain area S/D1 and a second source/drain area S/D2 therein. And the active regions AA may extend in a first direction, and the first source/drain regions S/D1 in each of the active regions AA correspond to a middle region of the active region AA, and the second source/drain regions S/D2 are formed on both ends of the active region AA (i.e., two second source/drain regions S/D2 are respectively disposed on both sides of the first source/drain regions S/D1).

The active area AA is used to form a memory cell of the memory, such as a memory transistor. And, the first source/drain region S/D1 and the second source/drain region S/D2 may be used to form a drain region and a source region of the memory transistor, and the first source/drain region S/D1 is electrically connected to a bit line (specifically, a bit line contact 200 is formed on each of the first source/drain regions S/D1, such that the first source/drain region S/D1 may be further electrically connected to the bit line 300 through the bit line contact 200), and the second source/drain region S/D2 is electrically connected to a storage node contact to be further electrically connected to a storage capacitor through the storage node contact.

With continued reference to fig. 1 and 2b, in the present embodiment, the bit line contact 200 is formed in the substrate 100. Specifically, a plurality of bit line contacts 200 are formed in a one-to-one correspondence in the plurality of bit line contacts by forming the plurality of bit line contacts in the substrate 100. At least the bottom of the bit line contact exposes a portion of the active area AA (in this embodiment, the bit line contact exposes the first source/drain area S/D1), so that the bit line contact 200 formed in the bit line contact electrically contacts the active area AA.

Further, the bit line contact window exceeds the active region in the width direction of the active region to extend laterally into the isolation region adjacent to the corresponding active region (in the present embodiment, into the trench isolation structure 110), that is, the opening size of the bit line contact window in the width direction of the active region is larger than the width size of the active region, so that the first source/drain region S/D1 is exposed in an area as large as possible, and the bit line contact window based on the large opening size is also beneficial to reducing the difficulty in manufacturing the bit line contact 200. And the bottom surface of the bit line contact window is higher than the bottom boundary of the first source/drain region S/D1, namely, the depth of the recess of the bit line contact window in the substrate 100 is less than the doping depth of the first source/drain region S/D1 in the substrate.

With continued reference to fig. 1, the sidewalls of the bit line contact 200 are further formed with a first sidewall oxide layer 200a, and the first sidewall oxide layer 200a is formed by, for example, performing an oxidation process on the bit line contact 200. Specifically, the material of the bit line contact 200 may include polysilicon, and the first sidewall oxide layer 200a is a sidewall oxide layer.

That is, in this embodiment, the sidewall of the bit line contact 200 is preferentially covered with the first sidewall oxide layer 200a with a low dielectric constant, so that the sidewall of the bit line contact 200 is primarily isolated by the first sidewall oxide layer 200a, which is equivalent to reducing the dielectric constant of the dielectric material between the adjacent bit lines, and is beneficial to reducing the coupling capacitance between the adjacent bit lines.

Referring to fig. 2b with emphasis, the bottom of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 at least partially contacts the active region AA. Further, the first sidewall oxide layer 200a further laterally extends from the active area AA into the isolation region, so that the bottom of the first sidewall oxide layer 200a further contacts the inner wall of the trench in the isolation region. That is, in the present embodiment, the first sidewall oxide layer 200a covers the edge of the active area AA and extends to the trench isolation structure 110. At this time, the active region corresponding to the bit line contact is covered by the bit line contact 200 and the first sidewall oxide layer 200a on the sidewall thereof without being exposed.

In addition, an isolation layer 600 is formed on the top surface of the substrate 100, and an opening is formed in the isolation layer 600 corresponding to the region of the bit line contact. It is understood that the bit line contact window penetrates the isolation layer 600 and extends down into the substrate 100, and the top surface of the bit line contact portion 200 is flush with the top surface of the isolation layer 600, and the bit line 300 is formed above the isolation layer 600. In this embodiment, the isolation layer 600 exposes the first source/drain region and covers the second source/drain region, and at this time, the isolation layer 600 can be used to prevent the bit line 300 formed above the substrate from being electrically connected to the second source/drain region.

With continued reference to fig. 1, the bit line 300 is formed on the isolation layer 600 and extends along a predetermined direction, and the bit line 300 further covers a plurality of bit line contacts 200 arranged on an extension path thereof. That is, a plurality of bit line contacts 200 on the extension path of the bit line 300 are electrically connected to the bit line 300 to enable electrical transmission between the bit line 300 and the corresponding active region through the bit line contacts 200.

Further, at least a portion of the sidewalls of the bit line 300 is further formed with a sidewall nitride layer (the sidewall nitride layer in this embodiment includes a sidewall metal nitride layer 330a and a sidewall silicon nitride layer 310a) based on a nitridation process. It should be noted that, since the sidewall nitride layer is formed on the sidewall of the bit line 300, the risk of oxidation of the bit line 300 can be avoided under the isolation protection of the sidewall nitride layer (for example, when the sidewall of the bit line contact 200 is oxidized to form the first sidewall oxide layer 200a, the bit line 300 can be prevented from being oxidized under the isolation protection of the sidewall nitride layer). In particular, when the bit line 300 includes a metal material layer, the metal material layer, after being oxidized, may directly adversely affect the conductive performance thereof.

In this embodiment, the bit line 300 includes a bottom polysilicon layer 310, a thin film metal nitride layer 320 and a metal material layer 330 stacked in sequence from bottom to top. The material of the metal nitride layer 320 may further include tungsten nitride, titanium nitride, tantalum nitride, or the like, and the material of the metal material layer 330 includes tungsten, for example.

With continued reference to fig. 1, the sidewall of the metal material layer 330 in the bit line 300 is formed with a sidewall metal nitride layer 330a based on a nitridation process, and the bottom of the sidewall metal nitride layer 330a is connected to the sidewall of the thin film metal nitride layer 320. It is believed that in the present embodiment, the bottom wall and the sidewall of the metal material layer 330 are surrounded by the nitride layer, so that on one hand, the problem that the metal material layer 330 is easily oxidized is avoided, and on the other hand, the electrical conductivity of the bit line 300 is improved. Meanwhile, the metal nitride layer (including the sidewall metal nitride layer 330a) can be used to realize the metal diffusion barrier function of the metal material layer 330, so as to prevent the metal in the metal material layer 330 from diffusing into the peripheral dielectric material layer (not shown in the figure) and prevent the adjacent bit lines from having the electrical crosstalk problem.

In this embodiment, the thickness of the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330 is further greater than the thickness of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200.

With continued reference to fig. 1, the bottom polysilicon layer 310 in the bit line 300 is formed in direct contact with the bit line contact 200, and the sidewall of the bottom polysilicon layer 310 is formed with a sidewall silicon nitride layer 310a based on a nitridation process. Wherein the thickness of the sidewall silicon nitride layer 310a is less than the thickness of the sidewall metal nitride layer 330 a.

In this embodiment, the material of the bit line contact 200 may also include polysilicon, and the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 may include a sidewall silicon oxide layer, and the thickness of the sidewall silicon oxide layer is greater than the thickness of the sidewall silicon nitride layer 310 a.

In a further aspect, the bit line 300 further includes a shielding layer 340 made of a dielectric material, and the shielding layer 340 made of a dielectric material is formed on the metal material layer 330 to cover a top surface of the metal material layer 330. Wherein the dielectric material shielding layer 340 includes, for example, a silicon nitride layer.

Referring next to fig. 2a and 2b, the memory further includes an insulating cap layer 400, wherein the insulating cap layer 400 continuously covers the bit line 300 and the bit line contact 200. In this embodiment, the insulating capping layer 400 covers the dielectric material shielding layer 340, the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330, the thin film metal nitride layer 320, the sidewall silicon nitride layer 310a on the sidewall of the bottom polysilicon layer 310, and the first sidewall oxide layer 200a on the sidewall of the bit line contact 200.

Namely, by using the insulating capping layer 400, on one hand, the adjacent bit lines BL can be further isolated, and on the other hand, the mechanical strength of the bit lines BL can be improved, so that the complete appearance of the bit lines BL is ensured. Specifically, the material of the insulating cap layer 400 includes, for example, silicon nitride.

Further, the dielectric constant of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 is lower than that of the insulating capping layer 400. In this embodiment, the dielectric constant of the sidewall silicon oxide layer on the sidewall of the bit line contact 200 is lower than that of the silicon nitride material of the insulating capping layer 400, which is favorable for reducing the overall dielectric constant of the dielectric material between the adjacent bit lines BL, so as to correspondingly reduce the parasitic capacitance between the adjacent bit lines BL.

In this embodiment, the insulating capping layer 400 further extends to cover the sidewall of the trench extending from the bit line contact to the trench isolation structure, and further covers the isolation layer 600 between adjacent bit lines BL.

In addition, as shown in fig. 2b, since the width of the bit line contact 200 is smaller than the opening of the bit line contact, a certain distance is formed between the sidewall of the bit line contact 200 and the sidewall of the trench of the bit line contact, and at this time, an insulating material (e.g., a second sidewall oxide layer 500) may be further filled between the first sidewall oxide layer 200a and the sidewall of the trench.

In this embodiment, after the bit line contact is covered with the insulating cap layer 400, an inner trench is surrounded by the insulating cap layer 400 at the side of the bit line contact 200, and the second sidewall oxide layer 500 is filled in the inner trench. And, the highest interface of the second sidewall oxide layer 500 may be further higher than that of the first sidewall oxide layer 200 a. Specifically, the insulating capping layer 400 covers the trench sidewall of the bit line contact, and further extends to cover the top surface of the isolation layer 600, so that the highest interface of the insulating capping layer 400 on the isolation layer 600 is higher than the highest interface of the first sidewall oxide layer 200a, in this embodiment, the highest interface of the second sidewall oxide layer 500 and the highest interface of the insulating capping layer 400 on the isolation layer 600 are flush or nearly flush.

Based on the memory described above, the forming method thereof will be described in detail below with reference to fig. 3 and 4a to 4 f. Fig. 3 is a schematic flow chart of a method for forming a memory according to an embodiment of the present invention, and fig. 4a to 4f are schematic structural diagrams of the method for forming a memory according to an embodiment of the present invention during a manufacturing process thereof.

First, step S100 is performed, and referring to fig. 4a in particular, a substrate 100 is provided, a plurality of active regions AA are defined in the substrate 100, and a plurality of bit line contacts 120 are formed in the substrate 100, wherein at least the bottom of the bit line contacts 120 expose the active regions AA. In this embodiment, the bit line contact 120 exposes the first source/drain region in the active region AA.

Specifically, a plurality of trench isolation structures 110 may be formed in the substrate 100 to define a plurality of active regions AA. And, the first and second source/drain regions in the active area AA may be formed by an ion implantation process.

With continuing reference to FIG. 4a, before forming the bit line contact 120, the method further comprises: an isolation layer 600 is formed on the top surface of the substrate 100, the isolation layer 600 covering the active area AA thereunder.

And, the bit line contact 120 may be formed by performing a photolithography process on the basis of a reticle, for example, and further performing an etching process on the substrate 100. In this embodiment, the bit line contact 120 penetrates through the isolation layer 600 and extends downward into the substrate 100.

Further, the opening size of the bit line contact window 120 is larger than the size of the first source/drain region S/D1, such that the first source/drain region S/D1 can be exposed to a greater extent, such that the first source/drain region S/D1 can be electrically contacted with the subsequently formed bit line contact with a larger area. For example, in the present embodiment, the width dimension of the bit line contact window 120 is greater than the width dimension of the first source/drain region S/D1 in both the direction perpendicular to the extension direction of the active region and in the extension direction along the active region. That is, the bitline contact 120 exposes the first source/drain region S/D1 and also laterally expands to expose the trench isolation structure 110 adjacent to the first source/drain region.

The opening shape of the bitline contact 120 may be an ellipse, a circle, a rectangle, a diamond, or other polygons, and the like, which is not limited herein.

Next, step S200 is performed, and referring to fig. 4b in particular, a layer 210 of bit line contact material is filled in the bit line contact windows 120. The material of the bit line contact material layer 210 includes, for example, polysilicon.

Further, the bit line contact material layer 210 may be formed in conjunction with a planarization process. Specifically, the method for forming the bit line contact material layer 210 includes, for example: a chemical mechanical polishing process is performed with the isolation layer 600 as a polishing stop layer, so that the formed bit line contact material layer 210 is aligned and filled in the bit line contact window, and the top surface of the bit line contact material layer 210 is flush with the top surface of the isolation layer 600.

Next, step S300 is performed, and referring to fig. 4c in particular, a bit line 300 is formed on the substrate 100, wherein the bit line 300 extends along a predetermined direction and covers the plurality of bit line contact material layers 210 arranged on the extending path thereof. In this embodiment, the bit line 300 is formed on the isolation layer 600 and covers the bit line contact material layer 210, and the width of the bit line 300 is smaller than the width of the bit line contact material layer 210, so that the bit line contact material layer 210 is partially exposed.

Specifically, the method for forming the bit line 300 includes: firstly, a conductive material layer and a dielectric material layer are sequentially formed on the substrate 100; then, an etching process is performed to sequentially pattern the dielectric material layer and the conductive material layer, thereby forming a dielectric material shielding layer 340 and a conductive layer, respectively, to form the bit line 300. Further, when the conductive material layer is etched, an etching end point detection may be performed with the isolation layer 600 as an end point, so that the etching is stopped on the isolation layer 600, and at this time, the corresponding etching is stopped on the bit line contact material layer 210.

In practical application, when the etching process is performed, the substrate structure is placed in an etching chamber and a first etching gas is introduced to etch the conductive material layer. The conductive layer of the bit line 300 includes a bottom polysilicon layer 310, a thin film metal nitride layer 320, and a metal material layer 330 stacked in sequence from bottom to top. The material of the thin-film metal nitride layer 320 may further include tungsten nitride, titanium nitride, tantalum nitride, or the like, and the material of the metal material layer 330 includes tungsten, for example.

In addition, as described above, the width of the bit line 300 is smaller than the width of the bit line contact material layer 210, so that the bit line 300 covers the bit line contact material layer 210 from the middle region of the bit line contact material layer 210 and the two side regions of the bit line contact material layer 210 are exposed from the two sides of the bit line 300.

Then, step S400 is performed, and referring to FIG. 4d, a nitridation process is performed to form a sidewall nitride layer on at least a portion of the sidewalls of the bit line 300.

Specifically, through the nitridation process, the sidewall of the bottom polysilicon layer 310 in the bit line 300 may be nitrided to form a sidewall silicon nitride layer 310a, and the sidewall of the metal material layer 330 in the bit line 300 may also be nitrided to form a sidewall metal nitride layer 330a, and the bottom of the sidewall metal nitride layer 330a is further connected to the thin film metal nitride layer 320. In this embodiment, the metal material layer 330 is made of tungsten, and based on this, the sidewall metal nitride layer 330a is made of tungsten nitride. In addition, the exposed top surface of the bit line contact material layer 210 may also be partially nitrided by the nitridation process.

In practical applications, the nitridation process may also be performed in the etch chamber. Specifically, when the conductive material layer is etched in the etching chamber to form the bit line 300, after the etching end point is detected, the first etching gas is stopped to be introduced, and nitrogen is introduced into the etching chamber to perform nitridation on the sidewall of the bit line 300. That is, the sidewall nitride layer on the sidewall of the bit line 300 can be directly formed in the same etching chamber without replacing the semiconductor processing equipment, thereby greatly simplifying the processing flow of the device and shortening the manufacturing time of the device.

Next, step S500 is executed, and referring to fig. 4e in particular, the bit line contact material layer is etched by using the bit line 300 as a mask to form the bit line contact 200 in the bit line contact window.

In practical application, the bit line contact material layer can be etched in the same etching cavity. Specifically, after the nitridation treatment is performed, a second etching gas is introduced into the etching cavity to etch the bit line contact material layer, so that the processing efficiency of the device is further improved.

As described above, after the nitridation process, a nitride layer may be formed on the top surface of the bit line contact material layer, but the nitride layer on the top surface of the bit line contact material layer has a small thickness (much smaller than the thickness of the isolation layer 600), so that a small amount of nitride layer on the top surface of the bit line contact material layer can be consumed quickly when the bit line contact material layer is etched, and the bit line contact material layer is further etched downward to form the bit line contact 200.

And, optionally, when the bit line contact material layer is etched, the sidewall silicon nitride layer 310a on the sidewall of the bottom polysilicon layer 310 may be slightly etched, so that the thickness of the sidewall silicon nitride layer 310a on the sidewall of the bottom polysilicon layer 310 is reduced, for example, smaller than the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330.

In a further aspect, the method for forming the memory further includes: in step S600, a first sidewall oxide layer 200a is formed on the sidewall of the bit line contact 200.

Referring specifically to fig. 4f, an oxidation process is performed to form the first sidewall oxide layer 200a on the sidewalls of the bit line contact 200. In this embodiment, the first sidewall oxide layer 200a is a sidewall oxide layer.

It should be noted that, when the oxidation process is performed, since the sidewall of the metal material layer 330 in the bit line 300 is covered with the sidewall nitride layer (i.e., the sidewall metal nitride layer 330a), the problem that the metal material layer 330 is oxidized during the oxidation process can be effectively avoided, and the electrical conductivity of the bit line 300 is ensured.

In addition, in the present embodiment, before the oxidation process is performed, the edges of the active region (the first source/drain region S/D1 in the present embodiment) are also exposed from both sides of the bit line contact 200. Accordingly, the bottom of the first sidewall oxide layer 200a may be brought into contact with the active region when the oxidation process is performed. And, the process parameters of the oxidation treatment can be controlled until the formed first sidewall oxide layer 200a further extends laterally from the active region into the isolation region, so that the bottom of the first sidewall oxide layer 200a further contacts the inner wall of the trench in the isolation region, thus ensuring that the active region can be completely covered.

Alternatively, the thickness of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 may be further greater than the thickness of the sidewall silicon nitride layer 310a on the sidewall of the underlying polysilicon layer 310.

Further, after the oxidation treatment is performed, the method further includes: an insulating cap layer is formed on the substrate 100.

As can be seen in conjunction with fig. 2a and 2b, the insulating capping layer 400 at least covers the bit lines (i.e., covers the bit lines 300 and the bit line contacts 200). Wherein, the material of the insulating cap layer 400 includes silicon nitride, for example. And, the insulating cap layer 400 can conformally cover the bit line 300 and the bit line contact 200, and also cover the exposed trench sidewall in the bit line contact window, so that the inner trench can be surrounded by the insulating cap layer 400 at the side of the bit line contact 200.

Based on this, after the forming of the insulating capping layer 400, the method may further include: the second sidewall oxide layer 500 is filled in the bit line contact window, and the second sidewall oxide layer 500 is filled at the side of the bit line contact 200.

In this embodiment, the insulating cap layer 400 covers the trench sidewall of the bit line contact, and also extends to cover the top surface of the isolation layer 600, so that the highest interface of the insulating cap layer 400 on the isolation layer 600 is higher than the highest interface of the first sidewall oxide layer 200 a. And, the second sidewall oxide layer 500 may be prepared based on the insulating cap layer 400, such that the highest interface of the second sidewall oxide layer 500 is flush or nearly flush with the highest interface of the insulating cap layer 400 covering the isolation layer 600, where the highest interface of the second sidewall oxide layer 500 is higher than the highest interface of the first sidewall oxide layer 200 a. Thus, the bit line contact 200 and the first sidewall oxide layer 200a on the sidewall thereof can be stably buried in the bit line contact window, thereby improving the overall stability and mechanical strength of the formed bit line.

In summary, in the memory provided in this embodiment, the first sidewall oxide layer with a low dielectric constant is disposed on the sidewall of the bit line contact portion, and the insulating capping layer may be further disposed to cover the bit line contact portion and the bit line, so that on one hand, the overall dielectric constant of the dielectric material between adjacent bit lines is reduced, and on the other hand, the mechanical strength of the bit line is ensured, thereby avoiding the problem of bit line deformation and even collapse.

In addition, in this embodiment, at least a portion of the sidewalls of the bit lines further have a sidewall nitride layer, and the sidewall nitride layer not only can effectively protect the metal material layer in the bit lines and prevent the metal material layer from being oxidized, but also can function as a metal diffusion barrier, thereby further improving the electrical conductivity of the formed bit lines.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise.

Claims

1. A memory, comprising:

a substrate having a plurality of active regions defined therein;

a plurality of bit line contacts in the substrate and connected to the plurality of active regions;

the bit lines cover the bit line contact parts and comprise bottom polysilicon layers, metal material layers and dielectric material shielding layers which are sequentially stacked, wherein the side walls of the metal material layers are provided with side wall metal nitride layers;

and the insulating cover layer covers the dielectric material cover layer, the side wall metal nitride layer on the side wall of the metal material layer and the bottom layer polycrystalline silicon layer.

2. The memory of claim 1, wherein the bit line further comprises a thin film metal nitride layer located below the metal material layer, and wherein a bottom of the sidewall metal nitride layer on the sidewall of the metal material layer is connected to the sidewall of the thin film metal nitride layer.

3. The memory of claim 1, wherein the bottom polysilicon layer is on the bit line contact and a sidewall of the bottom polysilicon layer has a sidewall silicon nitride layer.

4. The memory of claim 3, wherein the bit line contact material comprises polysilicon and the sidewall of the bit line contact has a sidewall silicon oxide layer between the insulating cap layer and the polysilicon material of the bit line contact, the sidewall silicon oxide layer having a thickness greater than a thickness of the sidewall silicon nitride layer.

5. The memory of claim 1, wherein sidewalls of the bit line contact have a first sidewall oxide layer, the first sidewall oxide layer and the bit line contact being in direct contact.

6. The memory of claim 5, wherein a thickness of the sidewall metal nitride layer is greater than a thickness of the first sidewall oxide layer.

7. The memory of claim 5, wherein the insulating cap layer continuously covers the bit line and the bit line contact, and the first sidewall oxide layer has a dielectric constant lower than that of the insulating cap layer.

8. The memory of claim 5, wherein the substrate has a plurality of bit line contacts therein, at least bottoms of the bit line contacts expose the active region, and the plurality of bit line contacts are in one-to-one correspondence in the plurality of bit line contacts, and bottoms of the first sidewall oxide layers at least partially contact the active region.

9. The memory of claim 8 wherein the bitline contact window extends beyond the active region in a width direction of the active region to extend laterally into the adjoining isolation region, and the first sidewall oxide extends laterally from the active region into the isolation region such that a bottom of the first sidewall oxide also contacts an inner wall of the trench located in the isolation region.