CN114256381B - N-type TopCon battery piece and preparation method thereof - Google Patents

N-type TopCon battery piece and preparation method thereof Download PDF

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CN114256381B
CN114256381B CN202111314179.4A CN202111314179A CN114256381B CN 114256381 B CN114256381 B CN 114256381B CN 202111314179 A CN202111314179 A CN 202111314179A CN 114256381 B CN114256381 B CN 114256381B
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silicon wafer
silicon
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battery
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CN114256381A (en
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张东威
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Ordos Longji Photovoltaic Technology Co ltd
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Xian Longi Solar Technology Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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Abstract

The invention discloses an N-type TopCon battery piece and a preparation method thereof. The preparation method comprises the following steps: providing an N-type silicon wafer with one side containing boron diffusion; taking one side of the silicon wafer, which is away from boron diffusion, as a back surface, performing back surface polishing treatment on the silicon wafer, and forming a square morphology with expected size on the back surface of the silicon wafer; depositing a silicon oxide layer on the back of the silicon wafer; carrying out partial laser grooving on the silicon oxide layer to remove the silicon oxide layer at the grooving part and cauterizing the lower silicon layer to form an inverted pyramid structure; carrying out back corrosion treatment on the obtained silicon wafer, and removing the silicon oxide layer in the non-laser area; and depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the obtained silicon wafer, wherein a metal grid line on the back surface of the silicon wafer is arranged at a position corresponding to the slotted pattern. The method can improve the passivation effect of the back surface of the silicon wafer, can improve the contact performance of the metal electrode of the back surface of the silicon wafer and the silicon substrate, can reduce the resistance of the battery, and can improve the open-circuit voltage, the filling factor and the battery conversion efficiency of the battery.

Description

N-type TopCon battery piece and preparation method thereof
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to an N-type TopCon cell and a preparation method thereof.
Background
At present, the mainstream battery product in the photovoltaic market is a P-type Perc battery, the most probable of the next generation of upgrading products is an N-type TopCon battery, and a back polishing process is needed after boron diffusion of the TopCon battery in a conventional process route, so that the purpose is to remove boron diffusion and coiling plating on the side edge and the back edge of a silicon wafer, and simultaneously, a back small square structure is formed, and the back passivation effect is enhanced. In order to be compatible with the contact performance of the back metal of the battery, the size of the alkaline polishing square block of the back of the battery can only be controlled to be 5 mu m, and compared with a back surface morphology structure with a larger square size (more than 20 mu m), the passivation effect is relatively poor, and the improvement of the battery performance is limited.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present invention is to provide an N-type TopCon battery sheet and a method for preparing the same, wherein the method can improve passivation effect of the back surface of a silicon wafer, improve contact performance between a metal electrode on the back surface of the silicon wafer and a silicon substrate, reduce resistance of a battery, and improve open circuit voltage, filling factor and conversion efficiency of the battery.
In one aspect of the invention, a method of making an N-type TopCon battery sheet is provided. According to an embodiment of the invention, the method comprises:
(1) Providing an N-type silicon wafer with one side containing boron diffusion;
(2) Taking one side of the silicon wafer, which is away from boron diffusion, as a back surface, and performing back surface polishing treatment on the silicon wafer so as to form a square morphology with expected size on the back surface of the silicon wafer;
(3) Depositing a silicon oxide layer on the back of the silicon wafer obtained in the step (2);
(4) Carrying out partial laser grooving on the silicon oxide layer so as to remove the silicon oxide layer at the grooving part and cauterize the lower silicon layer to form an inverted pyramid structure;
(5) Carrying out back corrosion treatment on the silicon wafer obtained in the step (4), and removing the silicon oxide layer in the non-laser area;
(6) Depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the silicon wafer obtained in the step (5),
the metal grid line on the back of the silicon wafer is arranged at a position corresponding to the slotting pattern.
The method for preparing the N-type TopCon battery plate provided by the embodiment of the invention has at least the following advantages: 1. when the back surface of the silicon wafer is polished, a square morphology with larger size can be formed on the back surface of the silicon wafer, for example, the square size can reach about 20 mu m, and compared with the square size formed by the existing back surface polishing, the square morphology with larger size can be formed, so that a passivation film is deposited on a larger square and flat silicon substrate more densely, and the passivation effect is better; 2. when the square morphology with larger size is formed on the back of the silicon wafer, the etching amount of back polishing control is larger than that of the conventional process, so that the side surface and the back winding and expanding layer of the battery can be completely removed, the better parallel resistance of the battery is ensured, and electric leakage is prevented; 3. in a metallized area (namely an area contacted with a back electrode) on the back of the silicon wafer, the silicon substrate is contacted with metal slurry through an inverted pyramid structure, so that the mutual contact area is larger, the contact resistance is smaller, the series resistance is correspondingly smaller, and the conductive effect can be further improved; 4. the battery prepared by the method can be compatible with the performance of back passivation, good contact between the back metal paste and the silicon substrate, has lower resistance, and can improve the open-circuit voltage, the filling factor and the conversion efficiency of the battery, for example, the series resistance can be reduced by 1.5mΩ or more, the open-circuit voltage can be improved by 5mV or more, the filling factor can be improved by 0.4% or more, and the conversion efficiency of the battery can be improved by 0.3% or more.
In addition, the method for preparing the N-type TopCon battery sheet according to the above embodiment of the present invention may further have the following additional technical features:
in some embodiments of the present invention, in the step (2), based on 182 silicon wafers having a thickness of 170 μm±10 μm, a side length of 182mm±0.25mm, and a chamfer diameter of 247mm±0.25mm, the etching amount of the polishing treatment is 0.58g±0.05g, wherein the polishing treatment is performed at 65°c±3 ℃ for 400s±20s, the polishing solution used includes a base including KOH and/or NaOH and the volume concentration of the base is 4v% ±0.2v%, and the polishing additive.
In some embodiments of the invention, in step (2), the square features have square dimensions of 20 μm±2 μm.
In some embodiments of the present invention, the back side reflectance of the silicon wafer obtained in step (2) is 42% ± 1%.
In some embodiments of the invention, in step (3), the silicon oxide layer has a thickness of 90 to 150nm.
In some embodiments of the present invention, in step (4), the laser grooving power is 20w±5W, and the frequency is 40000hz±2000Hz.
In some embodiments of the present invention, in step (5), the etching treatment is performed at a temperature of 80 ℃ ± 3 ℃ for a time of 120s ± 10s, wherein the etching treatment uses an etching solution comprising a base, the base comprising KOH and/or NaOH, and the base having a volume concentration of 1v% ± 0.2v%.
In some embodiments of the invention, the method of making an N-type TopCon battery sheet further comprises: (7) Taking one side of the silicon wafer with boron diffusion as the front surface, injecting phosphorus into the polysilicon layer at the back surface of the silicon wafer, and removing the polysilicon layer around plating at the front surface of the silicon wafer; (8) Sequentially depositing an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer to form a front passivation layer; (9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) And printing electrode slurry on the front and back surfaces of the silicon wafer, and sintering to obtain the battery piece.
According to a second aspect of the present invention, the present invention further provides an N-type TopCon battery sheet manufactured by the above-described method for manufacturing an N-type TopCon battery sheet. Compared with the prior art, the square shape and the size of the back of the battery piece are larger, the passivation effect is better, the contact part of the back of the battery and the back electrode is of an inverted pyramid suede structure, the contact effect with the electrode is better, the conductivity is high, the performance of back passivation and good contact between the back metal paste and the silicon substrate is compatible, the resistance is lower, and the open-circuit voltage, the filling factor and the conversion efficiency of the battery are all improved.
In some embodiments of the invention, an N-type TOPCon battery comprises an N-type monocrystalline silicon substrate, a front electrode, and a back electrode, wherein the front surface of the N-type monocrystalline silicon substrate has P + Doped layer, the front electrode and the P + Doped layer is in direct contact with the P + The area of the doped layer, which is not contacted with the front electrode, is covered with a front passivation layer; the back surface of the N-type monocrystalline silicon substrate is provided with N + A doped layer, the back electrode and the N + Doped layer is in direct contact with the N + The doped layer and the corresponding area of the monocrystalline silicon substrate contacted with the back electrode have a suede pyramid structure, and the N is + The area of the doped layer, which is not contacted with the back electrode, is in a square shape, and the square size in the square shape is 20 mu m plus or minus 2 mu m.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a flow chart of a method of making an N-type TopCon cell according to one embodiment of the present invention;
fig. 2 is a schematic structural view of an N-type TopCon battery sheet obtained by using a method of manufacturing an N-type TopCon battery sheet according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In one aspect of the invention, a method of making an N-type TopCon battery sheet is provided. Referring to fig. 1, the method according to an embodiment of the present invention includes:
(1) Providing an N-type silicon wafer with boron diffusion on one side
According to the embodiment of the invention, the N-type silicon wafer with the single side containing boron diffusion can be obtained by performing double-sided texturing and boron diffusion treatment on an N-type bare silicon wafer and removing the BSG layer on the back side. The surface of the silicon substrate can be provided with a pyramid suede structure by double-sided flocking of the N-type bare silicon wafer, the surface of the silicon substrate is provided with a boron diffusion treatment, the surface of the silicon substrate can be provided with a BSG layer, and before the back polishing treatment, only the BSG layer on the back of the silicon substrate can be removed, and the BSG layer on the front of the silicon substrate can be reserved. The process conditions used in the double-sided texturing and boron diffusion treatment of the N-type bare silicon wafer and the removal of the BSG layer on the back side of the silicon wafer are not particularly limited, and may be selected by those skilled in the art according to actual needs.
According to a specific embodiment of the invention, an N-type bare silicon wafer can be put into a groove type texturing cleaning machine to be subjected to alkali texturing treatment, wherein the texturing solution can comprise alkali and a texturing additive, the types of the alkali and the texturing additive in the texturing solution are not particularly limited, a person skilled in the art can select the alkali and the texturing additive according to actual needs, for example, the alkali can be KOH and/or NaOH, the concentration of the alkali can be about 1wt%, the texturing additive can be a conventional texturing additive in the art, the temperature of the texturing solution can be 80 ℃ ± 3 ℃, the texturing treatment time can be 500s ± 15s, and pyramid structures can be successfully formed on the front surface and the back surface of the N-type bare silicon wafer by controlling the double-sided texturing condition, wherein the reflectivity of the surface of the silicon wafer after texturing can reach about 9%, so that the optical loss can be further reduced, and the high utilization rate of light energy of a finally manufactured battery piece can be ensured.
According to still another embodiment of the present invention, the double-sided textured silicon wafer may be placed in a boron diffusion furnace tube to perform boron diffusion treatment, wherein the boron diffusion temperature may be 950±50 ℃, and the sheet resistance of the silicon wafer obtained by the boron diffusion treatment may be up to 120 Ω/sq±20 Ω/sq, thereby being more beneficial to combining the subsequent processes to make the finally manufactured battery piece have an ideal sheet resistance.
According to another embodiment of the invention, the silicon wafer obtained by the boron diffusion treatment can be treated by adopting hydrofluoric acid so as to remove the BSG layer on the back surface of the silicon wafer, specifically, the silicon wafer obtained by the boron diffusion treatment can be placed in a chain type BSG removing cleaning machine, the BSG layer on the back surface of the silicon wafer is removed by adopting hydrofluoric acid with the concentration of 40+/-5 weight percent, and the controlled process temperature can be about 20 ℃, so that the BSG layer on the back surface of the silicon wafer can be effectively removed.
(2) Taking one side of the silicon wafer, which is away from boron diffusion, as a back surface, carrying out back surface polishing treatment on the silicon wafer, and forming a square morphology with expected size on the back surface of the silicon wafer
According to the embodiment of the invention, the inventor finds that the silicon wafer back passivation film is deposited on a larger square and flat silicon substrate more densely, and the passivation effect is better, but the size of the silicon wafer back alkali polishing square cannot be too large for the contact performance of the battery back metal, so that the size of the silicon wafer back alkali polishing square can only be controlled to be about 5 μm, in view of the fact, the invention mainly aims to break the limitation of the size of the silicon wafer back alkali polishing square on the contact performance of the battery back metal, and in order to achieve the aim, the inventor envisages that the structure of a non-metal contact area (namely the area of the silicon wafer back which is not contacted with an electrode) and the structure of a metal contact area (namely the area of the silicon wafer back which is contacted with an electrode) of the silicon wafer back are distinguished, and in view of the figure 2, the square size of the small silicon wafer back structure can be improved for the non-metal contact area of the battery back, and further the passivation effect of the back surface can be improved, and the contact effect of the silicon wafer back alkali polishing square on the metal contact area of the battery back can be further improved by laser grooving (wherein the laser grooving area is shown as 17 in figure 2) and the texture forming a texture structure in the metal contact area of the silicon wafer back surface of the back metal contact area can be further improved, and further, the contact effect of the silicon wafer back and the silicon wafer back alkali polishing performance can be further improved can be well guaranteed.
According to some embodiments of the present invention, in the square morphology formed by the back polishing process, the square size may be 20 μm±2 μm, for example, 19 μm, 19.5 μm, 20 μm, 20.5 μm or 21 μm, etc., and the inventor finds that if the square size of the back of the silicon wafer is too small, it is difficult to effectively improve the passivation effect of the back of the silicon wafer, and if the square size of the back of the silicon wafer is too large, the etching amount is large, the silicon wafer becomes thinner, and the reliability of the battery is reduced.
According to other embodiments of the present invention, the reflectivity of the back surface of the silicon wafer after the back surface polishing treatment can be up to 42% ± 1%, and the inventors found that the higher the reflectivity of the back surface of the silicon wafer, the smoother the square formed on the back surface of the silicon wafer is, and the larger the silicon wafer size can also improve the reflectivity of the back surface of the silicon wafer.
According to still other embodiments of the present invention, 182 wafers having a thickness of 170 μm.+ -. 10 μm, a side length of 182 mm.+ -. 0.25mm, and a chamfer diameter of 247 mm.+ -. 0.25mm are used as references (or a wafer planar area of 330.15cm is 170 μm.+ -. 10 μm) 2 The etching amount of the back polishing treatment can be 0.58g plus or minus 0.05g, and the etching amount of the back polishing treatment in the conventional process is about 0.16g, but the inventor finds that if the etching amount of the back polishing treatment is too small, the side and back winding expansion layers of the battery are difficult to sufficiently remove, and if the etching amount of the back polishing treatment is too large, the silicon wafer becomes thinner, the reliability of the battery is reduced, and meanwhile, the reaction time is relatively longer, the production efficiency is reduced and the cost is increased.
According to still other embodiments of the present invention, in order to enable formation of a larger-sized alkali polished square on the back surface of a silicon wafer, it is necessary to select appropriate polishing conditions, wherein the polishing liquid used may include alkali and polishing additives, the types of alkali and polishing additives in the polishing liquid are not particularly limited, and those skilled in the art may select according to actual needs, for example, the alkali may include KOH and/or NaOH, the polishing additives may be polishing additives commonly used in the art, further, the volume concentration of alkali may be 4v% ± 0.2v%, the temperature for the polishing liquid may be 65 ℃ ± 3 ℃ for 400s ± 20s, wherein the polishing treatment of the back surface of the silicon wafer may be performed in a tank washer, and the inventors have found that the silicon wafer has a thickness of 170 μm ± 10 μm and a planar area of 330.15cm by a large number of experiments 2 By controlling the polishing conditions, it is more advantageous to obtain a silicon wafer having a backside morphology of 20 μm.+ -.2 μm in size, a backside reflectance of 42%.+ -. 1%, and an etching amount of 0.58 g.+ -. 0.05g based on 182 chips of (a), thereby not onlyThe method is beneficial to enabling the nonmetal area on the back of the finally manufactured battery piece to have a good passivation effect, and can also ensure good parallel resistance of the battery and prevent electric leakage.
(3) Depositing a silicon oxide layer on the back surface of the silicon wafer obtained in the step (2)
According to the embodiment of the invention, a SiOx layer, specifically a silicon dioxide layer, can be deposited on the back of a battery in an Atmospheric Pressure Chemical Vapor Deposition (APCVD) device, wherein the thickness of the silicon oxide layer can be 90-150 nm, for example, 95nm, 100nm, 105nm, 115nm, 125nm, 135nm or 145nm, etc., and the inventor finds that if the thickness of the silicon oxide layer is too small, the protection effect on a silicon substrate is difficult to ensure, and in the subsequent texturing treatment performed after laser grooving, the damage of alkali in a texturing solution on the silicon substrate cannot be effectively blocked, and if the thickness of the silicon oxide layer is too large, not only the preparation efficiency is influenced, but also the raw material waste is caused, and meanwhile, the difficulty in the subsequent laser grooving is increased.
(4) Locally laser grooving the silicon oxide layer to remove the silicon oxide layer at the grooved part and cauterizing the lower silicon layer to form an inverted pyramid structure
According to the embodiment of the invention, a silicon oxide layer (SiOx layer) on the back of the battery can be subjected to laser grooving on an ultraviolet laser (a laser area is shown as 17 in fig. 2), the grooved pattern is consistent with a metal fine grid line pattern formed on the back of a silicon wafer later, after the surface SiOx of the pattern area is removed, laser is used for burning silicon on the lower layer simultaneously to form an inverted pyramid structure, and Mark points are finally marked on 4 corners of the battery for alignment during subsequent screen printing. The metal grid line formed on the back of the silicon wafer is arranged at the position corresponding to the slotting pattern, the silicon oxide layer on the back of the battery is slotted by laser, the silicon substrate can be exposed and form an inverted pyramid structure, the silicon substrate is contacted with metal slurry in a metallized area (namely an area contacted with a back electrode) on the back of the silicon wafer through the inverted pyramid structure, the mutual contact area is larger, the contact resistance is smaller, the series resistance is correspondingly smaller, and the conductive effect can be further improved.
According to some specific embodiments of the present invention, the power of the laser grooving may be 20w±5W, the frequency may be 40000hz±2000Hz, and the inventor finds that if the laser power is too small or the frequency is too low, it is difficult to achieve a good laser grooving effect and a burning effect on the underlying silicon, and if the laser power is too large or the frequency is too high, it is difficult to control the laser degree, which is not beneficial to forming the expected pyramid structure.
(5) Carrying out back corrosion treatment on the silicon wafer obtained in the step (4), and removing the silicon oxide layer in the non-laser area;
according to the embodiment of the invention, the main purpose of back etching treatment on the silicon wafer is to eliminate the damaged layer formed by laser burning in the previous step, and modify the inverted pyramid structure at the same time, and finally, the SiOx layer in the non-laser area can be removed by adopting hydrofluoric acid.
According to one embodiment of the invention, the silicon wafer can be put into a groove-type texturing cleaning machine for back surface corrosion treatment, wherein the corrosion liquid can comprise alkali and corrosion additives, the types of the alkali and the corrosion additives in the corrosion liquid are not particularly limited, a person skilled in the art can select according to actual needs, for example, the alkali can be KOH and/or NaOH, the volume concentration of the alkali can be 1v% +/-0.2 v%, the corrosion additives can be conventional corrosion additives in the art, the temperature of the corrosion liquid can be 80+/-3 ℃, the corrosion treatment time can be 120 s+/-10 s, and a damaged layer formed by laser burning in the previous step can be effectively eliminated by controlling the texturing conditions, and meanwhile, the inverted pyramid structure is modified.
(6) And (5) depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the silicon wafer obtained in the step (5).
According to embodiments of the present invention, a backside tunneling oxide (SiO) layer may be performed in a low pressure chemical vapor deposition furnace (LPCVD) 2 ) And deposition of a polysilicon (Poly) layer, wherein the thickness of the tunneling oxide layer and the polysilicon layer is not particularly limited, and can be selected according to practical needs by those skilled in the art, for example, the thickness of the tunneling oxide layer can be about 1.5nm, and the thickness of the polysilicon layer can be about 120 nm.
According to some embodiments of the invention, the method of preparing an N-type TopCon battery sheet may further comprise: (7) The method comprises the steps of taking one side of a silicon wafer with boron diffusion as the front side, injecting phosphorus into a polycrystalline silicon layer on the back side of the silicon wafer to form a passivation contact structure, wherein the step can be carried out in a back phosphorus diffusion furnace, and the passivation contact structure is formed by preparing an ultrathin tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back side of a battery together.
According to still further embodiments of the present invention, the method of preparing an N-type TopCon battery sheet may further comprise: the method for removing the front-side around-plating polysilicon layer of the silicon wafer comprises the steps of adopting polishing solution to carry out in a groove type cleaning machine, wherein the polishing solution can comprise KOH and polishing additive, the concentration of the KOH in the polishing solution can be 4wt% and the polishing additive can be a polishing additive which is conventional in the field, the polishing temperature can be 66 ℃ +/-3 ℃, the process time can be 200 s+/-20 s, and the front-side around-plating polysilicon layer of the silicon wafer can be effectively removed by controlling the conditions.
According to still further embodiments of the present invention, the method of preparing an N-type TopCon battery sheet may further comprise: (8) Sequentially depositing an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer to form a front passivation layer; (9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) And printing electrode slurry on the front and back surfaces of the silicon wafer, and sintering to obtain the battery piece.
Compared with the prior art, the method for preparing the N-type TopCon battery piece of the embodiment of the invention deposits the silicon oxide layer on the back of the silicon wafer after the back polishing treatment, the inverted pyramid structure can be formed on the surface of the silicon wafer by carrying out laser grooving on the silicon oxide layer and burning the silicon on the lower layer of the grooved part, and then the damaged surface caused by laser burning can be removed and the inverted pyramid structure can be modified by further texturing, so that the textured pyramid structure can be used for contacting with the back metal electrode, the contact effect of the back of the silicon wafer and the metal electrode can be improved, the conductivity can be improved, and the square size of a non-contact area can be allowed to be larger, thereby achieving better passivation effect. In summary, the preparation process has at least the following advantages: 1. when the back surface of the silicon wafer is polished, a square morphology with larger size can be formed on the back surface of the silicon wafer, for example, the square size can reach about 20 mu m, and compared with the square size formed by the existing back surface polishing, the square morphology with larger size can be formed, so that a passivation film is deposited on a larger square and flat silicon substrate more densely, and the passivation effect is better; 2. when the square morphology with larger size is formed on the back of the silicon wafer, the etching amount of back polishing control is larger than that of the conventional process, so that the side surface and the back winding and expanding layer of the battery can be completely removed, the better parallel resistance of the battery is ensured, and electric leakage is prevented; 3. in a metallized area (namely an area contacted with a back electrode) on the back of the silicon wafer, the silicon substrate is contacted with metal slurry through an inverted pyramid structure, so that the mutual contact area is larger, the contact resistance is smaller, the series resistance is correspondingly smaller, and the conductive effect can be further improved; 4. the battery prepared by the method can be compatible with the performance of back passivation, good contact between the back metal paste and the silicon substrate, has lower resistance, and can improve the open-circuit voltage, the filling factor and the conversion efficiency of the battery, for example, the series resistance can be reduced by 1.5mΩ or more, the open-circuit voltage can be improved by 5mV or more, the filling factor can be improved by 0.4% or more, and the conversion efficiency of the battery can be improved by 0.3% or more.
According to the second aspect of the inventionIn one aspect, the invention also provides an N-type TOPCon battery piece prepared by the method for preparing the N-type TOPCon battery piece. Specifically, according to some specific examples of the present invention, it is understood with reference to fig. 2 that an N-type TOPCon battery can include an N-type monocrystalline silicon substrate 10, a front electrode 11 (e.g., ag/Al electrode), and a back electrode 12 (e.g., ag electrode), wherein the front surface of the N-type monocrystalline silicon substrate 10 has P + Doped layer 13, front electrode 11 and P + Doped layer 13 is in direct contact with P + The doped layer 13 has a textured pyramid structure in the region contacting the front electrode 11, P + The area of the doped layer 13, which is not contacted with the front electrode 11, is covered with a front passivation layer 14, wherein the front passivation layer 14 is sequentially formed with an aluminum oxide layer and a silicon nitride layer in a direction away from the front surface of the monocrystalline silicon substrate 10, and the front electrode 11 can be an Al electrode or an Ag electrode; n is arranged on the back surface of the N-type monocrystalline silicon substrate 10 + Doped layer 15, back electrode 12 and N + Doped layer 15 is in direct contact with N + The doped layer 15 and the corresponding region of the monocrystalline silicon substrate 10 in contact with the rear electrode 12 have a textured pyramid structure, N + The area of the doped layer 15 not in contact with the back electrode 12 is in a square shape, wherein the square shape has a square size of 20 μm + -2 μm, and the square shape is covered with a back passivation layer 16, wherein the back passivation layer 16 is sequentially formed with a polysilicon doped layer and a silicon nitride layer in a direction away from the back surface of the single crystal silicon substrate 10. Compared with the prior art, the N-type TopCon battery piece has larger shape and size of the square at the back, better passivation effect, better electrode contact effect with the back, high conductivity, compatibility of back passivation, good contact performance between the back metal paste and the silicon substrate, lower resistance, and improvement of open-circuit voltage, filling factor and conversion efficiency of the battery. It should be noted that the features and effects described in the above method for preparing an N-type TopCon battery cell are also applicable to the N-type TopCon battery cell, and are not described herein again. In addition, "P" as used in the present invention + Doped layer and said N + In the doped layer, "P" refers to P-type (positive electrode), and "N" refers to N-type (negative electrode), and "+" refers toHeavy doping, high doping concentration relative to intrinsic silicon wafer, "P + The doped layer represents a P-type heavily doped layer, and N + The doped layer "represents an N-type heavily doped layer.
The following examples are illustrative only and are not to be construed as limiting the invention. The examples are not to be construed as limiting the specific techniques or conditions described in the literature in this field or as per the specifications of the product. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
Example 1
N-type TopCon cell plates were prepared:
1. firstly, putting an N-type bare silicon wafer into a groove type texturing cleaning machine for alkali texturing, wherein the solution is KOH+texturing additive solution with concentration of 1+/-0.2 v%, the solution temperature is 80+/-3 ℃, the process time is 500 s+/-15 s, the etching amount is 0.58+/-0.05 g, and the reflectivity is 9+/-0.5%;
2. performing a boron diffusion process on the battery piece subjected to the second step of texturing in a boron diffusion furnace tube, wherein the sheet resistance is 120+/-20 omega/sq, and the process temperature is 950+/-50 ℃;
3. thirdly, removing the back BSG layer in a chain type BSG removing cleaning machine, wherein the solution is hydrofluoric acid with the concentration of 40+/-5 wt% and the process temperature is 20+/-3 ℃;
4. fourthly, performing back alkaline polishing in a groove type cleaning machine, wherein the solution is KOH+polishing additive with the volume concentration of 4+/-0.2%, the solution temperature is 65+/-3 ℃, the process time is 400+/-20 s, the back appearance is square with the size of 20+/-2 mu m, and the back reflectivity is 42+/-1%;
5. fifthly, depositing a SiOx layer with the film thickness of 100+/-10 nm on the back surface of the battery in normal pressure chemical vapor deposition equipment (APCVD);
6. step six, laser grooving is carried out on the SiOx layer on the back of the battery on an ultraviolet laser, the laser power is 20W, the frequency is 40000Hz, the grooved pattern is consistent with the pattern of the metal fine grid line on the back, after the surface SiOx of the pattern area is removed, laser cauterizes the silicon on the lower layer to form an inverted pyramid structure, and Mark points are finally marked on 4 corners of the battery for alignment during subsequent screen printing;
7. the seventh step is to carry out alkali corrosion in a groove type cleaning machine, the solution is KOH+ corrosion additive with the concentration of 1+/-0.2 v% (volume ratio), the solution temperature is 80+/-3 ℃, the process time is 120+/-10 s, the main purpose is to eliminate the damaged layer formed by laser burning in the last step, and simultaneously modify the inverted pyramid structure, and finally remove the SiOx film in the un-laser area in the following hydrofluoric acid groove;
8. eighth step, back tunneling oxide layer (SiO) is carried out in a low pressure chemical vapor deposition furnace (LPCVD) 2 ) And depositing a polysilicon (Poly) layer, wherein the thickness of the tunneling oxide layer is 1.5+/-0.2 nm, and the thickness of the Poly layer is 120+/-20 nm;
9. a ninth step of injecting phosphorus into the back Poly layer by a back phosphorus diffusion furnace to form a passivation contact structure;
10. the tenth step is to remove the front surface winding plating Poly layer in a groove type cleaning machine, the solution is KOH+polishing additive with the concentration of 4+/-0.2 v% (volume ratio), the temperature is 66+/-3 ℃, and the process time is 200+/-20 s;
11. eleventh step, coating a passivation film on the front surface AlOx+SiNx and the back surface SiNx;
12. and finally, carrying out screen printing and sintering test sorting on the battery pieces.
Comparative example 1
N-type TopCon cell plates were prepared:
1. firstly, putting an N-type bare silicon wafer into a groove type texturing cleaning machine for alkali texturing, wherein the solution is KOH+texturing additive solution with the concentration of 1+/-0.2% (volume ratio), the temperature of the solution is 80+/-3 ℃, the process time is 500+/-15 s, the etching amount is 0.58+/-0.05 g, and the reflectivity is 9+/-0.5%;
2. performing a boron diffusion process on the battery piece subjected to the second step of texturing in a boron diffusion furnace tube, wherein the sheet resistance is 120+/-20 omega/sq, and the process temperature is 950+/-50 ℃;
3. thirdly, removing the back BSG layer in a chain type BSG removing cleaning machine, wherein the solution is hydrofluoric acid with the concentration of 40+/-5 wt% and the process temperature is 20+/-3 ℃;
4. fourthly, performing back alkaline polishing in a groove type cleaning machine, wherein the solution is KOH+polishing additive with concentration of 4+/-0.2 v%, the solution temperature is 65+/-3 ℃, the process time is 160+/-10 s, the back surface appearance is square with size of 5+/-0.5 mu m, and the back surface reflectivity is 40+/-1%;
5. fifth step, back tunneling oxide layer (SiO) is performed in low pressure chemical vapor deposition furnace (LPCVD) 2 ) And depositing a polysilicon (Poly) layer, wherein the thickness of the tunneling oxide layer is 1.5+/-0.2 nm, and the thickness of the Poly layer is 120+/-20 nm;
6. a sixth step of injecting phosphorus into the back Poly layer by a back phosphorus diffusion furnace to form a passivation contact structure;
7. the seventh step, the front side is wound and plated with a Poly layer in a groove type cleaning machine, the solution is KOH+polishing additive with the concentration of 4+/-0.2% (volume ratio), the temperature is 66+/-3 ℃, and the process time is 200+/-20 s;
8. eighth, coating a passivation film on the front surface AlOx+SiNx and the back surface SiNx;
9. and finally, carrying out screen printing and sintering test sorting on the battery pieces.
Comparative example 2
The difference from example 1 is that:
4. fourthly, performing back alkaline polishing in a groove type cleaning machine, wherein the solution is KOH+polishing additive with the concentration of 4+/-0.2% (volume ratio), the temperature of the solution is 65+/-3 ℃, the process time is 800+/-20 s, the shape of the back is square with the size of 40+/-2 mu m, and the reflectivity of the back is 43+/-1%;
example 2
The difference from example 1 is that steps 4 to 7. Specifically:
4. fourthly, performing back alkaline polishing in a groove type cleaning machine, wherein the solution is KOH+polishing additive with the concentration of 4+/-0.2% (volume ratio) wt%, the solution temperature is 65+/-3 ℃, the process time is 600+/-20 s, the back appearance is square with the size of 30+/-2 mu m, and the back reflectivity is 42.5+/-1%;
5. fifthly, depositing a SiOx layer with the film thickness of 100+/-10 nm on the back surface of the battery in normal pressure chemical vapor deposition equipment (APCVD);
6. step six, laser grooving is carried out on the SiOx layer on the back of the battery on an ultraviolet laser, the laser power is 20W, the frequency is 40000Hz, the grooved pattern is consistent with the pattern of the metal fine grid line on the back, after the surface SiOx of the pattern area is removed, laser cauterizes the silicon on the lower layer to form an inverted pyramid structure, and Mark points are finally marked on 4 corners of the battery for alignment during subsequent screen printing;
7. and seventhly, performing alkali corrosion in a groove type cleaning machine, wherein the solution is KOH+ corrosion additive with the concentration of 1+/-0.2% (volume ratio), the solution temperature is 80+/-3 ℃, the process time is 120+/-10 s, the main purpose is to eliminate a damaged layer formed by laser burning in the last step, and simultaneously modifying an inverted pyramid structure, and finally removing the SiOx film in a non-laser area in a following hydrofluoric acid groove.
Evaluation and results
The battery sheets prepared in examples 1 to 2 and comparative examples 1 to 2 were subjected to electric performance tests, and the test results are shown in table 1.
Table 1 comparison of the electrical properties of the battery sheets of examples 1 to 2 and comparative examples 1 to 2 (average value of 100 battery sheets)
Number of battery pieces Eff(％) Voc(mV) Jsc(mA/cm 2) FF(％)
Example 1 100 24.54 723 41.33 82.12
Comparative example 1 100 24.22 716 41.31 81.90
Comparative example 2 100 24.52 722 41.35 82.13
Example 2 100 24.47 721 41.34 82.10
Wherein Total is the number of battery pieces; eff is the battery conversion efficiency; voc is the open circuit voltage; jsc is the short circuit current density; FF is the fill factor.
As can be seen from Table 1, compared with the square block with the back surface morphology of 5+ -0.5 μm in comparative example 1 and the process without laser grooving, the preparation process of the present application can improve the open circuit voltage, short circuit current, filling factor and battery conversion efficiency of the battery. In addition, it should be further noted that, although the alkali polishing time adopted in the embodiment 2 and the comparative embodiment 2 is longer, the obtained back surface morphology is larger in square size, and the average performance parameter of the battery piece is closer to that of the embodiment 1, the battery pieces adopted in the test are all selected battery pieces which can be prepared and qualified, and in the actual operation process, compared with the embodiment 1, the battery pieces in the embodiment 2 and the comparative embodiment 2 are lower in preparation efficiency and lower in yield, and in the preparation process of the battery pieces, the condition that the front mask to be protected is partially etched also causes the performance of individual battery pieces to be reduced, so that the average performance of the battery pieces is affected; in addition, the silicon wafer in the battery plate manufactured in example 2 and comparative example 2 is relatively thinner, the limit load of the battery plate capable of loading is smaller, and the risk of the battery plate is larger.
In the present invention, unless explicitly specified and limited otherwise, terms such as "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. The preparation method of the N-type TopCon battery piece is characterized by comprising the following steps of:
(1) Providing an N-type silicon wafer with one side containing boron diffusion;
(2) Taking one side of the silicon wafer, which is away from boron diffusion, as a back surface, and performing back surface polishing treatment on the silicon wafer so as to form a square morphology with expected size on the back surface of the silicon wafer;
(3) Depositing a silicon oxide layer on the back of the silicon wafer obtained in the step (2);
(4) Carrying out partial laser grooving on the silicon oxide layer so as to remove the silicon oxide layer at the grooving part and cauterize the lower silicon layer to form an inverted pyramid structure;
(5) Etching the silicon wafer obtained in the step (4), and removing the silicon oxide layer in the area without laser;
(6) Depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the silicon wafer obtained in the step (5),
the metal grid line on the back of the silicon wafer is arranged at a position corresponding to the slotting pattern.
2. The method according to claim 1, wherein in the step (2), the etching amount of the polishing treatment is 0.58 g.+ -. 0.05g based on 182 wafers having a thickness of 170 μm.+ -. 10 μm, a side length of 182 mm.+ -. 0.25mm and a chamfer diameter of 247 mm.+ -. 0.25mm,
wherein the polishing treatment temperature is 65 ℃ +/-3 ℃ and the polishing time is 400 s+/-20 s, the adopted polishing solution comprises alkali and polishing additives, the alkali comprises KOH and/or NaOH, and the volume concentration of the alkali is 4v% +/-0.2 v%.
3. The method of claim 1, wherein in step (2), the square shape has a square size of 20 μm±2 μm.
4. The preparation method of claim 1, wherein the reflectivity of the back surface of the silicon wafer obtained in the step (2) is 42% ± 1%.
5. The method according to claim 1, wherein in the step (3), the thickness of the silicon oxide layer is 90 to 150nm.
6. The method according to claim 1, wherein in the step (4), the laser grooving power is 20w±5W, and the frequency is 40000hz±2000Hz.
7. The method according to claim 1, wherein in the step (5), the etching treatment is performed at a temperature of 80.+ -. 3 ℃ for a time of 120 s.+ -. 10s,
wherein the etching solution adopted in the etching treatment comprises alkali, the alkali comprises KOH and/or NaOH, and the volume concentration of the alkali is 1v% +/-0.2 v%.
8. The production method according to any one of claims 1 to 7, characterized by further comprising:
(7) Taking one side of the silicon wafer with boron diffusion as the front surface, injecting phosphorus into the polysilicon layer at the back surface of the silicon wafer, and removing the polysilicon layer around plating at the front surface of the silicon wafer;
(8) Sequentially depositing an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer to form a front passivation layer;
(9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer;
(10) And printing electrode slurry on the front and back surfaces of the silicon wafer, and sintering to obtain the battery piece.
9. An N-type TOPCon battery cell prepared by the method of any one of claims 1-8.
10. The N-type TOPCon battery cell of claim 9 comprising an N-type monocrystalline silicon substrate, a front electrode, and a back electrode, wherein,
the front surface of the N-type monocrystalline silicon substrate is provided with P + Doped layer, the front electrode and the P + Doped layer is in direct contact with the P + The area of the doped layer, which is not contacted with the front electrode, is covered with a front passivation layer;
the back surface of the N-type monocrystalline silicon substrate is provided with N + A doped layer, the back electrode and the N + Doped layer is in direct contact with the N + The doped layer and the corresponding area of the monocrystalline silicon substrate contacted with the back electrode have a suede pyramid structure, and the N is + The area of the doped layer, which is not contacted with the back electrode, is in a square shape, and the square size in the square shape is 20 mu m plus or minus 2 mu m.
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