CN114256381A - N-type TopCon battery piece and preparation method thereof - Google Patents
N-type TopCon battery piece and preparation method thereof Download PDFInfo
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- CN114256381A CN114256381A CN202111314179.4A CN202111314179A CN114256381A CN 114256381 A CN114256381 A CN 114256381A CN 202111314179 A CN202111314179 A CN 202111314179A CN 114256381 A CN114256381 A CN 114256381A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
- H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an N-type TopCon battery piece and a preparation method thereof. The preparation method comprises the following steps: providing an N-type silicon wafer with a single side containing boron diffusion; taking the side of the silicon wafer departing from the boron diffusion as the back, and carrying out back polishing treatment on the silicon wafer to form a square shape with an expected size on the back of the silicon wafer; depositing a silicon-oxygen compound layer on the back of the silicon wafer; local laser grooving is carried out on the silicon-oxygen compound layer so as to remove the silicon-oxygen compound layer at the grooving position and burn the lower layer silicon to form an inverted pyramid structure; carrying out back corrosion treatment on the obtained silicon wafer, and removing the silicon-oxygen compound layer in the non-laser area; and depositing a tunneling oxide layer and a polysilicon layer on the back of the obtained silicon wafer, wherein the metal grid line on the back of the silicon wafer is arranged at the position corresponding to the slotted graph. The method can improve the passivation effect of the back of the silicon chip, improve the contact performance of the metal electrode on the back of the silicon chip and the silicon substrate, reduce the resistance of the battery, and improve the open-circuit voltage, the filling factor and the conversion efficiency of the battery.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to an N-type TopCon cell and a preparation method thereof.
Background
At present, a mainstream battery product in a photovoltaic market is a P-type Perc battery, a next generation upgraded product is an N-type TopCon battery, and a conventional process route is that a back polishing process is required after boron diffusion of the TopCon battery, so that boron diffusion winding plating on the side edge and the back edge of a silicon wafer is removed, a small square structure on the back is formed, and the back passivation effect is enhanced. In order to be compatible with the contact performance of the metal on the back of the battery, the size of the alkali polishing block on the back of the battery can only be controlled to be 5 mu m, and compared with a back surface appearance structure with a larger block size (more than 20 mu m), the passivation effect is relatively poor, so that the improvement of the battery performance is limited.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide an N-type TopCon cell and a method for manufacturing the same, wherein the method can improve the passivation effect of the back side of the silicon wafer, improve the contact performance between the metal electrode on the back side of the silicon wafer and the silicon substrate, reduce the resistance of the cell, and improve the open-circuit voltage, the fill factor and the cell conversion efficiency of the cell.
In one aspect of the invention, the invention provides a method for preparing an N-type TopCon cell sheet. According to an embodiment of the invention, the method comprises:
(1) providing an N-type silicon wafer with a single side containing boron diffusion;
(2) taking the side of the silicon wafer, which is far away from the boron diffusion, as a back surface, and carrying out back polishing treatment on the silicon wafer so as to form a square shape with an expected size on the back surface of the silicon wafer;
(3) depositing a silicon-oxygen compound layer on the back surface of the silicon wafer obtained in the step (2);
(4) local laser grooving is carried out on the silicon oxide layer so as to remove the silicon oxide layer at the grooving part and burn the lower layer silicon to form an inverted pyramid structure;
(5) carrying out back corrosion treatment on the silicon wafer obtained in the step (4), and removing the silicon-oxygen compound layer in the non-laser area;
(6) depositing a tunneling oxide layer and a polysilicon layer on the back surface of the silicon wafer obtained in the step (5),
and the metal grid line on the back of the silicon wafer is arranged at a position corresponding to the slotted graph.
The method for preparing the N-type TopCon cell piece in the embodiment of the invention at least has the following advantages: 1. when the back surface of the silicon wafer is polished, a square shape with larger size can be formed on the back surface of the silicon wafer, for example, the size of the square can reach about 20 microns, and compared with the size of the square with the size of about 5 microns formed by the conventional back surface polishing, the square shape with larger size can be formed in the invention, so that the deposition of a passivation film on a larger square and a flat silicon substrate is more compact, and the passivation effect is better; 2. when a square shape with larger size is formed on the back surface of the silicon chip, the etching amount controlled by back surface polishing is larger than that of the conventional process, so that the side surface and the back surface of the battery are completely removed, a better parallel resistance of the battery is ensured, and electric leakage is prevented; 3. in a metalized area (namely an area contacted with a back electrode) on the back of the silicon chip, the silicon substrate is contacted with the metal slurry through an inverted pyramid structure, and the mutual contact area is larger, so that the contact resistance is smaller, the series resistance is correspondingly smaller, and the conductive effect can be further improved; 4. the battery prepared by the method can be compatible with the back passivation and good contact performance of the back metal slurry and the silicon substrate, the resistance is lower, the open-circuit voltage, the filling factor and the conversion efficiency of the battery can be improved, for example, the series resistance can be reduced by 1.5m omega or even more, the open-circuit voltage can be improved by 5mV or even more, the filling factor can be improved by 0.4 percent or even more, and the conversion efficiency of the battery can be improved by 0.3 percent or even more.
In addition, the method for preparing the TopCon cell sheet of the N type according to the above embodiment of the present invention may also have the following additional technical features:
in some embodiments of the invention, in the step (2), based on 182 silicon wafers with the thickness of 170 μm +/-10 μm, the side length of 182mm +/-0.25 mm and the chamfer diameter of 247mm +/-0.25 mm, the etching amount of the polishing treatment is 0.58g +/-0.05 g, wherein the temperature of the polishing treatment is 65 +/-3 ℃ and the time is 400 +/-20 s, the polishing solution adopted comprises alkali and polishing additives, the alkali comprises KOH and/or NaOH, and the volume concentration of the alkali is 4 v% +/-0.2 v%.
In some embodiments of the present invention, in step (2), the square size in the square morphology is 20 μm ± 2 μm.
In some embodiments of the present invention, the silicon wafer backside reflectivity obtained in step (2) is 42% ± 1%.
In some embodiments of the present invention, in the step (3), the thickness of the silicon oxide layer is 90 to 150 nm.
In some embodiments of the invention, in the step (4), the power of the laser grooving is 20W +/-5W, and the frequency is 40000Hz +/-2000 Hz.
In some embodiments of the invention, in the step (5), the temperature of the etching treatment is 80 ℃ ± 3 ℃ and the time is 120s ± 10s, wherein the etching treatment uses an etching solution containing a base, the base contains KOH and/or NaOH, and the volume concentration of the base is 1 v% ± 0.2 v%.
In some embodiments of the present invention, the method for preparing a TopCon type N cell sheet further comprises: (7) taking one side of the silicon wafer with boron diffusion as a front side, injecting phosphorus into the polycrystalline silicon layer on the back side of the silicon wafer, and removing the winding-plated polycrystalline silicon layer on the front side of the silicon wafer; (8) depositing an aluminum oxide layer and a silicon nitride layer on the front surface of the silicon wafer in sequence to form a front passivation layer; (9) depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) and printing electrode slurry on the front side and the back side of the silicon wafer and sintering to obtain the cell.
According to the second aspect of the invention, the invention also provides an N-type TOPCon battery piece prepared by the method for preparing the N-type TopCon battery piece. Compared with the prior art, the battery piece has the advantages that the shape and the size of the square block on the back side are larger, the passivation effect is better, the contact part of the back side of the battery and the back side electrode is of an inverted pyramid suede structure, the contact effect with the electrode is better, the conductivity is high, the good contact performance of the back side passivation, the back side metal slurry and the silicon substrate is compatible, the resistance is lower, and the open-circuit voltage, the filling factor and the conversion efficiency of the battery are improved.
In some embodiments of the invention, an N-type TOPCon cell includes an N-type single crystal silicon substrate, a front side electrode and a back side electrode, wherein the front side of the N-type single crystal silicon substrate has a P-type surface+Doped layer, the front electrode and the P+The doped layers are in direct contact with each other, P+The region of the doped layer, which is not in contact with the front electrode, is covered with a front passivation layer;the back of the N-type monocrystalline silicon substrate is provided with N+A doped layer, the back electrode and the N+The doped layers are in direct contact, N+The doped layer and the corresponding monocrystalline silicon substrate and the contact region of the back electrode have a suede pyramid structure, and the N+The region of the doping layer, which is not in contact with the back electrode, is in a square shape, and the size of a square block in the square shape is 20 microns +/-2 microns.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a method for preparing an N-type TopCon cell sheet according to one embodiment of the present invention;
fig. 2 is a schematic structural diagram of an N-type TopCon cell sheet obtained by a method for preparing an N-type TopCon cell sheet according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In one aspect of the invention, the invention provides a method for preparing an N-type TopCon cell sheet. According to an embodiment of the invention, as shown with reference to fig. 1, the method comprises:
(1) providing an N-type silicon wafer with a single side containing boron diffusion
According to the embodiment of the invention, the N-type silicon wafer with one side containing boron diffusion can be obtained by performing double-side texturing and boron diffusion treatment on an N-type bare silicon wafer and removing the BSG layer on the back side. The method comprises the steps of carrying out double-sided texturing on an N-type bare silicon wafer to form a pyramid textured structure on the surface of a silicon substrate, carrying out boron diffusion treatment on the textured silicon wafer to form a BSG layer on the surface of the silicon wafer, removing the BSG layer on the back of the silicon wafer before carrying out back polishing treatment, and keeping the BSG layer on the front of the silicon wafer. It should be noted that the process conditions adopted for performing double-sided texturing and boron diffusion treatment on the N-type bare silicon wafer and removing the BSG layer on the back surface of the silicon wafer are not particularly limited, and those skilled in the art can select the process conditions according to actual needs.
According to one embodiment of the invention, the N-type bare silicon wafer can be put into a groove type texturing cleaning machine for alkali texturing treatment, wherein, the texture-making solution can comprise alkali and texture-making additives, the types of the alkali and the texture-making additives in the texture-making solution are not particularly limited, and the texture-making solution can be selected by the technicians in the field according to the actual needs, for example, the alkali can be KOH and/or NaOH, the concentration of the alkali can be about 1 wt%, the texturing additive can be conventional texturing additive in the field, the temperature of the texturing solution can be 80 ℃ plus or minus 3 ℃, the time of the texturing treatment can be 500s plus or minus 15s, by controlling the double-sided texturing condition, pyramid structures can be successfully formed on the front side and the back side of the N-type bare silicon wafer, the reflectivity of the surface of the textured silicon wafer can reach about 9%, so that the optical loss can be further reduced, and the high utilization rate of the finally prepared battery piece to light energy is ensured.
According to another embodiment of the invention, the silicon wafer after double-sided texturing can be placed in a boron diffusion furnace tube for boron diffusion treatment, wherein the boron diffusion temperature can be 950 ℃ +/-50 ℃, and the sheet resistance of the silicon wafer obtained through boron diffusion treatment can reach 120 Ω/sq +/-20 Ω/sq, so that the finally prepared battery piece has ideal sheet resistance value by combining with subsequent processes.
According to another embodiment of the present invention, the silicon wafer obtained by boron diffusion treatment may be treated with hydrofluoric acid to remove the BSG layer on the back side of the silicon wafer, and specifically, the silicon wafer obtained by boron diffusion treatment may be placed in a chain BSG removal cleaning machine, and the hydrofluoric acid with a concentration of 40 ± 5 wt% may be used to remove the BSG layer on the back side of the silicon wafer, and the process temperature may be controlled to be about 20 ℃, thereby ensuring that the BSG layer on the back side of the silicon wafer can be effectively removed.
(2) Taking the side of the silicon wafer departing from the boron diffusion as the back, carrying out back polishing treatment on the silicon wafer, and forming a square shape with an expected size on the back of the silicon wafer
According to the embodiment of the invention, the inventor finds that the passivation film on the back surface of the silicon wafer is deposited more densely on a larger square and flat silicon substrate, the passivation effect is better, but in order to be compatible with the contact performance of the metal on the back surface of the battery, the size of the alkali polished square on the back surface of the silicon wafer cannot be too large, and can be controlled to be only about 5 μm at present, so that the main purpose of the invention is to break through the limitation of the size of the alkali polished square on the back surface of the silicon wafer on the contact performance of the metal on the back surface of the battery, and in order to achieve the purpose, the inventor imagines that the non-metal contact area (namely the area of the back surface of the silicon wafer, which is not in contact with the electrode) on the back surface of the battery can be distinguished from the structure of the metal contact area (namely the area of the back surface of the silicon wafer, which is understood by referring to fig. 2, the square size of the small square structure on the back surface of the silicon wafer can be improved, and then improve the back passivation effect, and to the metal contact area on the back of the battery, can form the suede pyramid structure in the metal contact area on the back of the silicon chip through laser grooving (wherein the laser grooving area is shown as 17 in fig. 2) and texturing process, and then improve the contact effect of the back of the silicon chip and the electrode, improve the conductivity, can solve the restriction of the contact performance of the metal on the back of the battery of the size of the alkali polished block on the back of the silicon chip effectively, thus can improve the passivation effect on the back of the silicon chip, can also guarantee the good contact of the back of the silicon chip and the electrode, improve the conductivity.
According to some embodiments of the present invention, in the square morphology formed by the back polishing process, the square size may be 20 μm ± 2 μm, for example, 19 μm, 19.5 μm, 20 μm, 20.5 μm, or 21 μm, and the inventors found that if the square size of the back of the silicon wafer is too small, it is difficult to effectively improve the passivation effect of the back of the silicon wafer, and if the square size of the back of the silicon wafer is too large, the etching amount is large, the silicon wafer may become thinner, and the battery reliability is reduced.
According to some specific embodiments of the invention, after the back surface is polished, the reflectivity of the back surface of the silicon wafer reaches 42% ± 1%, and the inventor finds that the higher the reflectivity of the back surface of the silicon wafer is, the smoother the square formed on the back surface of the silicon wafer is, and in addition, the larger the size of the silicon wafer can also improve the reflectivity of the back surface of the silicon wafer.
According to still other embodiments of the present invention, 182 silicon wafers with a thickness of 170 μm + -10 μm, a side length of 182mm + -0.25 mm and a chamfer diameter of 247mm + -0.25 mm are used as a reference (or 170 μm + -10 μm in thickness and 330.15cm in planar area of the silicon wafers)2182 chips of (1) are used as a reference), the etching amount of the back polishing treatment can be 0.58g +/-0.05 g, and the etching amount of the back polishing treatment in the conventional process is about 0.16g, but the inventor finds that if the etching amount of the back polishing treatment is too small, the side and back diffusion layers of the battery are difficult to be sufficiently removed, and if the etching amount of the back polishing treatment is too large, the silicon wafer becomes thinner, the reliability of the battery is reduced, and meanwhile, the reaction time is relatively long, the production efficiency is reduced and the cost is increased.
According to still other embodiments of the present invention, in order to form the alkali polishing block with a larger size on the back surface of the silicon wafer, it is necessary to select suitable polishing conditions, wherein the polishing solution used may include alkali and polishing additives, the types of the alkali and polishing additives in the polishing solution are not particularly limited, and those skilled in the art can select the polishing conditions according to actual needs, for example, the alkali may include KOH and/or NaOH, and the polishing additives may be those commonly used in the artThe polishing additive, further, the volume concentration of the alkali can be 4 v% + -0.2 v%, the temperature of the polishing treatment can be 65 ℃ + -3 ℃ and the time can be 400s + -20 s, wherein the polishing treatment of the back surface of the silicon wafer can be carried out in a tank type cleaning machine, and the inventor has proved through a large number of experiments that the thickness is 170 μm + -10 μm and the plane area of the silicon wafer is 330.15cm2The 182 chips are taken as a reference, and by controlling the polishing conditions, the silicon wafer with the back surface appearance of 20 microns +/-2 microns, the back surface reflectivity of 42% +/-1% and the etching amount of 0.58g +/-0.05 g is more favorably obtained, so that the finally prepared non-metal area on the back surface of the battery piece has a better passivation effect, better parallel resistance of the battery can be ensured, and electric leakage is prevented.
(3) Depositing a silicon-oxygen compound layer on the back of the silicon wafer obtained in the step (2)
According to an embodiment of the invention, a SiOx layer, in particular a silicon dioxide layer, the thickness of the silicon oxide layer may be 90 to 150nm, for example, 95nm, 100nm, 105nm, 115nm, 125nm, 135nm or 145nm, and the inventors have found that if the thickness of the silicon oxide layer is too small, it is difficult to secure the protective effect on the silicon substrate, in the subsequent texturing treatment after laser grooving, the damage of alkali in the texturing solution to the silicon substrate can not be effectively prevented, if the thickness of the silicon oxide layer is too large, the preparation efficiency is influenced, raw materials are wasted, and the difficulty in subsequent laser grooving is increased.
(4) Local laser grooving is carried out on the silicon oxide layer so as to remove the silicon oxide layer at the grooved position and burn the lower layer silicon to form an inverted pyramid structure
According to the embodiment of the invention, laser grooving can be carried out on a silicon oxide compound layer (SiOx layer) on the back surface of the battery on an ultraviolet laser (a laser area is shown as 17 in figure 2), the pattern of the grooving is consistent with the pattern of metal fine grid lines formed on the back surface of a silicon wafer subsequently, after the SiOx layer on the surface layer of the pattern area is removed, the laser simultaneously burns the silicon on the lower layer to form an inverted pyramid structure, and finally Mark points are printed on the corners of the battery 4 for alignment in the subsequent screen printing. The metal grid lines formed on the back of the silicon wafer are arranged at the positions corresponding to the slotted graphs, the silicon-oxygen compound layer on the back of the battery is subjected to laser slotting, the silicon substrate can be exposed and form an inverted pyramid structure, in the metalized area (namely the area in contact with the back electrode) on the back of the silicon wafer, the silicon substrate is in contact with metal slurry through the inverted pyramid structure, the mutual contact area is larger, the contact resistance is smaller, the series resistance is correspondingly smaller, the conductive effect can be further improved, therefore, even if the nonmetal contact on the back of the battery has larger alkali polishing block size, the good contact effect of the silicon substrate and the electrode can be ensured, and the conductivity is improved.
According to some embodiments of the present invention, the power of the laser grooving may be 20W ± 5W, and the frequency may be 40000Hz ± 2000Hz, and the inventors found that if the laser power is too low or the frequency is too low, it is difficult to achieve a better laser grooving effect and a burning effect on the underlying silicon, and if the laser power is too high or the frequency is too high, it is difficult to control the laser degree, which is not favorable for forming a desired pyramid structure.
(5) Carrying out back corrosion treatment on the silicon wafer obtained in the step (4), and removing the silicon-oxygen compound layer in the non-laser area;
according to the embodiment of the invention, the main purpose of carrying out back etching treatment on the silicon wafer is to eliminate the damage layer formed by the last step of laser burning, modify the inverted pyramid structure and finally remove the SiOx layer in the non-laser area by adopting hydrofluoric acid.
According to a specific embodiment of the present invention, the silicon wafer may be put into a tank-type texture etching cleaning machine for performing a back etching treatment, wherein the etching solution may include an alkali and an etching additive, the types of the alkali and the etching additive in the etching solution are not particularly limited, and those skilled in the art may select the alkali according to actual needs, for example, the alkali may be KOH and/or NaOH, the volume concentration of the alkali may be 1 v% ± 0.2 v%, the etching additive may be an etching additive conventional in the art, the temperature of the etching solution may be 80 ℃ ± 3 ℃, the time of the etching treatment may be 120s ± 10s, and by controlling the texture etching conditions, the damaged layer formed by the previous laser burning may be effectively eliminated, and the inverted pyramid structure may be modified.
(6) And (5) depositing a tunneling oxide layer and a polysilicon layer on the back surface of the silicon wafer obtained in the step (5).
According to embodiments of the present invention, a back side tunnel oxide (SiO) layer may be performed in a low pressure chemical vapor deposition furnace (LPCVD)2) And depositing a polysilicon (Poly) layer, wherein the thicknesses of the tunnel oxide layer and the polysilicon layer are not particularly limited, and may be selected by those skilled in the art according to actual needs, for example, the thickness of the tunnel oxide layer may be about 1.5nm, and the thickness of the polysilicon layer may be about 120 nm.
According to some embodiments of the present invention, the method for preparing the TopCon type N cell sheet may further comprise: (7) the side of the silicon chip with boron diffusion is taken as the front side, phosphorus is injected into a polycrystalline silicon layer on the back side of the silicon chip to form a passivation contact structure, wherein the step can be carried out in a back side phosphorus diffusion furnace, the passivation contact structure is formed by preparing an ultrathin tunneling oxidation layer and a phosphorus-doped polycrystalline silicon thin layer on the back side of the battery together, good surface passivation can be provided for the back side of the silicon chip, the ultrathin oxidation layer can enable multi-electron tunneling to enter the polycrystalline silicon layer and simultaneously block minority hole recombination, and then electrons are transversely transmitted in the polycrystalline silicon layer and collected by metal, so that metal contact recombination current can be greatly reduced, and open-circuit voltage and short-circuit current of the battery are improved.
According to still other embodiments of the present invention, the method for preparing the TopCon type N cell sheet may further comprise: the method specifically comprises the step of removing the silicon wafer front side wrapped polycrystalline silicon layer, wherein the polishing solution can be used in a groove type cleaning machine and comprises KOH and polishing additives, the concentration of the KOH in the polishing solution can be 4 wt%, the polishing additives can be conventional polishing additives in the field, the polishing temperature can be 66 +/-3 ℃, the process time can be 200 +/-20 s, and the silicon wafer front side wrapped polycrystalline silicon layer can be effectively removed by controlling the conditions.
According to still other embodiments of the present invention, the method for preparing the TopCon type N cell sheet may further comprise: (8) depositing an aluminum oxide layer and a silicon nitride layer on the front surface of the silicon wafer in sequence to form a front passivation layer; (9) depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) and printing electrode slurry on the front side and the back side of the silicon wafer and sintering to obtain the cell.
Compared with the prior art, the method for preparing the N-type TopCon battery piece has the advantages that the silicon-oxygen compound layer is deposited on the back surface of the silicon chip after the back surface polishing treatment, the silicon-oxygen compound layer is subjected to laser grooving and silicon on the lower layer of the groove part is burned, the inverted pyramid structure can be formed on the surface of the silicon chip, and then the damaged surface caused by laser burning can be removed and the inverted pyramid structure can be modified through further texturing, so that the textured and modified pyramid structure can be used for contacting with a back surface metal electrode, the contact effect of the back surface of the silicon chip and the metal electrode is increased, the conductivity is improved, the square size of a non-contact area is allowed to be larger, and the better passivation effect is achieved. In conclusion, the preparation process has at least the following advantages: 1. when the back surface of the silicon wafer is polished, a square shape with larger size can be formed on the back surface of the silicon wafer, for example, the size of the square can reach about 20 microns, and compared with the size of the square with the size of about 5 microns formed by the conventional back surface polishing, the square shape with larger size can be formed in the invention, so that the deposition of a passivation film on a larger square and a flat silicon substrate is more compact, and the passivation effect is better; 2. when a square shape with larger size is formed on the back surface of the silicon chip, the etching amount controlled by back surface polishing is larger than that of the conventional process, so that the side surface and the back surface of the battery are completely removed, a better parallel resistance of the battery is ensured, and electric leakage is prevented; 3. in a metalized area (namely an area contacted with a back electrode) on the back of the silicon chip, the silicon substrate is contacted with the metal slurry through an inverted pyramid structure, and the mutual contact area is larger, so that the contact resistance is smaller, the series resistance is correspondingly smaller, and the conductive effect can be further improved; 4. the battery prepared by the method can be compatible with the back passivation and good contact performance of the back metal slurry and the silicon substrate, the resistance is lower, the open-circuit voltage, the filling factor and the conversion efficiency of the battery can be improved, for example, the series resistance can be reduced by 1.5m omega or even more, the open-circuit voltage can be improved by 5mV or even more, the filling factor can be improved by 0.4 percent or even more, and the conversion efficiency of the battery can be improved by 0.3 percent or even more.
According to the second aspect of the invention, the invention also provides an N-type TOPCon battery piece prepared by the method for preparing the N-type TopCon battery piece. Specifically, according to some specific examples of the present invention, as understood with reference to fig. 2, the N-type TOPCon cell piece may include an N-type single-crystal silicon substrate 10, a front surface electrode 11 (e.g., Ag/Al electrode), and a back surface electrode 12 (e.g., Ag electrode), wherein the front surface of the N-type single-crystal silicon substrate 10 has P+Doped layer 13, front electrode 11 and P+Doped layer 13 in direct contact, P+The contact region between the doping layer 13 and the front electrode 11 has a textured pyramid structure, P+The doped layer 13 is covered with a front passivation layer 14 in the region not in contact with the front electrode 11, wherein the front passivation layer 14 is formed with an aluminum oxide layer and a silicon nitride layer in sequence in the direction away from the front surface of the single crystal silicon substrate 10, and the front electrode 11 can be an Al electrode or an Ag electrode; the back surface of the N-type single crystal silicon substrate 10 has N+Doped layer 15, back electrode 12 and N+Doped layer 15 in direct contact, N+The doped layer 15 and the corresponding contact region of the monocrystalline silicon substrate 10 and the back electrode 12 have a textured pyramid structure, N+The doped layer 15 is not contacted with the back electrode 12, the square shape is a square shape, the size of the square in the square shape is 20 microns +/-2 microns, the square shape is covered with a back passivation layer 16, and the back passivation layer 16 is sequentially formed with a polycrystalline silicon doped layer and a silicon nitride layer in the direction away from the back of the monocrystalline silicon substrate 10. Compared with the prior art, the N-type TopCon battery piece has larger shape and size of the back square, better passivation effect, better contact effect with the electrode and high conductivity, and is compatible with the reverse pyramid suede structure of the back of the battery and the back electrodeThe back passivation has good contact performance with the back metal slurry and the silicon substrate, the resistance is lower, and the open-circuit voltage, the filling factor and the conversion efficiency of the battery are improved. It should be noted that the features and effects described for the above method for preparing the N-type TopCon cell sheet are also applicable to the N-type TopCon cell sheet, and are not described herein again. In addition, "P" in the present invention+Doped layers "and said" N+In the doped layer, "P" refers to P-type (positive electrode), "N" refers to N-type (negative electrode), "+" refers to heavy doping, and "P" is high relative to the intrinsic silicon doping concentration+Doped layer "represents a heavily doped P-type layer," N+Doped layer "means a heavily doped N-type layer.
The following examples are illustrative only and are not to be construed as limiting the invention. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products commercially available.
Example 1
Preparing an N type TopCon cell piece:
1. the first step of the process steps is that the N-type bare silicon wafer is put into a groove type texturing cleaning machine to carry out an alkali texturing process, the solution is KOH + texturing additive solution with the concentration of 1 +/-0.2 v%, the temperature of the solution is 80 +/-3 ℃, the process time is 500 +/-15 s, the etching amount is 0.58 +/-0.05 g, and the reflectivity is 9 +/-0.5%;
2. carrying out a boron diffusion process on the battery piece subjected to texturing in the second step in a boron diffusion furnace tube, wherein the sheet resistance is 120 +/-20 omega/sq, and the process temperature is 950 +/-50 ℃;
3. thirdly, removing a BSG layer on the back surface in a chain type BSG removing cleaning machine, wherein the solution is hydrofluoric acid with the concentration of 40 +/-5 wt%, and the process temperature is 20 +/-3 ℃;
4. fourthly, carrying out back alkali polishing in a groove type cleaning machine, wherein the solution is KOH + polishing additive with the volume concentration of 4 +/-0.2 v%, the solution temperature is 65 +/-3 ℃, the process time is 400 +/-20 s, the back appearance is a square block with the size of 20 +/-2 mu m, and the back reflectivity is 42 +/-1%;
5. fifthly, depositing a SiOx layer on the back surface of the battery in an atmospheric pressure chemical vapor deposition device (APCVD), wherein the thickness of the SiOx layer is 100 +/-10 nm;
6. sixthly, performing laser grooving on the SiOx layer on the back of the battery on an ultraviolet laser, wherein the laser power is 20W, the frequency is 40000Hz, the grooved pattern is consistent with the pattern of the metal fine grid line on the back, after the SiOx layer on the surface layer of the pattern region is removed, the laser simultaneously burns the silicon on the lower layer to form an inverted pyramid structure, and finally, marking Mark points on 4 corners of the battery for aligning during the subsequent silk-screen printing;
7. seventhly, performing alkali corrosion in a tank type cleaning machine, wherein the solution is KOH + corrosion additive with the concentration of 1 +/-0.2 v% (volume ratio), the temperature of the solution is 80 +/-3 ℃, and the process time is 120 +/-10 s, and the method mainly aims to eliminate a damage layer formed by laser burning in the previous step, modify an inverted pyramid structure and finally remove the SiOx film in the non-laser area in the later hydrofluoric acid tank;
8. eighth step of performing back tunneling oxide (SiO) in Low Pressure Chemical Vapor Deposition (LPCVD) furnace2) And depositing a polycrystalline silicon (Poly) layer, wherein the thickness of the tunneling oxide layer is 1.5 +/-0.2 nm, and the thickness of the Poly is 120 +/-20 nm;
9. ninth, injecting phosphorus into the back Poly layer by a back phosphorus diffusion furnace to form a passivation contact structure;
10. the tenth step is that the front surface is removed from the groove type cleaning machine and is coated with the Poly layer in a winding way, the solution is KOH plus polishing additive with the concentration of 4 plus or minus 0.2v percent (volume ratio), the temperature is 66 plus or minus 3 ℃, and the process time is 200 plus or minus 20 s;
11. eleventh, coating films on the front AlOx + SiNx and the back SiNx passivation films;
12. and finally, screen printing and sintering test sorting of the battery piece.
Comparative example 1
Preparing an N type TopCon cell piece:
1. the first step of the process comprises the steps of putting an N-type bare silicon wafer into a groove type texturing cleaning machine to carry out an alkali texturing process, wherein the solution is KOH + texturing additive solution with the concentration of 1 +/-0.2 v% (volume ratio), the solution temperature is 80 +/-3 ℃, the process time is 500 +/-15 s, the etching amount is 0.58 +/-0.05 g, and the reflectivity is 9 +/-0.5%;
2. carrying out a boron diffusion process on the battery piece subjected to texturing in the second step in a boron diffusion furnace tube, wherein the sheet resistance is 120 +/-20 omega/sq, and the process temperature is 950 +/-50 ℃;
3. thirdly, removing a BSG layer on the back surface in a chain type BSG removing cleaning machine, wherein the solution is hydrofluoric acid with the concentration of 40 +/-5 wt%, and the process temperature is 20 +/-3 ℃;
4. fourthly, carrying out back alkali polishing in a groove type cleaning machine, wherein the solution is KOH + polishing additive with the concentration of 4 +/-0.2 v%, the solution temperature is 65 +/-3 ℃, the process time is 160 +/-10 s, the back appearance is a square block with the size of 5 +/-0.5 mu m, and the back reflectivity is 40 +/-1%;
5. the fifth step is to carry out back tunneling oxide (SiO) in a low pressure chemical vapor deposition furnace (LPCVD)2) And depositing a polycrystalline silicon (Poly) layer, wherein the thickness of the tunneling oxide layer is 1.5 +/-0.2 nm, and the thickness of the Poly is 120 +/-20 nm;
6. sixthly, injecting phosphorus into the back Poly layer by using a back phosphorus diffusion furnace to form a passivation contact structure;
7. seventhly, removing a front surface winding and plating Poly layer in a groove type cleaning machine, wherein the solution is KOH + polishing additive with the concentration of 4 +/-0.2 v% (volume ratio)% and the temperature is 66 +/-3 ℃, and the process time is 200 +/-20 s;
8. eighthly, coating films on the front AlOx + SiNx and the back SiNx passivation films;
9. and finally, screen printing and sintering test sorting of the battery piece.
Comparative example 2
The difference from example 1 is that:
4. fourthly, carrying out back alkali polishing in a groove type cleaning machine, wherein the solution is KOH + polishing additive with the concentration of 4 +/-0.2 v% (volume ratio), the temperature of the solution is 65 +/-3 ℃, the process time is 800 +/-20 s, the appearance of the back is a square block with the size of 40 +/-2 mu m, and the back reflectivity is 43 +/-1%;
example 2
The difference from the embodiment 1 is in steps 4 to 7. Specifically, the method comprises the following steps:
4. fourthly, carrying out back alkali polishing in a groove type cleaning machine, wherein the solution is KOH + polishing additive with the concentration of 4 +/-0.2 v% (volume ratio) wt%, the solution temperature is 65 +/-3 ℃, the process time is 600 +/-20 s, the back appearance is a square block with the size of 30 +/-2 mu m, and the back reflectivity is 42.5 +/-1%;
5. fifthly, depositing a SiOx layer on the back surface of the battery in normal pressure chemical vapor deposition equipment (APCVD), wherein the thickness of the SiOx layer is 100 +/-10 nm;
6. sixthly, performing laser grooving on the SiOx layer on the back of the battery on an ultraviolet laser, wherein the laser power is 20W, the frequency is 40000Hz, the grooved pattern is consistent with the pattern of the metal fine grid line on the back, after the SiOx layer on the surface layer of the pattern region is removed, the laser simultaneously burns the silicon on the lower layer to form an inverted pyramid structure, and finally, marking Mark points on 4 corners of the battery for aligning during the subsequent silk-screen printing;
7. and seventhly, performing alkali corrosion in a tank type cleaning machine, wherein the solution is KOH + corrosion additive with the concentration of 1 +/-0.2 v% (volume ratio), the temperature of the solution is 80 +/-3 ℃, and the process time is 120 +/-10 s, and the method mainly aims to eliminate a damage layer formed by laser burning in the previous step, modify an inverted pyramid structure and finally remove the SiOx film in the non-laser area in the later hydrofluoric acid tank.
Evaluation and results
The electrical properties of the cells prepared in examples 1-2 and comparative examples 1-2 were tested, and the test results are shown in table 1.
TABLE 1 comparison of cell Electrical Performance parameters (average of 100 cells) for examples 1-2 and comparative examples 1-2
| Number of battery pieces | Eff(％) | Voc(mV) | Jsc(mA/cm2) | FF(％) | |
| Example 1 | 100 | 24.54 | 723 | 41.33 | 82.12 |
| Comparative example 1 | 100 | 24.22 | 716 | 41.31 | 81.90 |
| Comparative example 2 | 100 | 24.52 | 722 | 41.35 | 82.13 |
| Example 2 | 100 | 24.47 | 721 | 41.34 | 82.10 |
Wherein, Total is the number of the battery pieces; eff is the battery conversion efficiency; voc is the open circuit voltage; jsc is short-circuit current density; FF is the fill factor.
As can be seen from Table 1, compared with the square with the back surface of 5 +/-0.5 μm in size in the comparative example 1 and the process without combining the laser grooving, the preparation process of the invention can improve the open-circuit voltage, the short-circuit current, the filling factor and the conversion efficiency of the battery. In addition, although the alkaline polishing time adopted in example 2 and comparative example 2 is longer, the size of the obtained back surface morphology square is larger, and the average performance parameter of the cell is closer to that of example 1, the cell adopted in the test is a qualified cell which can be prepared, and in the actual operation process, compared with example 1, the cell of example 2 and comparative example 2 not only has lower preparation efficiency and lower yield, but also has the situation that the front surface mask needing to be protected is partially etched in the cell preparation process, so that the performance of individual cells is reduced, and the average performance of the cell is affected; in addition, the silicon sheets in the battery pieces prepared in the example 2 and the comparative example 2 are relatively thinner, the limit load of the energy load of the battery pieces is smaller, and the risk of the battery pieces is higher.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A method for preparing an N-type TopCon battery piece is characterized by comprising the following steps:
(1) providing an N-type silicon wafer with a single side containing boron diffusion;
(2) taking the side of the silicon wafer, which is far away from the boron diffusion, as a back surface, and carrying out back polishing treatment on the silicon wafer so as to form a square shape with an expected size on the back surface of the silicon wafer;
(3) depositing a silicon-oxygen compound layer on the back surface of the silicon wafer obtained in the step (2);
(4) local laser grooving is carried out on the silicon oxide layer so as to remove the silicon oxide layer at the grooving part and burn the lower layer silicon to form an inverted pyramid structure;
(5) carrying out corrosion treatment on the silicon wafer obtained in the step (4), and removing the silicon-oxygen compound layer in the non-laser area;
(6) depositing a tunneling oxide layer and a polysilicon layer on the back surface of the silicon wafer obtained in the step (5),
and the metal grid line on the back of the silicon wafer is arranged at a position corresponding to the slotted graph.
2. The production method according to claim 1, wherein in the step (2), the etching amount of the polishing treatment is 0.58 g. + -. 0.05g based on 182 silicon wafer having a thickness of 170 μm. + -. 10 μm, a side length of 182 mm. + -. 0.25mm, and a chamfer diameter of 247 mm. + -. 0.25mm,
the polishing treatment temperature is 65 +/-3 ℃, the polishing treatment time is 400 +/-20 s, the adopted polishing solution comprises alkali and a polishing additive, the alkali comprises KOH and/or NaOH, and the volume concentration of the alkali is 4 v% +/-0.2 v%.
3. The method according to claim 1, wherein in the step (2), the dice form has a dice size of 20 μm ± 2 μm.
4. The method according to claim 1, wherein the silicon wafer back surface reflectivity obtained in step (2) is 42% ± 1%.
5. The production method according to claim 1, wherein in the step (3), the thickness of the silicon oxide layer is 90 to 150 nm.
6. The method according to claim 1, wherein in the step (4), the power of the laser grooving is 20W ± 5W, and the frequency is 40000Hz ± 2000 Hz.
7. The production method according to claim 1, wherein in the step (5), the temperature of the etching treatment is 80 ℃ ± 3 ℃ for 120s ± 10s,
wherein, the corrosive liquid adopted by the corrosion treatment comprises alkali, the alkali comprises KOH and/or NaOH, and the volume concentration of the alkali is 1 v% + -0.2 v%.
8. The production method according to any one of claims 1 to 7, characterized by further comprising:
(7) taking one side of the silicon wafer with boron diffusion as a front side, injecting phosphorus into the polycrystalline silicon layer on the back side of the silicon wafer, and removing the winding-plated polycrystalline silicon layer on the front side of the silicon wafer;
(8) depositing an aluminum oxide layer and a silicon nitride layer on the front surface of the silicon wafer in sequence to form a front passivation layer;
(9) depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer;
(10) and printing electrode slurry on the front side and the back side of the silicon wafer and sintering to obtain the cell.
9. An N-type TOPCon cell, characterized in that it is prepared by the method of any one of claims 1 to 8.
10. The N-type TOPCon cell of claim 9 comprising an N-type single crystal silicon substrate, a front electrode and a back electrode, wherein,
the front surface of the N-type monocrystalline silicon substrate is provided with P+Doped layer, the front electrode and the P+The doped layers are in direct contact with each other, P+The region of the doped layer, which is not in contact with the front electrode, is covered with a front passivation layer;
the back of the N-type monocrystalline silicon substrate is provided with N+A doped layer, the back electrode and the N+The doped layers are in direct contact, N+The doped layer and the corresponding monocrystalline silicon substrate and the contact region of the back electrode have a suede pyramid structure, and the N+The region of the doping layer, which is not in contact with the back electrode, is in a square shape, and the size of a square block in the square shape is 20 microns +/-2 microns.
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