CN114256292A

CN114256292A - Three-dimensional phase change memory and manufacturing method thereof

Info

Publication number: CN114256292A
Application number: CN202111252492.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2022-03-29

Abstract

The invention provides a three-dimensional phase change memory and a manufacturing method thereof, which enable each layer of phase change memory units and first wiring (namely word lines or bit lines) required by the phase change memory units to be manufactured separately, and further utilize the replacement of a sacrificial layer and the limiting and shrinking action of a dielectric side wall to manufacture the phase change memory units with bottom electrodes electrically contacted with first contacts, so that the shapes and the sizes of the phase change memory units are not completely dependent on the overlapping condition of the cross points of the word lines and the bit lines, the realization of smaller memory size and higher memory density is facilitated, the parasitic effect introduced by the word lines and the bit lines can be improved, and the programming current and the power supply requirements of the phase change memory are reduced. In addition, the contact plugs for leading out the word lines and the bit lines can be arranged on the periphery of the array formed by the phase change memory cells, so that the overall size of the phase change memory can be further reduced, and the storage density can be further improved.

Description

Three-dimensional phase change memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional phase change memory and a manufacturing method thereof.

Background

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and costly. Thus, the storage density of the planar memory cell is close to the upper limit, and a three-dimensional (3D) memory architecture is developed to solve the problem of density limitation in the planar memory cell.

The architecture of a currently mainstream three-dimensional Phase Change Memory (3D PCM) may include a single-layer Phase Change Memory cell (PCM cell), a two-layer stacked Phase Change Memory cell, or a four-layer stacked Phase Change Memory cell, and each layer of Phase Change Memory cell is generally formed at an intersection of a Word Line (WL) and a Bit Line (BL) perpendicular to each other in a self-aligned manner, and the shape and size of each layer of Phase Change Memory cell are completely dependent on an overlapping condition at the intersection of the word line and the bit line, so that the Phase Change Memory cell generally has a vertical square column shape as a whole.

Although the architecture of the three-dimensional phase change memory can break through the density limitation in the planar phase change memory, the shape and size of the phase change memory cell are completely dependent on the overlapping condition at the intersection of the word line and the bit line, and the phase change memory cell is in a vertical square column shape, which is not favorable for further shrinking the device size, and this is one of the technical problems to be solved by those skilled in the art.

Disclosure of Invention

An object of the present invention is to provide a three-dimensional phase change memory and a method of manufacturing the same, which can facilitate realization of a memory device of a smaller size and a higher memory density.

In order to achieve the above object, the present invention provides a method for manufacturing a three-dimensional phase change memory, comprising the following steps:

forming a first interlayer dielectric layer by adopting a first wiring process, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer, and the first wirings are bit lines or word lines;

forming a stack layer on the first interlayer dielectric layer and the first contact, the stack layer including a bottom electrode layer and a sacrificial layer stacked over the bottom electrode layer;

carrying out corresponding photoetching and etching on the stacked layers until the bottom electrode layer is patterned to form a plurality of stacked bodies which are spaced from each other;

forming a gap filling layer in a gap between adjacent stacks, the gap filling layer exposing a top surface of the sacrificial layer;

removing the sacrificial layer to form an opening, and further forming a medium side wall on the side wall of the opening;

and depositing a phase change storage layer on the surfaces of the opening, the medium side wall and the gap filling layer.

Optionally, the step of forming the first interlayer dielectric layer, the first wiring and the first contact by using a first wiring process includes:

forming a first dielectric layer on a substrate, and photoetching and etching the first dielectric layer to form a plurality of first grooves extending along a first direction;

forming first wirings filled in the first trenches;

covering a second dielectric layer on the first dielectric layer and the first wirings, and photoetching and etching the second dielectric layer to form a plurality of first contact holes on each first wiring, wherein the first dielectric layer and the second dielectric layer form the first interlayer dielectric layer;

and forming first contacts filled in the first contact holes.

Optionally, performing corresponding lithography and etching on the stacked layers along the first direction until the bottom electrode layer is patterned to form a plurality of stacked bodies which are spaced apart from each other and extend along the first direction;

and after depositing the phase change memory layer on the surfaces of the opening, the dielectric side wall and the gap filling layer, the manufacturing method further comprises:

correspondingly photoetching and etching the phase change memory layer and the rest of the stacked body along a second direction which is intersected with the first direction until the bottom electrode layer is patterned again so as to form a plurality of phase change memory units which are spaced from each other by a double-pattern exposure technology, wherein the bottom electrode layer of each phase change memory unit is aligned with and electrically contacted with the corresponding first contact;

forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills gaps between adjacent phase change storage units and buries the top surfaces of the phase change storage layers of the phase change storage units;

and forming a required second contact in the second interlayer dielectric layer by adopting a second wiring process, and forming a plurality of second wirings extending along the second direction on the second interlayer dielectric layer, wherein each second contact is aligned with and contacts with the corresponding phase change memory layer of the phase change memory unit, and each second wiring is electrically connected with the corresponding phase change memory unit through the corresponding second contact, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

Optionally, after depositing a phase change memory layer on the surfaces of the opening, the dielectric sidewall and the gap filling layer, and before or after performing corresponding photolithography and etching on the phase change memory layer and the remaining stacked body along the second direction to form a plurality of phase change memory cells spaced apart from each other, performing top surface planarization on the phase change memory layer until the top surface of the gap filling layer is exposed.

carrying out top surface planarization on the phase change storage layer until the top surface of the gap filling layer is exposed;

depositing a top electrode layer and a second wiring layer on the phase change storage layer and the gap filling layer in sequence;

and carrying out corresponding photoetching and etching on the second wiring layer, the top electrode layer, the phase change storage layer and the rest stacked body along the second direction until the bottom electrode layer is patterned again so as to form a plurality of phase change storage units which are spaced from each other and a plurality of top electrode wires and second wirings which extend along the second direction through a double-pattern exposure technology, wherein the bottom electrode layer of each phase change storage unit is aligned with and electrically contacted with the corresponding first contact, and each second wiring is electrically connected with a plurality of phase change storage units through the top electrode wires aligned below the second wiring, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

Optionally, the step of performing corresponding lithography and etching on the stack layers until the bottom electrode layer is patterned to form a plurality of mutually spaced stacks comprises:

carrying out corresponding photoetching and etching on the sacrificial layer by adopting a single-time exposure technology or a multiple-pattern exposure technology so as to form a pattern for defining each phase change memory cell in the sacrificial layer;

and etching the bottom electrode layer by taking the sacrificial layer as a mask to form stacked bodies corresponding to the phase change storage units, wherein gaps are formed between every two adjacent stacked bodies, and the bottom electrode layer in each stacked body is aligned with and electrically contacted with the corresponding first contact to be used as a bottom electrode of the phase change storage unit to be formed.

Optionally, after depositing a phase change memory layer on the surfaces of the opening, the dielectric sidewall, and the gap filling layer, the manufacturing method further includes:

carrying out top surface planarization on the phase change memory layer until the top surface of the gap filling layer is exposed so as to form a plurality of phase change memory units which are mutually spaced;

forming a second interlayer dielectric layer on the phase change memory layer and the gap filling layer by adopting a second wiring process, forming a required second contact in the second interlayer dielectric layer, and forming a plurality of second wirings extending along the second direction on the second interlayer dielectric layer, wherein each second contact is aligned with and contacts with the corresponding phase change memory layer of the phase change memory unit, and each second wiring is electrically connected with the corresponding phase change memory unit through the corresponding second contact.

Optionally, an interface protection layer is formed on sidewalls of the stacks before forming a gap fill layer in a gap between adjacent stacks.

Optionally, the first interlayer dielectric layer and the first wiring are formed on a substrate, the substrate has a storage region and a peripheral region located at a periphery of the storage region, the first wiring extends from the storage region into the peripheral region, and the manufacturing method further includes: and simultaneously forming corresponding electric connection structures in the peripheral area while the first wiring process is carried out in the storage area.

Based on the same inventive concept, the present invention also provides a three-dimensional phase change memory, which comprises:

the circuit comprises a first interlayer dielectric layer, a second interlayer dielectric layer and a plurality of first contacts, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer;

the phase-change memory units are formed on the first interlayer dielectric layer and are sequentially stacked, the bottom electrode layer is aligned to and electrically contacted with the corresponding first contact, a medium side wall is formed on the side wall of the phase-change memory layer, and the combined structure of the medium side wall and the phase-change memory layer is aligned to the bottom electrode layer;

the gap filling layer is filled in the gap between the adjacent phase change memory units;

a plurality of second wirings extending in a second direction intersecting the first direction, the second wirings being formed above the phase change memory cells and the gap filling layer, and each of the second wirings being electrically connected to a corresponding one of the phase change memory cells through a corresponding second contact or a top electrode line extending in the second direction;

wherein the first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

Optionally, the three-dimensional phase change memory further includes a substrate, the first interlayer dielectric layer and the first wiring are formed on the substrate, the substrate has a storage region and a peripheral region located at a periphery of the storage region, and an electrical connection structure formed together with the first wiring and the first contact is formed in the peripheral region.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. the manufacturing method comprises the steps of firstly forming a first wiring used as a bit line or a word line and a first contact on the first wiring on a substrate by adopting a first wiring process, and then manufacturing a phase change memory unit with a bottom electrode electrically contacted with the first contact by utilizing the replacement of a sacrificial layer and the limitation of a dielectric side wall.

2. The gate layer is etched by utilizing the shielding and protecting effects of the sacrificial layer, and then the sacrificial layer is replaced by the phase-change storage layer, so that the phase-change storage layer and the gate layer are not etched together at least in the direction along the word line or the bit line, the problem of cross contamination between the phase-change storage layer and the gate layer can be further improved, and the respective performances of the phase-change storage layer and the gate layer are guaranteed.

3. The bit line, the phase change memory cell and the word line can be manufactured separately, so that the bit line, the phase change memory cell and the word line can be manufactured by respectively adopting a corresponding single exposure technology (or a single patterning processing technology), thereby avoiding the process complexity and cost brought by the double patterning technology used for manufacturing the word line and the bit line in the prior art, and achieving the effects of simplifying the process steps and reducing the cost.

4. After the stacked layer is patterned in the first direction to form a stacked body, the second wiring layer, the top electrode layer, the phase change memory layer, and the remaining stacked body are patterned in the second direction together, thereby further simplifying the process complexity and cost for manufacturing the second wiring (i.e., word line or bit line).

5. Since the second wire (for example, the word line) can be electrically contacted with the top electrode of the phase change memory cell through the second contact, and the first wire (for example, the bit line) can be electrically contacted with the bottom electrode of the phase change memory cell through the first contact, parasitic effects (including parasitic resistance R, parasitic capacitance C, RC delay effect and the like) caused by the word line and the bit line can be reduced, the crosstalk problem between adjacent memory cells is improved, and further, the programming current and the power supply requirement of the phase change memory are reduced.

6. And a peripheral area can be further arranged, and electrical connection structures (contact plugs) respectively used for leading the first wiring and the second wiring outwards are uniformly arranged on the periphery of an array (namely a storage area) formed by the phase change memory unit, so that the problem that the storage area is occupied by the word line contact plug and the bit line contact plug in the prior art can be avoided, and the overall size of the phase change memory can be further reduced, and the storage density can be further improved.

7. The first wiring process and the second wiring process may be respectively a manufacturing process of two-layer metal lines in a multi-layer metal interconnection process in the peripheral region, thereby embedding the manufacturing of the phase change memory into a manufacturing process of the peripheral integrated circuit.

Drawings

Fig. 1A to 1C are schematic cross-sectional views of a device structure in a conventional method for manufacturing a three-dimensional phase change memory.

Fig. 2 is a schematic diagram illustrating the distribution of word lines, bit lines and contact holes thereof in a conventional three-dimensional phase change memory.

Fig. 3 is a flowchart illustrating a method for fabricating a three-dimensional phase change memory according to an embodiment of the invention.

Fig. 4A to 4H are schematic cross-sectional views of a device in a method for manufacturing a three-dimensional phase change memory according to a first embodiment of the invention.

FIG. 5 is a schematic top view illustrating a method for fabricating a three-dimensional phase change memory according to a first embodiment of the present invention.

FIG. 6 is a schematic top view illustrating a method for fabricating a three-dimensional phase change memory according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a device in a method for fabricating a three-dimensional phase change memory according to a second embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating the distribution of word lines, bit lines and contact holes thereof in the three-dimensional phase change memory shown in FIG. 6.

Fig. 9 and 10 are a schematic cross-sectional view and a schematic top-view structure of a device in a method for manufacturing a three-dimensional phase change memory according to a fourth embodiment of the invention.

Fig. 11 is a schematic top view illustrating a method for fabricating a three-dimensional phase change memory according to a fifth embodiment of the invention.

Fig. 12 is a schematic cross-sectional view of a device in a method for manufacturing a three-dimensional phase change memory according to a sixth embodiment of the invention.

Wherein the reference numerals are:

100-a substrate; 101-a first interlayer dielectric layer; 1011-first dielectric layer; 1012-second dielectric layer; 102 — a first wiring; 102' -a first level of word line peripheral circuit wiring (i.e., a level of metal wiring in a multi-level metal interconnect structure in the peripheral region); 103-a first contact; 103' -peripheral contacts; 104-lower structural layer of phase change memory cell; 1041-a bottom electrode layer; 1042-gating layer; 1043-an intermediate electrode layer; 105-a sacrificial layer; 106-gap; 107-an interface protection layer; 1071 — a first interface layer; 1072 — a second interface layer; 1073 — a third interface layer; 108-a gap-fill layer; 109-opening; 110-dielectric sidewall spacers; 111-phase change storage reservoir; 112-a second interlayer dielectric layer; 113-a second contact; 113' -peripheral contacts; 114 — a second wiring; 114' -a second layer of word line peripheral circuit wiring (i.e., another layer of metal wiring in the multi-layer metal interconnect structure in the peripheral region); 115-top electrode line; 115' -peripheral wiring; cell-phase change memory cell; WL-word line; BBL-bottom bit line; TBL-top bit line; CT1 — second contact plug (i.e., bit line contact plug to BBL); CT2 — first contact plug (i.e., word line contact plug to WL); CT 3-third contact plug (i.e., bit line contact plug to TBL).

Detailed Description

Referring to fig. 1A to 1C, in the conventional method for manufacturing a three-dimensional phase change memory, when forming each layer of phase change memory cells and bit lines BL and word lines WL electrically connected to the phase change memory cells, a double patterning technique (also referred to as a double pattern exposure technique) is usually adopted, and the double patterning technique requires two times of overlapping the patterns of the word lines WL and the bit lines BL to define the patterns of the phase change memory cells at the intersections of the word lines WL and the bit lines BL.

For example, when fabricating the bottom phase-change memory cell, the word line WL electrically connected to the bottom phase-change memory cell, and the bottom bit line BL, it is usually necessary to perform a photolithography and etching process on the stacked layer deposited for fabricating the bottom phase-change memory cell and the bottom bit line layer, and perform a first re-patterning to form a plurality of bit lines BL extending along the horizontal direction Y and divide the stacked layer into a plurality of bottom stacked bodies in parallel lines extending along the horizontal direction Y, where a gap is formed between the stacked bodies of adjacent bottom layers, as shown in fig. 1A; after gap filling and deposition of the word line layer, the stacked body of the word line layer and the bottom layer is subjected to photolithography and etching once again, a second re-patterning is performed to form several word lines WL extending in the horizontal direction X, and the stacked body of the bottom layer extending in the Y direction in fig. 1A is simultaneously subjected to division in the X direction, thereby forming phase change memory cells cell located at intersections of the word lines WL and the bottom bit lines BL, as shown in fig. 1B.

When it is necessary to further fabricate the top phase change memory cell and the electrically connected top bit line BL on the basis of the structure shown in fig. 1B, similarly, it is also necessary to implement double patterning (double patterning technology), specifically, a first re-patterning is performed on the deposited stack layer of the phase change memory cell for fabricating the top layer to form a stack of top layers extending in the horizontal direction X and having parallel lines, and then a second re-patterning is performed on the top layer and the stack of top layers after gap filling and deposition of the top layer bit line layer, to form bit lines BL of the top layer extending in the Y direction and simultaneously to divide the stack of the top layer extending in the X direction in the Y direction, thereby forming a phase change memory cell located at an intersection of the word line WL and the top-level bit line BL, as shown in fig. 1C.

If the architecture of the three-dimensional phase-change memory includes four stacked phase-change memory cells, the sequential structure of bit line-phase-change memory cell-word line-phase-change memory cell can be repeatedly fabricated once again along the Z-direction in the above-described manner.

Referring to fig. 2, in the conventional three-dimensional phase change memory architecture, word line contact plugs (also called contacts or contacts in some embodiments, i.e., CT1 in fig. 2) for leading word lines WL out, bit line contact plugs (i.e., CT2 in fig. 2) for leading bit lines BBL out of the bottom layer, and bit line contact plugs (i.e., CT3 in fig. 2) for leading bit lines TBL out of the top layer are typically arranged in an array formed by phase change memory cells.

The inventor researches and discovers that the following defects exist in the conventional three-dimensional phase change memory and the manufacturing method thereof: (1) because each layer of phase change memory cell and the manufacture of the bit line BL and the word line WL which are electrically connected with each layer of phase change memory cell need to use a double patterning technology, the shape and the size of each layer of phase change memory cell completely depend on the overlapping condition of the cross points of the word line and the bit line, and the phase change memory cell is not beneficial to realizing smaller memory size and higher memory density; (2) the process is complex and expensive, and the reduction of parasitic effects (including parasitic resistance R, parasitic capacitance C, RC delay effect, and the like) introduced by the word line WL and the bit line BL is limited; (3) because both the word line contact plug and the bit line contact plug are arranged in the array formed by the phase change memory unit, the area of a storage area of the phase change memory is occupied, and the further reduction of the size and the density of the whole phase change memory is limited; (4) when the deposited stack layer for fabricating the phase-change memory cell includes a bottom electrode layer, an access layer (OTS) intermediate electrode layer, a phase-change memory layer, and a top electrode layer from bottom to top, in the double patterning technique, when the stack layer is etched in the Y direction and the stack layer formed is further etched in the X direction, the phase-change memory layer and the access layer are usually etched together, which easily causes cross contamination between the phase-change memory layer and the access layer, and affects respective performances of the phase-change memory layer and the access layer.

Based on this, the invention provides a three-dimensional phase change memory and a manufacturing method thereof, so that each layer of phase change memory unit and a first wiring (namely word line or bit line) required by the phase change memory unit are separately manufactured, and the phase change memory unit with a bottom electrode electrically contacted with a first contact is further manufactured by utilizing the replacement of a sacrificial layer and the limiting effect of a dielectric side wall, so that the shape and the size of the phase change memory unit are not completely dependent on the overlapping condition of the cross point of the word line and the bit line any more, the realization of smaller memory size and higher memory density is facilitated, the parasitic effect introduced by the word line and the bit line can be improved, and the programming current and the power supply requirement of the phase change memory are reduced. Further, when the word lines, the bit lines and the phase change memory cells are all implemented by using a single exposure technique, the process complexity and cost of using a double patterning technique to fabricate the word lines and the bit lines in the prior art can be further avoided. In addition, contact plugs (also called electrical connection structures) for leading out word lines and contact plugs for leading out bit lines can be arranged on the periphery of the array formed by the phase change memory cells, so that the phase change memory can be further miniaturized in overall size and further improved in storage density.

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to scale, which is intended merely for convenience and clarity in assisting in the description of the embodiments of the invention.

First embodiment

Referring to fig. 3, the present embodiment provides a method for manufacturing a three-dimensional phase change memory, which includes the following steps:

s1, forming a first interlayer dielectric layer by adopting a first wiring process, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer, and the first wirings are bit lines or word lines;

s2, forming a stack layer on the first interlayer dielectric layer and the first contact, wherein the stack layer comprises a bottom electrode layer and a sacrificial layer stacked above the bottom electrode layer;

s3, carrying out corresponding photoetching and etching on the stacked layers until the bottom electrode layer is patterned to form a plurality of stacked bodies which are spaced from each other;

s4, forming a gap filling layer in the gap between the adjacent stacked bodies, wherein the gap filling layer exposes the top surface of the sacrificial layer;

s5, removing the sacrificial layer to form an opening, and further forming a medium side wall on the side wall of the opening;

and S6, depositing a phase change storage layer on the surfaces of the opening, the medium side wall and the gap filling layer.

First, referring to fig. 4A, in step S1, a substrate 100 is provided, and then a first interlayer dielectric layer 101, a plurality of first wires 102 extending along a first direction Y, and a plurality of first contacts 103 on each first wire 102 may be formed on the substrate 100 by using a first wire process.

The substrate 100 may be a wafer material that has been processed through a series of integrated circuit manufacturing processes, and the wafer material may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds, which may also be a multilayer structure or be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeO), and the like. The substrate 100 may have active or passive electronic elements such as MOS transistors, diodes, and resistors formed therein, may have a device isolation structure, and may further have a multilayer metal interconnection structure. When the three-dimensional phase change memory to be formed has two or four or more stacked phase change memory cells, the fabrication of some layers of the phase change memory cells and their electrically connected word lines and/or bit lines in the substrate 100 may also be completed.

When the first wirings 102 are used as bit lines, a column of phase change memory cells are formed above the first contacts 103 on each first wiring 102, and when the first wirings 102 are used as word lines, a row of phase change memory cells are formed above the first contacts 103 on each first wiring 102.

The process of step S1 and the subsequent steps S2 to S4 will be described in detail below, taking as an example that the first wiring 102 serves as a bit line and the second wiring formed subsequently serves as a word line.

As an example, in step S1, the process of forming the first interlayer dielectric layer 101, the first wiring 102, and the first contact 103 includes:

first, a first dielectric layer 1011 is formed on the substrate 100 by a suitable process such as chemical vapor deposition, spin coating, etc., wherein the material of the first dielectric layer 1011 includes any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, etc. The first dielectric layer 1011 is preferably a low-k dielectric having a dielectric constant k less than 3, so as to reduce the parasitic effect introduced by the first wire.

Next, using a bit line mask, the first dielectric layer 1011 is subjected to photolithography and etching to form a plurality of first trenches (not shown) extending along the first direction Y.

Then, the conductive material is filled into each first trench by a suitable process of chemical vapor deposition, sputter deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, or the like, and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP) stopping on the top surface of the first dielectric layer 1011 to form the first wiring 102 filled in each first trench, whereby the material of the first wiring 102 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, metal silicide, or the like.

Next, by using a suitable process such as chemical vapor deposition and spin coating, a second dielectric layer 1012 is covered on the first dielectric layer 1011 and the first wire 102, the first interlayer dielectric layer 101 is formed by the second dielectric layer 1012 and the first dielectric layer 1011, and the material of the second dielectric layer 1012 may be the same as or different from that of the first dielectric layer 1011.

Thereafter, the second dielectric layer 1012 may be subjected to photolithography and etching of the contact hole lattice by means of a corresponding mask capable of defining the contact hole lattice to form a plurality of first contact holes (not shown) on each first wire 102, which expose top surfaces of corresponding positions of the first wire 102. When the size and shape of the phase change memory cell to be formed are substantially the same as those of the first contact 103 to be formed, the mask capable of defining the contact hole lattice is a mask for manufacturing the phase change memory cell array.

Then, by a suitable process such as chemical vapor deposition, sputter deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, etc., the first contact holes are filled with a conductive material, and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP), which stops on the top surface of the second dielectric layer 1012, to form the first contacts 103 filled in the first contact holes. The material of the first contact 103 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, and the like. The material of the first contact 103 may be the same as or different from that of the first wiring 102, and for example, the first wiring 102 is made of copper and the first contact 103 is made of tungsten. The phase change memory cells connected to the same first wiring 102 through the first contact 103 subsequently constitute a column of phase change memory cells.

Of course, the first wiring process may not be limited to the above example, and in another example of the present embodiment, the process of forming the first interlayer dielectric layer 101, the first wiring 102 and the first contact 103 by the first wiring process may include forming a plurality of first wirings 102 separated from each other and extending along the first direction Y on the substrate 100 by a metal lift-off (lift-off) process, in which a patterned photoresist layer is formed on the substrate 100, then a metal layer covers the patterned photoresist layer and the gaps thereof, and then the patterned photoresist layer is peeled off, the metal layer filled in the gaps of the patterned photoresist layer is the first wiring 102, and the metal layers outside the gaps are removed along with the peeling of the photoresist layer; then, a first interlayer dielectric layer 101 is covered on the gap of the first wire 102 and the top surface of the first wire 102, the first interlayer dielectric layer 101 may fill the gap of the first wire 102, then holes are punched in the first interlayer dielectric layer 101 at corresponding positions of the first wire 102 to form first contact holes arranged in an array, the first contact holes expose the top surface of the first wire 102, and then the first contacts 103 filled in the first contact holes are further formed according to the method of the foregoing example.

Alternatively, the first wiring process may be a copper wiring process (e.g., a copper interconnect process or a rewiring process using copper wires, etc.).

The first wire 102 can be realized by a single patterning technique (also referred to as a single patterning technique, a single photolithography technique, etc.) without a double patterning technique, and has a few process steps and a low cost.

With reference to fig. 4A, in step S2, a bottom electrode layer 1041, a gate layer 1042, an intermediate electrode layer 1043, and a sacrificial layer 105 may be sequentially covered on the first interlayer dielectric layer 101 and the first contact 103 by a suitable process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, to form a stack layer. The bottom electrode layer 1041 and the middle electrode layer 1043 may be made of the same material or different materials, and may be respectively selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, and Ni. The gate layer 1042 may include an Ovonic Threshold Switch (OTS) material. The material of the sacrificial layer 105 may be an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, may be an organic insulating layer including polyvinyl phenol, polyimide, siloxane, or the like, may be a single-layer film, or may be a composite structure in which a plurality of layers are stacked, and for example, the sacrificial layer 105 includes an organic material layer (not shown) and a hard mask layer (not shown) stacked from the bottom up. The bottom electrode layer 1041, the gate layer 1042 and the middle electrode layer 1043 are used for forming the lower structural layer 104 of the phase change memory cell. In other embodiments of the present invention, the gate layer 1042 and the middle electrode layer 1043 can be omitted.

In this embodiment, the stack layer needs to be processed by the double-pattern exposure technique to form the finally required phase-change memory cell, in step S3, the first pattern exposure in the double-pattern exposure technique is performed only on the stack layer, and the second pattern exposure in the double-pattern exposure technique is performed on the stack layer after step S6.

Specifically, referring to fig. 4B, in step S3, according to the size of the phase change memory cell to be formed, the stacked layers are correspondingly etched and patterned along the first direction Y until the bottom electrode layer 1041 is patterned to form a plurality of stacked bodies (not labeled) spaced apart from each other and extending along the first direction Y, where the gaps 106 between adjacent stacked bodies are trenches extending along the first direction Y. The line width of the stacked body may be smaller than, equal to, or larger than the line width of the first wiring 102. In this step, the sacrificial layer 105 may be first subjected to corresponding photolithography and etching to form a corresponding pattern in the sacrificial layer 105, and then the lower structural layer 104 formed from the middle electrode layer 1043 to the bottom electrode layer 1041 may be etched using the sacrificial layer 105 as a mask to form a desired stacked body.

Referring to fig. 4C and 4D, in step S4, first, an interface protection layer 107 is formed on the sidewall of the stacked body by a suitable method such as a deposition method or a plasma reaction method; next, depositing a gap filling layer 108 in the gap 106 between the adjacent stacks and on the top surface of the sacrificial layer 105 by a suitable material deposition process such as chemical vapor deposition, high aspect ratio vapor deposition, etc., wherein the deposited gap filling layer 108 can fill the gap 106 and can also close the gap 106 into a structure with an air gap (the air gap can reduce parasitic capacitance); then, chemical mechanical polishing is performed on the top of the gap fill layer 108 until the top surface of the sacrificial layer 105 of each stack is exposed. The material of the interface protection layer 107 may be at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. The interface protection layer 107 can improve adhesion between the subsequent gap filling layer and the sidewalls of the middle electrode layer 1043 to the bottom electrode layer 1041 of the stacked body, and block element diffusion between the middle electrode layer 1043 to the bottom electrode layer 1041 and the subsequently formed gap filling layer, thereby preventing material components of each film layer from changing and ensuring device performance. In the present embodiment, the interface protection layer 107 has a first interface layer 1071, a second interface layer 1072, and a third interface layer 1073 sequentially stacked on the sidewall surface of each stacked body. The first and

third interface layers

1071 and 1073 may be the same material, and the second interface layer 1072 may be different from the first interface layer 1071 in material. The gap fill layer 108 material includes, for example, a combination of one or more of silicon oxide, tetraethylorthosilicate, low-k dielectric (including organic or inorganic porous materials), and the like.

Referring to fig. 4E, in step S5, first, the sacrificial layer 105 may be removed by any suitable process, such as wet etching or dry etching, to form an opening 109, where the opening 109 is a strip-shaped groove extending along a first direction; then, a dielectric material is deposited on the inner surface of the opening 109, the top surface of the interface protection layer 107 and the top surface of the gap filling layer 108 through a suitable deposition process, and the dielectric material on the bottom surface of the opening 109, the top surface of the interface protection layer 107 and the top surface of the gap filling layer 108 is further removed through etching through a suitable sidewall etching process, so that a dielectric sidewall 110 is formed on the sidewall of the opening 109. The material of the dielectric sidewall 110 may be at least one of titanium nitride, tantalum nitride, silicon oxynitride, and the like, and may be a single-layer film or a multi-layer film stack structure. The dielectric sidewall 110 can prevent elements in the phase change memory layer filled in the opening 109 from diffusing outward and prevent external elements from diffusing into the phase change memory layer, and the dielectric sidewall also needs to have a suitable thickness to ensure that the line width of the phase change memory layer in the finally formed phase change memory cell meets the requirement.

Referring to fig. 4F, in step S6, a phase change memory layer 111 may be deposited on the surfaces of the opening 109, the dielectric sidewall 110, the interface protection layer 107 and the gap filling layer 108 by a suitable deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Metal Organic Chemical Vapor Deposition (MOCVD). The phase change memory layer 111 is deposited to a thickness at least to fill the opening 109. The material of the phase-change memory layer 111 may be any suitable phase-change material, and may include at least one of Ge-Sb-Te based phase-change material (also referred to as GST), Ge-Te based phase-change material, Ge-Sb based phase-change material, Si-Sb-Te based phase-change material, Sb based phase-change material, etc., a combination of two phase-change materials, a combination of three phase-change materials, or a combination of more phase-change materials. The Ge-Sb-Te based phase-change material is composed of three elements of Ge, Sb and Te, and can include but is not limited to Ge3Sb4Te8, Ge2Sb2Te5, Ge2Sb2Te4, GeSb2Te4 and the like, and the Ge-Te based phase-change material is composed of two elements of Ge and Te. The Ge-Sb based phase-change material consists of two elements of Ge and Sb, and the Si-Sb-Te based phase-change material consists of three elements of Si-, Sb and Te, and can comprise but is not limited to Si11Sb57Te32, Si18Sb52Te30, Si24Sb48Te28 and the like. Therefore, based on the fact that the phase change material contained in the phase change memory layer 111 may be a single phase or a combination of multiple phase change materials, the number of layers of the phase change memory layer 111 is not particularly limited, and may be a single layer or multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers or even more, the crystallization temperature and the threshold voltage of the phase change material in two adjacent layers may be different, and when the pulse voltage or the pulse current for the phase change corresponding to the phase change material with different crystallization temperature and threshold voltage is different, the pulse voltage or the pulse current for the phase change corresponding to the phase change material with different crystallization temperature and threshold voltage may be different, in this way, under a pulse voltage or a pulse current of a specific magnitude, the phase change material in all layers of the phase change memory layer 111 may be in the low resistance state, the phase change material in all layers of the phase change memory layer 111 may be in the high resistance state, or the phase change material in a part of the layers may be in the low resistance state, while another portion of the layer of phase change material is in a high resistance state.

After step S6, the method for manufacturing a three-dimensional phase change memory according to this embodiment further includes the following steps:

s7 (not shown), referring to fig. 4G, the phase change memory layer 111 and the rest of the stack (i.e. the lower structural layer 104 formed by the middle electrode layer 1043, the gate layer 1042 and the bottom electrode layer 1041) are respectively etched and etched along a second direction X intersecting the first direction Y until the bottom electrode layer 1041 is patterned again, thereby achieving the purpose of forming a plurality of phase change memory cells spaced apart from each other by a double pattern exposure technique, wherein the bottom electrode layer 1041 of each phase change memory cell is aligned with and electrically contacts the corresponding first contact 103.

S8 (not shown), referring to fig. 4H, a second wiring process is used to form a second interlayer dielectric layer 112, and a desired second contact 113 is formed in the second interlayer dielectric layer 112, and a plurality of second wirings 114 extending along the second direction X are formed on the second interlayer dielectric layer 112. The second interlayer dielectric layer covers the phase change memory layers 111, the gap filling layer 108, the interface protection layer 107, and other film layers, fills gaps (not shown) between adjacent phase change memory cells, and buries the top surfaces of the phase change memory layers 111 of the respective phase change memory cells. The second interlayer dielectric layer 112 may comprise any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectric, and the like, and the material used for filling the gap between adjacent phase change memory cells is preferably a low-k dielectric with a dielectric constant k less than 3, so as to reduce the parasitic effect introduced by the subsequently formed second wiring. The second interlayer dielectric layer 112 may be a single layer or a multi-layer film. The second interlayer dielectric layer 112 includes another interface protection layer (not shown, which may be the same material as the interface protection layer 107) covering sidewalls of the respective phase change memory cells, another gap filling layer (not shown, which may be the same material as the gap filling layer 108) filling gaps between adjacent phase change memory cells, and an inter-metal dielectric layer (not shown, which may be the same material as the first interlayer dielectric layer 101) covering a surface of the device including the another gap filling layer. Each of the second contacts 113 is aligned with and contacts the phase change memory layer 111 of a corresponding phase change memory cell, each of the second wires 114 is electrically connected to the corresponding phase change memory cell through the corresponding second contact 113, wherein, when the first wire 102 is a bit line, the second wires 114 are word lines, each of the second wires 114 is electrically connected to a plurality of second contacts 113 arranged in a row along the second direction X, that is, the phase change memory cells connected to the same second wire 114 through the second contacts 113 constitute a row of phase change memory cells. When the first wiring 102 is a word line, the second wiring 114 is a bit line.

In this embodiment, the second wiring process may be implemented by a single patterning technology (also referred to as a single patterning technology, a single photolithography technology, etc.), and a double patterning technology is not required, so that the process steps are few and the cost is low.

In this embodiment, the second wire 114 and the first wire 102 intersect perpendicularly, the contact array formed by the second contact 113 and the contact array formed by the first contact 103 are aligned, the cross sections of the second contact 113, the first contact 103 and the phase change memory cell along the X-Y plane are all circular, the radius of the cross-sectional circle of the second contact 113 and the first contact 103 is smaller than that of the cross-sectional circle of the phase change memory cell, that is, the size of the second contact 113 and the first contact 103 is smaller than that of the phase change memory cell.

As can be seen from fig. 5, since the phase change memory cell finally formed by the etching in the first direction in step S3 and the etching in the second direction in step S8 in this embodiment is a rectangular (or square) pillar, but the length and width of the pillar may be smaller than the line width of the first wire and the line width of the second wire, respectively, so that the phase change memory cell with a smaller size can be manufactured compared to the prior art. In addition, in the embodiment, the second contact 113 serves as a top electrode of the phase change memory cell, so that the electrical connection between the phase change memory cell and the second wire 114 is realized.

As an example, referring to fig. 4H, the process of implementing the second wiring process in step S8 includes:

first, another interface protection layer (not shown) is formed on the sidewall of the phase change memory cell.

Then, another gap filling layer is filled in the gap between the adjacent phase change memory cells and planarized to the top surface of the phase change memory layer 111.

Then, an inter-metal dielectric layer is covered on the gap filling layer 108, another gap filling layer, the phase change storage layer 111, and the like, and the inter-metal dielectric layer may be subjected to contact dot matrix lithography and etching by using a corresponding mask capable of defining a contact dot matrix, so as to form a plurality of second contact holes (not shown) in the inter-metal dielectric layer. The mask may be the same mask as the mask used to form the first contact in step S1, so as to reduce the cost of the mask and improve the alignment accuracy between the first contact and the second contact to be formed. The another interface protection layer, the another gap filling layer and the inter-metal dielectric layer constitute a second inter-layer dielectric layer 112.

Then, by a suitable process such as chemical vapor deposition, sputter deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, etc., the second contact holes are filled with a conductive material, and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP), which stops on the top surface of the inter-metal dielectric layer, to form second contacts 113 filled in the second contact holes. The material of the second contact 113 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, and the like.

Thereafter, several second wirings 114 extending in the second direction X may be formed on the inter-metal dielectric layer in a manner similar to the method of forming the first dielectric layer 1011 on the substrate 100 and forming the first wirings 102 in the first dielectric layer 1011.

It should be noted that, in another example of the present embodiment, the second wiring process may include a process of forming the second contact 113 through a contact hole process and a process of forming the second wiring 114 through a metal stripping process, and specifically, reference may be made to the description of another embodiment of the first wiring process, and details are not repeated here. In another example of this embodiment, the second wiring process may also be a dual damascene process, which includes: first, a trench for forming the second wire 114 is etched in the intermetal dielectric layer, and a second contact hole exposing the top surface of the corresponding phase change memory layer is further etched in the intermetal dielectric layer at the bottom of the trench, and then the second contact hole and the trench are filled together to form the second contact 113 and the second wire 114 together.

Optionally, after step S6 and before step S7 is performed, or after step S7 and before step S8 is performed, a top surface of the phase change memory reservoir layer 111 is planarized by a Chemical Mechanical Polishing (CMP) process until the top surface of the gap filling layer 108 is exposed, so as to provide a planar process surface for the subsequent second wiring process. After the top surface of the phase change memory layer 111 is planarized, the structure of the combination of the dielectric sidewall 110 and the phase change memory layer 111 is aligned with the bottom electrode layer 1041.

It should be understood that, in the above embodiments, only one layer of phase change memory cells and the fabrication of the electrically connected word lines and bit lines thereof are shown, when the architecture of the three-dimensional phase change memory required to be fabricated in the present invention includes two stacked layers of phase change memory cells, then according to the fabrication method in the above embodiments, a corresponding contact array is fabricated above the second wiring, then the upper layer of phase change memory cells is fabricated above the contact array, and then another contact array and a third wiring electrically connected to the another contact array are fabricated on the upper layer of phase change memory cells, the second wiring and the third wiring intersect, and the third wiring may be parallel to the first wiring; alternatively, according to the manufacturing method in the above embodiment, a lower-layer phase-change memory cell and a fourth wiring electrically connected to the lower-layer phase-change memory cell may be manufactured under the first wiring, the fourth wiring connects to an electrode on the bottom of the lower-layer phase-change memory cell through a corresponding contact in a contact array, the first wiring connects to an electrode on the top of the lower-layer phase-change memory cell through a corresponding contact in another contact array, the fourth wiring intersects with the first wiring, and the fourth wiring may be parallel to the second wiring.

Therefore, when the architecture of the three-dimensional phase-change memory required to be fabricated by the present invention includes three, four or more layers of phase-change memory cells stacked along the Z direction perpendicular to the direction X, Y at the same time, the sequential structure of wiring-contact-phase-change memory cell-contact-wiring … in the above embodiment may be repeated along the Z direction until the fabrication of the phase-change memory cells of all layers and their electrically connected word lines and bit lines is completed.

The manufacturing method of the three-dimensional phase change memory of the embodiment adopts a first wiring process to form a first wiring used as a bit line or a word line and a first contact on the first wiring on a substrate, then utilizes the replacement of a sacrificial layer and the limiting and shrinking action of a dielectric side wall to manufacture a phase change memory cell with a bottom electrode electrically contacted with the first contact, and then further utilizes a second wiring process to manufacture a second wiring and a second contact, so that the manufacturing method ensures that the correlation among the patterning treatments of the bit line, the word line and the phase change memory cell does not exist in the existing double patterning technology, the shape and the size of the phase change memory cell do not depend on the overlapping condition of the intersection of the word line and the bit line completely, the dielectric side wall can be utilized to limit the line width of a phase change memory layer of the phase change memory cell, and the size of the phase change memory cell can be smaller, this can contribute to further miniaturization of the overall size of the phase change memory and further improvement of the memory density. And the second wiring (for example, the word line) can be electrically contacted with the top electrode of the phase change memory unit through the second contact, and the first wiring (for example, the bit line) can be electrically contacted with the bottom electrode of the phase change memory unit through the first contact, so that parasitic effects (including parasitic resistance R, parasitic capacitance C, RC delay effect and the like) caused by the word line and the bit line can be reduced, the crosstalk problem between adjacent memory units is improved, and the programming current and the power supply requirement of the phase change memory are further reduced.

In addition, since the gate layer 1042 and other film layers are etched in the Y direction under the protection of the sacrificial layer, and then the phase change memory layer 111 is used to replace the sacrificial layer 105, compared with the double pattern exposure technology in the prior art, the scheme of the embodiment reduces the process of etching the phase change memory layer 111 and the gate layer 1042 at a time, so that the problem of cross contamination between the phase change memory layer and the gate layer can be improved, and the respective performances of the phase change memory layer and the gate layer are guaranteed.

Second embodiment

Referring to fig. 3, fig. 4A to fig. 4H and fig. 6, the present embodiment also provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S8. The manufacturing method of the three-dimensional phase change memory of the present embodiment differs from the first embodiment in that in step S3, the stacked layers formed of the bottom electrode layer 1041 to the sacrificial layer 105 are patterned by a single exposure technique or a multiple pattern exposure technique to directly form an island-shaped stacked body corresponding to each phase change memory cell, whereby after step S6, the execution of step S7 is omitted.

Specifically, in step S3, when a single exposure technique (also called single patterning technique, single lithography technique, etc.) is adopted, the sacrificial layer 105 may be subjected to lithography and corresponding etching by a mask having a pattern corresponding to each phase change memory cell, so as to form a pattern for defining each phase change memory cell in the sacrificial layer 105. When a multiple pattern exposure technology is adopted, the multiple pattern exposure technology can be a lithography-etching-lithography-etching (Litho-Etch-Litho-Etch, LELE) technology, an original layer of lithography pattern is split on two or more masks, and the superposition of pattern density in the sacrifice layer 105 is realized; the multiple pattern exposure technique may also be a lithography-cure-lithography-Etch (LFLE) technique, utilizing two lithography steps and one etching step to achieve a doubling of the pattern density in the sacrificial layer 105; the multiple pattern exposure technique may also be a Self-Aligned Double Patterning (SADP) technique, in which an axis pattern is formed by a single photolithography and etching process, then a sidewall pattern is formed on the sidewall by an atomic layer deposition and etching process, the axis layer (i.e., sacrificial layer) is removed, and a sacrificial layer 105 pattern in the form of a sidewall with a halved size (pitch) is formed. Therefore, no matter what kind of lithography is used in step S3 of the embodiment, it is finally required to first pattern the sacrificial layer 105 by using corresponding lithography and etching processes, and make the pattern in the sacrificial layer 105 correspond to the phase-change memory cells and the array formed by the phase-change memory cells, the size and shape of each pattern meet the manufacturing requirements of the size and shape of each phase-change memory cell, and then etch the middle electrode layer 1043 to the lower structure layer 104 of the bottom electrode layer 1041 by using the sacrificial layer 105 as a mask to form an island-shaped stacked body corresponding to each phase-change memory cell, with a gap between adjacent stacked bodies, and the bottom electrode layer in each stacked body is aligned and electrically contacted with the corresponding first contact to serve as the bottom electrode of the phase-change memory cell to be formed. When a single exposure technique is used to form the pattern for defining each phase-change memory cell in the sacrificial layer 105, the process steps are fewer and the cost is lower than that of a double-pattern exposure technique or a multiple-pattern exposure processing technique, but the limit size of the phase-change memory cell formed by the method is limited by the limit size of the single exposure technique.

After step S6, the top surface of the phase change memory layer 111 is planarized until the top surface of the gap filling layer 108 is exposed; then, step S8 is executed, a second interlayer dielectric layer 112 is formed on the phase change memory layer 111 and the gap filling layer 108 by using a second wiring process, a desired second contact 113 is formed in the second interlayer dielectric layer 112, and a plurality of second wirings 114 extending along the second direction X are formed on the second interlayer dielectric layer 112, each second contact 113 is aligned with and contacts the phase change memory layer 111 of a corresponding phase change memory cell, each second wiring 114 is electrically connected to a corresponding phase change memory cell through a corresponding second contact 113, wherein when the first wiring 102 is a bit line, the second wiring 114 is a word line, and when the first wiring 102 is a word line, the second wiring 114 is a bit line.

It should be understood that steps S1 to S2, steps S4 to S6 and step S8 in this embodiment are all the same as those in the first embodiment, and reference may be made to the corresponding description above, which is not repeated herein.

Referring to fig. 6, since the intermediate electrode layer to the bottom electrode layer are directly etched in step S3 of the present embodiment to form an island structure corresponding to the phase change memory cell, the finally formed phase change memory cell can be a cylinder, and the diameters of the finally formed phase change memory cell are respectively smaller than the line width of the first wire 102 and the line width of the second wire 114, thereby enabling the fabrication of a smaller phase change memory cell compared to the first embodiment. The bit line, the phase change memory unit and the word line are manufactured separately and can be manufactured by adopting a single patterning processing technology, so that the process complexity and cost caused by manufacturing the word line, the phase change memory unit and the bit line by using a double patterning technology in the prior art can be avoided, and the effects of simplifying process steps and reducing cost are achieved.

In addition, since the middle electrode layer to the bottom electrode layer are directly etched in step S3 of this embodiment to form an island structure corresponding to the phase change memory cell, the phase change memory layer 111 and the gate layer 1042 can be completely separated from each other without etching together, so that the problem of cross contamination between the phase change memory layer and the gate layer can be effectively solved, and the respective performances of the phase change memory layer and the gate layer can be guaranteed.

Third embodiment

Referring to fig. 3, fig. 4A to 4H, and fig. 5 to 8, the present embodiment provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6, and further includes step S7 or steps S7 to S8. The difference from the first embodiment and the second embodiment is that the substrate 100 provided in step S1 has a memory area I mainly used for forming a phase change memory array to store data and a peripheral area II mainly used for forming a peripheral circuit to realize functional control of operations (read operation, write operation, etc.) of the phase change memory array, and the first wiring process in step S1 and the second wiring process in step S8 of the present embodiment and the manufacturing process of the electrical connection structure for realizing electrical connection of the peripheral circuit of the peripheral area II and the word line or the bit line are not separately realized but embedded in the manufacturing process of the electrical connection structure for realizing electrical connection of the peripheral circuit of the peripheral area II and the word line or the bit line.

Specifically, referring to fig. 7 and 8, in the method for manufacturing a three-dimensional memory provided in this embodiment, the substrate 100 provided in step S1 has a storage region I and a peripheral region II located at the periphery of the storage region I, and a required peripheral circuit (not shown) for realizing functional control of operations (read operation, write operation, etc.) of the phase-change memory cell is formed in the substrate of the peripheral region II. The manufacturing method of the present embodiment further includes: a multilayer metal interconnection structure is formed in the periphery region II above the substrate 100 through a multilayer metal interconnection process, wherein the first wiring process in step S1 is a formation process of a certain layer of metal wiring in the multilayer metal interconnection process, and the second wiring process in step S8 is a formation process of another layer of metal wiring in the multilayer metal interconnection process, so that the first wiring 102 and the one layer of metal wiring in the multilayer metal interconnection structure are the same layer of metal, and the second wiring 114 and the other layer of metal wiring in the multilayer metal interconnection structure are the same layer of metal. At this time, the manufacture of the phase change memory can be embedded in the manufacturing process of the peripheral integrated circuit. When the multilayer metal interconnection process is a copper interconnection process, the first wiring 102 and the second wiring 114 may be both copper, and the first contact 102 and the second contact 113 may be both tungsten plugs.

As an example, in step S1 of the present embodiment, the first-layer word line peripheral circuit wiring 102 'is formed in the peripheral region II while the first wiring 102 is formed as the bit line in the memory region I by the first wiring process, and the peripheral contact 103' which is located on the first-layer word line peripheral circuit wiring 102 'and electrically contacts the first-layer word line peripheral circuit wiring 102' is also formed in the peripheral region II while the first contact 103 is formed in the memory region I; simultaneously with the formation of the second contact 113 in the memory area I by the second wiring process in step S8, a peripheral contact 113 'that is located on the peripheral contact 103' and is in electrical contact with the peripheral contact 103 'is also formed in the peripheral area II, and simultaneously with the formation of the second wiring 114 in the memory area I, a second-layer word line peripheral circuit wiring 114' that is located on the peripheral contact 113 'and is in electrical contact with the peripheral contact 113' is also formed in the peripheral area II, whereby the peripheral contacts 103 'and 113' form word line contact plugs (i.e., second contact plugs), and the first-layer word line peripheral circuit wiring 102 ', the peripheral contact 103' and 113 ', and the second-layer word line peripheral circuit wiring 114' are sequentially connected to form an electrical connection structure for electrically connecting the second wiring (i.e., word line) 114 and the corresponding peripheral circuit in the peripheral area II.

It should be understood that the first layer of word line peripheral circuit wiring 102 ' is electrically isolated from the first wiring 102, the second layer of word line peripheral circuit wiring 114 ' may be integrated with the second wiring 114, that is, the second layer of word line peripheral circuit wiring 114 ' is a portion of the second wiring 114 extending into the peripheral region II, the second layer of word line peripheral circuit wiring 114 ' may also be separated from the second wiring 114, and the second layer of word line peripheral circuit wiring 114 ' may also be electrically connected to the second wiring 114 only through a subsequent wiring process or a metal interconnection process.

Likewise, when the first wiring 102 is led out outward from the top surface of the peripheral region II, in step S1, the first wiring 102 is formed as a bit line in the storage region I by the first wiring process, while a first-layer bit line peripheral circuit wiring (not shown) is formed in the peripheral region II, and a first peripheral contact (not shown) which is located on the first-layer bit line peripheral circuit wiring and electrically contacts the first-layer bit line peripheral circuit wiring is also formed in the peripheral region II while the first contact 103 is formed in the storage region I; while the second contact 113 is formed in the storage area I by the second wiring process in step S8, a second peripheral contact (not shown) is also formed in peripheral region II over and in electrical contact with the first peripheral contact, at the same time as the second wiring 114 is formed in the memory area I, a second level bitline peripheral circuit wiring (not shown) which is located on and electrically contacts the second peripheral contact is also formed in the peripheral area II, thus, the first peripheral contact and the second peripheral contact form a bit line contact plug (i.e., a first contact plug), and the first layer of bit line peripheral circuit wiring, the first peripheral contact and the second peripheral contact, and the second layer of bit line peripheral wiring are sequentially connected to form an electrical connection structure for electrically connecting the first wiring (i.e., word line) 102 and the corresponding peripheral circuit in the peripheral region II.

It should also be understood that the second level bitline peripheral circuit wiring is electrically isolated from the second wiring 114. The first layer of bit line peripheral circuit wiring may be integrated with the first wiring 102, that is, the first layer of bit line peripheral circuit wiring is a portion of the first wiring 102 extending into the peripheral region II, the first layer of bit line peripheral circuit wiring may also be electrically insulated and isolated from the first wiring 102, and the first layer of word line peripheral circuit wiring and the first wiring 102 may be electrically connected only by a subsequent wiring process or a metal interconnection process, that is, by an electrical connection structure including the second layer of bit line peripheral circuit wiring.

That is, in the present embodiment, the substrate 100 has the storage region I and the peripheral region II located at the periphery of the storage region I, the first wiring 102 and the second wiring 114 both extend from the storage region I into the peripheral region II, and the manufacturing method of the present embodiment further includes: while the first wiring process and the second wiring process are respectively performed in the storage area I, corresponding electrical connection structures are also formed in the peripheral area II together, so that the manufacturing of the second contact 113 is completed in the storage area I, and the manufacturing of the first contact plug (contact) and the second contact plug (contact) is completed in the peripheral area II, so that the second wiring 114 extending into the peripheral area II is electrically connected with the second contact plug, and the first wiring 102 extending into the peripheral area II is electrically connected with the first contact plug.

It should be understood that steps S1 to S2, steps S4 to S6, and step S8 (or steps S7 to S8) of the present embodiment are all the same as those of the first embodiment or the second embodiment, and reference may be made to the corresponding description above, which is not repeated herein.

Referring to fig. 8, in the method for manufacturing a three-dimensional phase-change memory of this embodiment, the contact plugs (contacts) required by the word lines and the bit lines can be uniformly distributed in the peripheral region II, that is, the second contact plug CT1 required by the second wire 114, the first contact plug CT2 required by the first wire 102, and the third contact plug CT3 required by the third wire (for example, the top bit line TBL) are uniformly distributed in the peripheral region II, so that the problem that the memory area occupied by the word line contact plugs and the bit line contact plugs in the prior art can be avoided, thereby facilitating further shrinking the overall size of the phase-change memory and further improving the memory density.

In some examples of the present embodiment, the peripheral circuits in the peripheral region II are digital, analog and/or mixed signal circuits formed in advance in the substrate for the operation of the phase change memory array, and these signal circuits include control logic elements, data buffers, decoders (also referred to as decoders), drivers, read/write circuits, and the like, and these peripheral circuits need to be electrically connected to the word lines and the bit lines finally through a multi-layer metal interconnection structure formed in the substrate and an electrical connection structure such as contact plugs formed in the peripheral region II and located at the periphery of the memory region.

Fourth embodiment

Referring to fig. 3, fig. 4A to fig. 4G, and fig. 9 to fig. 10, the present embodiment also provides a method for manufacturing a three-dimensional phase change memory, which includes steps S1 to S6 and step S7. The manufacturing method of the three-dimensional phase change memory of the present embodiment is different from the first embodiment in that after step S6 is performed and before step S7 is performed, the top surface of the phase change memory layer 111 deposited in step S6 is planarized until the top surface of the gap filling layer 108 is exposed, and then a top electrode layer and a second wiring layer are sequentially deposited on the phase change memory layer 111 and the gap filling layer 108. In step S7, performing photolithography and etching on the second wiring layer, the top electrode layer, the phase change memory layer 111 and the remaining stacked body (i.e. the middle electrode layer 1043 to the lower structural layer 104 formed by the bottom electrode layer 1041) along the second direction X until the bottom electrode layer 1041 is patterned again to form a plurality of phase change memory cells spaced apart from each other and a plurality of top electrode lines 115 and second wirings 114 extending along the second direction X, wherein the bottom electrode layer 1041 of each phase change memory cell is aligned with and electrically contacted to the corresponding first contact 103, each second wiring 114 is electrically connected to a plurality of phase change memory cells (i.e. phase change memory cells in the same row) through the top electrode line 115 aligned therebelow, and when the first wiring 102 is a bit line, the second wiring 114 is a word line, and the first wiring 102 is a word line, the second wiring 114 is a bit line.

The material of the top electrode lines 115 may be the same as or different from the material of the middle electrode layer 1043 or the bottom electrode layer 1041. As an example, the materials of the top electrode lines 115, the middle electrode layer 1043 and the bottom electrode layer 1041 are all amorphous carbon.

It should be understood that steps S1 to S6 in this embodiment are the same as those in the first embodiment, and reference may be made to the corresponding description above, which is not repeated herein.

As can be seen from fig. 10, in this embodiment, since the patterning process of the stack layer in the first direction is not performed together with the manufacturing of the first wire, and the patterning process in the second direction is performed together with the manufacturing of the second wire, one critical dimension (e.g., width) of the formed phase-change memory cell is limited by the line width of the second wire, but another critical dimension (e.g., length) of the phase-change memory cell can be flexibly designed as required, so that the shape and size of the phase-change memory cell are not completely dependent on the overlapping condition at the intersection of the word line and the bit line, and the line width of the phase-change memory layer of the phase-change memory cell can be limited by using the dielectric sidewall, so that a smaller phase-change memory cell size can be realized, which may be beneficial to further shrinking the overall size of the phase-change memory and further improving the storage density. Furthermore, the method for manufacturing the three-dimensional phase change memory of the present embodiment, which performs patterning processing on the second wiring layer, the top electrode layer, the phase change memory layer, and the remaining stacked body together in the second direction after step S6, can further reduce the process complexity and cost for manufacturing the second wiring (word line or bit line).

Fifth embodiment

Referring to fig. 3 and 4A to 4G, and fig. 9 and 11, the present embodiment also provides a method for manufacturing a three-dimensional phase change memory, which includes steps S1 to S6 and step S7. The manufacturing method of the three-dimensional phase change memory of the present embodiment is different from the second embodiment in that after step S6 is performed, the top surface of the phase change memory layer 111 deposited in step S6 is planarized until the top surface of the gap filling layer 108 is exposed, then a top electrode layer and a second wiring layer are sequentially deposited on the phase change memory layer 111 and the gap filling layer 108, and then the second wiring layer and the top electrode layer are respectively patterned and etched along the second direction X to form a plurality of top electrode lines 115 and second wirings 114 extending along the second direction X, the bottom electrode layer 1041 of each phase change memory cell is aligned with and electrically contacted with a corresponding first contact 103, each second wiring 114 is electrically connected with a plurality of phase change memory cells (i.e. phase change memory cells in the same row) through the top electrode line 115 aligned therebelow, wherein, when the first wiring 102 is a bit line, when the second wiring 114 is a word line and the first wiring 102 is a word line, the second wiring 114 is a bit line.

As can be seen from fig. 11, since the patterning process of the phase-change memory cell in this embodiment is not related to the first wiring and the second wiring, compared with the solution of the fourth embodiment, a phase-change memory cell with a smaller size, for example, a cylindrical shape, can be realized, which is beneficial to further shrinking the overall size of the phase-change memory and further improving the storage density. In addition, in the manufacturing method of the three-dimensional phase change memory of the embodiment, the second wire is simultaneously connected with the row of phase change memory cells through the top electrode line, which is beneficial to improving the control capability of the second wire on the row of phase change memory cells and simplifying the complexity and cost of the manufacturing process for electrically connecting the second wire and the row of phase change memory cells compared with the scheme of the second embodiment.

Sixth embodiment

Referring to fig. 3, fig. 4A to fig. 4G and fig. 12, the present embodiment provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S7. The difference from the fourth and fifth embodiments is that the substrate 100 provided in step S1 has a memory area I and a peripheral area II, the memory area I is mainly used for forming a phase change memory array to store data, the peripheral area II is mainly used for forming a peripheral circuit to implement functional control of the operation (read operation, write operation, etc.) of the phase change memory array, the first wiring process in step S1 of the present embodiment is also implemented in a manufacturing process (for example, a multilayer metal interconnection process) of an electrical connection structure for implementing electrical connection between the peripheral circuit of the peripheral area II and word lines or bit lines, and before depositing the top electrode layer and the second wiring layer, a peripheral contact 113 ' is formed in the peripheral area II by the manufacturing process of the electrical connection structure, and two layers of peripheral wirings (i.e., 115 ' and 114 ' in fig. 12) are formed in the memory area I while forming the top electrode line 115 and the second wiring 114 in the peripheral area II.

The process in which the peripheral contact 113 ' and the two-layer peripheral wiring (i.e., 115 ' and 114 ' in fig. 12) are formed is similar to the process in which the peripheral contact 113 ' and the second-layer word line peripheral circuit wiring 114 ' are formed in the third embodiment, and reference may be made to the above description, and will not be described in detail here.

With reference to fig. 8, in the method for manufacturing a three-dimensional phase-change memory of this embodiment, electrical connection structures such as contact plugs (contacts) required by the word lines and the bit lines can be arranged in the peripheral region II, that is, the second contact plug CT1 required by the second wire 114, the first contact plug CT2 required by the first wire 102, and the third contact plug CT3 required by the third wire (for example, the top bit line TBL) are uniformly arranged in the peripheral region II, so that the problem that the memory area occupied by the word line contact plugs and the bit line contact plugs in the prior art can be avoided, thereby facilitating further shrinking the overall size of the phase-change memory and further improving the storage density.

Seventh embodiment

Based on the same inventive concept, the present embodiment further provides a three-dimensional phase change memory, which is preferably manufactured by using the manufacturing method of the three-dimensional phase change memory according to any of the above embodiments of the present invention, and of course, a person skilled in the art may also use corresponding process steps to replace corresponding process steps in the manufacturing method of the three-dimensional phase change memory according to the present invention, so as to manufacture the same structure.

Referring to fig. 3 to 12, the three-dimensional phase change memory of the present embodiment includes:

a first interlayer dielectric layer 101, wherein a plurality of first wirings 102 extending along a first direction Y and a plurality of first contacts 103 located on each first wiring 102 are formed in the first interlayer dielectric layer 101;

a plurality of phase change memory cells which are spaced apart from each other are formed on the first interlayer dielectric layer 101, each phase change memory cell has a bottom electrode layer 1041 and a phase change memory layer 111 which are sequentially stacked, the bottom electrode layer 1041 is aligned with and electrically contacted with the corresponding first contact 103, a dielectric side wall 110 is formed on the side wall of the phase change memory layer 111, and the combined structure of the dielectric side wall 110 and the phase change memory layer 111 is aligned with the bottom electrode layer 1041;

a gap filling layer 108 filling gaps between adjacent phase change memory cells;

a plurality of second wirings 114 extending along a second direction X intersecting the first direction Y, the second wirings 114 being formed above the phase change memory cells and the gap filling layer 108, and each of the second wirings 114 being electrically connected to a corresponding phase change memory cell through a corresponding second contact 113 or a top electrode line 115 extending along the second direction X;

the first wiring 102 is a bit line and the second wiring 114 is a word line, or the first wiring 102 is a word line and the second wiring 114 is a bit line.

Alternatively, the materials of the first wire 102 and the second wire 114 respectively comprise at least one of Cu, Al, Pt, Au, and Ag, and the materials of the second contact 113 and the first contact 103 respectively comprise at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, and metal silicide.

Optionally, the three-dimensional phase change memory of the embodiment further includes a substrate 100, wherein a first interlayer dielectric layer 101 and a first wire 102 are formed on the substrate 100, the substrate 100 has a storage region I and a peripheral region II located at the periphery of the storage region I, and an electrical connection structure (i.e., 102 ', 103' in fig. 6 and 12) formed together with the first wire 102 and the first contact 103 is formed in the peripheral region II.

It should be understood that the three-dimensional phase change memory of this embodiment may further include other film layers, and the specific structures of these film layers may refer to the description of the corresponding film layers in the above manufacturing method of the three-dimensional phase change memory, and are not described herein again.

The shape and size of the phase change memory unit of the three-dimensional phase change memory provided by the embodiment do not depend on the overlapping condition at the intersection of the word line and the bit line, so that the three-dimensional phase change memory is beneficial to realizing smaller device size and higher storage density, improving the parasitic effect introduced by the word line and the bit line and reducing the programming current and power supply requirements of the phase change memory.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, to the inventive concepts set forth herein without departing from the scope of the inventive concepts. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of protection of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical relationship or order relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a three-dimensional phase change memory, comprising:

2. The method of manufacturing of claim 1, wherein the step of forming the first interlayer dielectric layer, the first wire, and the first contact using a first wire process comprises:

forming first wirings filled in the first trenches;

and forming first contacts filled in the first contact holes.

3. The manufacturing method according to claim 1, characterized in that the stack of layers is subjected to a respective lithography and etching along the first direction until the bottom electrode layer is patterned to form several stacks spaced apart from each other and extending along the first direction;

performing corresponding photolithography and etching on the phase change memory layer and the remaining stacked body along a second direction intersecting the first direction until the bottom electrode layer is patterned again to form a plurality of phase change memory cells spaced apart from each other by a double pattern exposure technique, the bottom electrode layer of each phase change memory cell being aligned with and in electrical contact with the corresponding first contact;

forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills gaps between adjacent phase change memory units and buries the top surfaces of the phase change memory layers of the phase change memory units;

4. The method according to claim 3, wherein after depositing the phase-change memory layer on the surfaces of the opening, the dielectric sidewall and the gap filling layer, and before or after performing corresponding photolithography and etching on the phase-change memory layer and the remaining stacked body along the second direction to form a plurality of phase-change memory cells spaced apart from each other, the top surface of the phase-change memory layer is planarized until the top surface of the gap filling layer is exposed.

5. The manufacturing method according to claim 1, characterized in that the stack of layers is subjected to a respective lithography and etching along the first direction until the bottom electrode layer is patterned to form several stacks spaced apart from each other and extending along the first direction;

and carrying out corresponding photoetching and etching on the second wiring layer, the top electrode layer, the phase change storage layer and the rest stacked body along the second direction until the bottom electrode layer is patterned again so as to form a plurality of phase change storage units which are spaced from each other and a plurality of top electrode wires and second wirings which extend along the second direction through a double-pattern exposure technology, wherein the bottom electrode layer of each phase change storage unit is aligned with and electrically contacted with the corresponding first contact, and each second wiring is electrically connected with a plurality of phase change storage units through the top electrode wires aligned below the second wiring, when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

6. The method of manufacturing according to claim 1, wherein the step of performing corresponding lithography and etching on the stack of layers until the bottom electrode layer is patterned to form a number of mutually spaced stacks comprises:

and etching the bottom electrode layer by taking the sacrificial layer as a mask to form stacked bodies corresponding to the phase change storage units, wherein gaps are formed between every two adjacent stacked bodies, and the bottom electrode layer in each stacked body is aligned to and electrically contacted with the corresponding first contact to be used as a bottom electrode of the phase change storage unit to be formed.

7. The method of claim 6, wherein after depositing a phase change memory layer on the surfaces of the opening, the dielectric sidewall, and the gap fill layer, the method further comprises:

forming a second interlayer dielectric layer on the phase change memory layer and the gap filling layer by adopting a second wiring process, forming a required second contact in the second interlayer dielectric layer, and forming a plurality of second wirings extending along the second direction on the second interlayer dielectric layer, wherein each second contact is aligned with and contacts with the corresponding phase change memory layer of the phase change memory unit, and each second wiring is electrically connected with the corresponding phase change memory unit through the corresponding second contact, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

8. The manufacturing method according to any one of claims 1 to 7, wherein an interface protection layer is formed on a sidewall of the stack before forming a gap filling layer in a gap between adjacent stacks.

9. The manufacturing method according to any one of claims 1 to 7, wherein the first interlayer dielectric layer and the first wiring are formed over a substrate having a storage region and a peripheral region located at a periphery of the storage region, the first wiring extending from the storage region into the peripheral region, and the manufacturing method further comprises: and simultaneously forming corresponding electric connection structures in the peripheral area while the first wiring process is carried out in the storage area.

10. A three-dimensional phase change memory, comprising:

the first interlayer dielectric layer is provided with a plurality of first wirings extending along a first direction and a plurality of first contacts positioned on each first wiring;

the phase change memory units are formed on the first interlayer dielectric layer and are sequentially stacked, the bottom electrode layer is aligned to and electrically contacted with the corresponding first contact, a medium side wall is formed on the side wall of the phase change memory layer, and the combined structure of the medium side wall and the phase change memory layer is aligned to the bottom electrode layer;

11. The three-dimensional phase change memory according to claim 9, further comprising a substrate on which the first interlayer dielectric layer and the first wiring are formed, the substrate having a storage region and a peripheral region located at a periphery of the storage region, the peripheral region having an electrical connection structure formed therein together with the first wiring and the first contact.