CN113871414A

CN113871414A - Three-dimensional phase change memory and manufacturing method thereof

Info

Publication number: CN113871414A
Application number: CN202111263727.5A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2021-12-31

Abstract

The invention provides a three-dimensional phase change memory and a manufacturing method thereof, which manufacture word lines and bit lines required by each layer of phase change memory units through corresponding wiring processes, finish the manufacturing of the phase change memory units after first wiring is formed and before second wiring is formed, and enable the word lines and the bit lines to be respectively and electrically connected with corresponding contacts and corresponding electrodes of the phase change memory units, so that the shape and the size of the phase change memory units are not completely dependent on the overlapping condition of the cross points of the word lines and the bit lines, the realization of smaller device size and higher memory density is facilitated, the parasitic effect introduced by the word lines and the bit lines is improved, and the programming current and the power supply requirement of the phase change memory are reduced. And when the corresponding single exposure technology is respectively adopted to manufacture the bit line, the phase change memory unit and the word line, the process complexity and cost brought by the double patterning technology used for manufacturing the word line and the bit line in the prior art can be avoided.

Description

Three-dimensional phase change memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional phase change memory and a manufacturing method thereof.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and costly. Thus, the storage density of the planar memory cell is close to the upper limit, and a three-dimensional (3D) memory architecture is developed to solve the problem of density limitation in the planar memory cell.

The architecture of a currently mainstream three-dimensional Phase Change Memory (3D PCM) may include a single-layer Phase Change Memory cell (PCM cell), a two-layer stacked Phase Change Memory cell, or a four-layer stacked Phase Change Memory cell, and each layer of Phase Change Memory cell is generally formed at an intersection of a Word Line (WL) and a Bit Line (BL) perpendicular to each other in a self-aligned manner, and the shape and size of each layer of Phase Change Memory cell completely depend on an overlapping condition at the intersection of the word line and the bit line, so that the Phase Change Memory cell generally has a vertical square column shape as a whole.

Although the architecture of the three-dimensional phase change memory can break through the density limitation in the planar phase change memory, the shape and size of the phase change memory cell are completely dependent on the overlapping condition at the intersection of the word line and the bit line, and the phase change memory cell is in a vertical square column shape, which is not favorable for further shrinking the device size, and this is one of the technical problems to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a three-dimensional phase change memory and a manufacturing method thereof, which can be beneficial to realizing a memory device with smaller size and higher memory density.

In order to achieve the above object, the present invention provides a method for manufacturing a three-dimensional phase change memory, comprising the steps of:

providing a substrate, and forming a first interlayer dielectric layer by adopting a first wiring process, wherein a plurality of first wirings and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer;

forming a plurality of phase change memory units which are spaced from each other on the first interlayer dielectric layer, wherein each phase change memory unit is provided with a bottom electrode and a top electrode, and the bottom electrodes are aligned with and electrically contacted with the corresponding first contacts;

forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills gaps between adjacent phase change memory cells and buries the tops of the phase change memory cells;

and forming a required second contact in the second interlayer dielectric layer by adopting a second wiring process, and forming a plurality of second wirings on the second interlayer dielectric layer, wherein each second contact is aligned with and electrically contacted with the top electrode of the corresponding phase change memory unit, and each second wiring is electrically connected with the top electrode of the corresponding phase change memory unit through the corresponding second contact, wherein the first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

Optionally, the step of forming the first interlayer dielectric layer, the first wiring and the first contact by using a first wiring process includes:

forming a first dielectric layer on a substrate, and photoetching and etching the first dielectric layer to form a plurality of first grooves extending along a first direction;

forming first wirings filled in the first trenches;

covering a second dielectric layer on the first dielectric layer and the first wirings, and photoetching and etching the second dielectric layer to form a plurality of first contact holes on each first wiring, wherein the first dielectric layer and the second dielectric layer form the first interlayer dielectric layer;

and forming first contacts filled in the first contact holes.

Optionally, the step of forming a plurality of phase change memory cells spaced apart from each other on the first interlayer dielectric layer includes:

forming a phase change storage stacking layer on the first interlayer dielectric layer and the first contact, wherein the phase change storage stacking layer comprises a bottom electrode layer, a phase change storage layer and a top electrode layer which are sequentially stacked from bottom to top;

and correspondingly photoetching and etching the phase change storage stack layer by adopting a single exposure technology or a multiple pattern exposure technology until the bottom electrode layer is patterned into bottom electrodes which are spaced from each other so as to form a plurality of phase change storage units which are spaced from each other.

Optionally, a bottom electrode layer, a gate layer, an intermediate electrode layer, a phase change memory layer, a top electrode layer and a hard mask layer are sequentially stacked on the first interlayer dielectric layer and the first contact to form the phase change memory stack layer; the steps of photoetching and etching the phase change storage stack layer by adopting a single exposure technology or a multiple pattern exposure technology comprise:

carrying out corresponding photoetching and etching on the hard mask layer by adopting a single exposure technology or a multiple pattern exposure technology so as to form a pattern for defining each phase change memory cell in the hard mask layer;

sequentially etching the top electrode layer and the phase change storage layer by taking the hard mask layer as a mask, and stopping on the top surface of the middle electrode layer to form stacked bodies corresponding to the phase change storage units, wherein gaps are formed between every two adjacent stacked bodies;

forming a first interface protection layer on a sidewall of the stack;

and etching the first interface protection layer, the middle electrode layer, the gate layer and the bottom electrode layer downwards along the gap, and stopping on the top surface of the first interlayer dielectric layer to form each phase change memory unit.

Optionally, the step of forming the second interlayer dielectric layer includes:

forming a second interface protection layer on the side wall of each phase change memory unit;

depositing a gap filling layer in a gap between adjacent phase change memory cells, and performing chemical mechanical polishing on the top of the gap filling layer until the top surface of the top electrode of each phase change memory cell is exposed;

depositing a third dielectric layer on the gap filling layer and the top electrode to form the second interlayer dielectric layer, wherein the second interlayer dielectric layer comprises the second interface protection layer, the gap filling layer and the third dielectric layer.

Optionally, the step of forming the second contact and the second wiring by using a second wiring process includes:

photoetching and etching the third dielectric layer to form a second contact hole exposing part or all of the top surface of the corresponding top electrode;

forming second contacts filled in the second contact holes;

and forming the second wiring on the third dielectric layer.

Optionally, the first interlayer dielectric layer and the first wire are formed on a substrate, the substrate has a storage region and a peripheral region located at the periphery of the storage region, and the manufacturing method further includes: forming a multilayer metal interconnection structure in the peripheral area through a multilayer metal interconnection process, wherein the first wiring process is a forming process of a certain layer of metal wiring in the multilayer metal interconnection process, and the second wiring process is a forming process of another layer of metal wiring in the multilayer metal interconnection process, so that the first wiring and the metal wiring in the layer of metal interconnection structure are the same layer of metal, and the second wiring and the metal wiring in the layer of metal interconnection structure are the same layer of metal;

and/or the first interlayer dielectric layer and the first wiring are formed on a substrate having a storage region and a peripheral region located at the periphery of the storage region, the first wiring and the second wiring both extending from the storage region into the peripheral region, and the manufacturing method further includes: and simultaneously forming corresponding electric connection structures in the peripheral area while respectively performing the first wiring process and the second wiring process on the storage area, so that the manufacture of a first contact plug and a second contact plug is completed in the peripheral area while the manufacture of the second contact is completed in the storage area, so that the second wiring extending into the peripheral area is electrically connected with the second contact plug, and the first wiring extending into the peripheral area is electrically connected with the first contact plug.

Based on the same inventive concept, the present invention also provides a three-dimensional phase change memory, which comprises:

the circuit comprises a first interlayer dielectric layer, a second interlayer dielectric layer and a plurality of first contacts, wherein a plurality of first wirings and a plurality of first contacts are formed in the first interlayer dielectric layer;

a plurality of phase change memory cells spaced apart from each other and formed on the first interlayer dielectric layer, each of the phase change memory cells having a bottom electrode and a top electrode, the bottom electrodes being aligned with and electrically contacting the corresponding first contacts;

the second interlayer dielectric layer fills gaps between adjacent phase change memory cells and buries the tops of the phase change memory cells, a plurality of second contacts are formed in the second interlayer dielectric layer, and each second contact is aligned with and electrically contacted with the top electrode of the corresponding phase change memory cell;

a plurality of second wirings intersecting the first wirings, formed on the second interlayer dielectric layer and the second contacts, and each of the second wirings is electrically connected to the top electrode of the corresponding phase change memory cell through the corresponding second contact;

wherein the first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

Optionally, the three-dimensional phase change memory further includes a substrate, where the first interlayer dielectric layer and the first wiring are formed on the substrate, the substrate has a storage region and a peripheral region located at the periphery of the storage region, a multi-layer metal interconnection structure is formed in the peripheral region, the first wiring and one layer of metal wiring in the multi-layer metal interconnection structure are the same layer of metal, and the second wiring and another layer of metal wiring in the multi-layer metal interconnection structure are the same layer of metal;

and/or the three-dimensional phase change memory further comprises a substrate, wherein the first interlayer dielectric layer and the first wiring are formed on the substrate, the substrate is provided with a storage area and a peripheral area located at the periphery of the storage area, the first wiring and the second wiring extend from the storage area to the peripheral area, and a second contact plug electrically connected with the second wiring and a first contact plug electrically connected with the first wiring are formed in the peripheral area.

Optionally, the materials of the first wire and the second wire respectively comprise at least one of Cu, Al, Pt, Au and Ag, and the materials of the second contact and the first contact respectively comprise at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon and metal silicide.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. the manufacturing method enables that the correlation in the existing double patterning technology does not exist among the patterning processing of the bit line, the phase change memory unit and the word line, the bit line, the phase change memory unit and the word line are manufactured separately, the shape and the size of the phase change memory unit do not depend on the overlapping condition of the cross point of the word line and the bit line completely, and the phase change memory unit which is located at the cross point of the word line and the bit line and is in a square column shape in the prior art can be replaced by a ruler close to the contact hole The small cylindrical shape can be beneficial to further miniaturization of the whole size of the phase change memory and further improvement of the storage density.

2. The bit line, the phase change memory unit and the word line can be manufactured separately, so that the bit line, the phase change memory unit and the word line can be manufactured by adopting a corresponding single exposure technology (or a single patterning processing technology), the process complexity and the cost caused by the fact that the word line and the bit line are manufactured by using a double patterning technology in the prior art can be avoided, and the effects of simplifying process steps and reducing the cost are achieved.

3. Since the second wire (for example, the word line) can be electrically contacted with the top electrode of the phase change memory cell through the second contact, and the first wire (for example, the bit line) can be electrically contacted with the bottom electrode of the phase change memory cell through the first contact, parasitic effects (including parasitic resistance R, parasitic capacitance C, RC delay effect and the like) caused by the word line and the bit line can be reduced, the crosstalk problem between adjacent memory cells is improved, and further, the programming current and the power supply requirement of the phase change memory are reduced.

4. The phase change memory cell can be further provided with a peripheral area, and the first contact plugs used for leading the first wiring (such as bit lines) outwards and the second contact plugs used for leading the second wiring (such as word lines) outwards are all arranged on the periphery of the array formed by the phase change memory cells, so that the problem that the word line contact plugs and the bit line contact plugs occupy storage area in the prior art can be avoided, and the overall size of the phase change memory can be further reduced, and the storage density can be further improved.

5. The first wiring process and the second wiring process may be respectively a manufacturing process of two metal layers in a metal interconnection process in the peripheral region, thereby embedding the manufacturing of the phase change memory into a manufacturing process of the peripheral integrated circuit.

Drawings

Fig. 1A to 1C are schematic cross-sectional views illustrating a device structure in a conventional method for manufacturing a three-dimensional phase change memory.

Fig. 2 is a schematic diagram illustrating the distribution of word lines, bit lines and contact holes thereof in a conventional three-dimensional phase change memory.

Fig. 3 is a flowchart illustrating a method for fabricating a three-dimensional phase change memory according to an embodiment of the invention.

Fig. 4A to 4G are schematic cross-sectional views of devices in a method for manufacturing a three-dimensional phase change memory according to an embodiment of the invention.

Fig. 5 is a schematic top view illustrating a method for fabricating a three-dimensional phase change memory according to an embodiment of the invention.

FIG. 6 is a schematic cross-sectional view of a device in a method for fabricating a three-dimensional phase change memory according to another embodiment of the invention.

FIG. 7 is a schematic diagram illustrating the distribution of word lines, bit lines and contact holes thereof in the three-dimensional phase change memory shown in FIG. 6.

Wherein the reference numerals are:

100-a substrate; 101-a first interlayer dielectric layer; 1011-first dielectric layer; 1012-second dielectric layer; 102 — a first wiring; 102' -a first level of word line peripheral circuit wiring (i.e., a level of metal wiring in a multi-level metal interconnect structure in the peripheral region); 103-a first contact; 103' -peripheral contacts; 104-phase change memory cells; 104 a-a stack; 1041-a bottom electrode layer; 1042-gating layer; 1043-an intermediate electrode layer; 1044-a phase change storage layer; 1045-a top electrode layer; 105-gap; 106-a first interface protection layer; 1061-a first interface layer; 1062-a second interface layer; 107-a second interlayer dielectric layer; 1071 — a second interface protection layer; 1072 — a gap filling layer; 1073-a third dielectric layer; 108-a second contact; 108' -peripheral contacts; 109 — second wiring; 109' -a second layer of word line peripheral circuit wiring (i.e., another layer of metal wiring in the multilayer metal interconnect structure in the peripheral region); cell-phase change memory cell; WL-word line; BBL-bottom bit line; TBL-top bit line; CT1 — second contact plug (i.e., bit line contact plug to BBL); CT2 — first contact plug (i.e., word line contact plug to WL); CT 3-third contact plug (i.e., bit line contact plug to TBL).

Detailed Description

Referring to fig. 1A to 1C, in the conventional method for manufacturing a three-dimensional phase change memory, when forming each layer of phase change memory cells and bit lines BL and word lines WL electrically connected to the phase change memory cells, a double patterning technique (also referred to as a double pattern exposure technique) is usually adopted, and the double patterning technique requires two times of overlapping the patterns of the word lines WL and the bit lines BL to define the patterns of the phase change memory cells at the intersections of the word lines WL and the bit lines BL.

For example, when fabricating a bottom phase-change memory cell, a word line WL electrically connected to the bottom phase-change memory cell, and a bottom bit line BL, it is usually necessary to perform a photolithography and etching process on a stack layer deposited for fabricating the bottom phase-change memory cell and the bottom bit line layer, and perform a first re-patterning to form a plurality of bit lines BL extending along a horizontal direction Y and divide the stack layer into a plurality of bottom stacks extending along the horizontal direction Y and having parallel lines, where a gap is formed between the stacks of adjacent bottom layers, as shown in fig. 1A; after gap filling and deposition of the word line layer, the stacked body of the word line layer and the bottom layer is subjected to photolithography and etching once again, a second re-patterning is performed to form several word lines WL extending in the horizontal direction X, and the stacked body of the bottom layer extending in the Y direction in fig. 1A is simultaneously subjected to division in the X direction, thereby forming phase change memory cells cell located at intersections of the word lines WL and the bottom bit lines BL, as shown in fig. 1B.

When the phase change memory cell of the top layer and the bit line BL of the top layer electrically connected to the phase change memory cell are further manufactured based on the structure of fig. 1B, similarly, a double patterning technique (double patterning technique) is also required to be used for implementation, specifically, a first double patterning is required to be performed on the stacked layers of the phase change memory cell deposited for manufacturing the top layer, a stacked body of the top layer extending along the horizontal direction X is formed, then, after gap filling and deposition of the bit line layer of the top layer, a second double patterning is required to be performed on the bit line layer of the top layer and the stacked body of the top layer, so as to form the bit line BL of the top layer extending along the Y direction, and simultaneously, the stacked body of the top layer extending along the X direction is divided along the Y direction, so as to form the phase change memory cell located at the intersection of the word line WL and the bit line BL of the top layer, as shown in fig. 1C.

If the architecture of the three-dimensional phase-change memory includes four stacked phase-change memory cells, the sequential structure of bit line-phase-change memory cell-word line-phase-change memory cell can be repeatedly fabricated once again along the Z-direction according to the above-mentioned method.

Referring to fig. 2, in the conventional three-dimensional phase change memory architecture, word line contact plugs (also called contacts or contacts in some embodiments, i.e., CT1 in fig. 2) for leading word lines WL out, bit line contact plugs (i.e., CT2 in fig. 2) for leading bit lines BBL out of the bottom layer, and bit line contact plugs (i.e., CT3 in fig. 2) for leading bit lines TBL out of the top layer are typically arranged in an array formed by phase change memory cells.

The inventor researches and discovers that the existing three-dimensional phase change memory and the manufacturing method thereof have the following defects: (1) because each layer of phase change memory cell and the manufacture of the bit line BL and the word line WL which are electrically connected with each layer of phase change memory cell need to use a double patterning technology, the shape and the size of each layer of phase change memory cell completely depend on the overlapping condition of the cross points of the word line and the bit line, and the phase change memory cell is not beneficial to realizing smaller memory size and higher memory density; (2) the process is complex and expensive, and the reduction of parasitic effects (including parasitic resistance R, parasitic capacitance C, RC delay effect, and the like) introduced by the word line WL and the bit line BL is limited; (3) since both the word line contact plugs and the bit line contact plugs are arranged in the array formed by the phase change memory cells, the area of the storage region of the phase change memory is occupied, and the further reduction of the size and density of the whole phase change memory is limited.

Based on the above, the invention provides a three-dimensional phase change memory and a manufacturing method thereof, so that each layer of phase change memory unit and the word line and the bit line required by each layer of phase change memory unit are manufactured respectively; the word line and the bit line are realized through a wiring process, and the word line and the bit line are respectively electrically connected with the corresponding contacts and the corresponding electrodes of the phase change memory unit, so that the shape and the size of the phase change memory unit are not completely dependent on the overlapping condition of the cross points of the word line and the bit line, the realization of smaller memory size and higher memory density is facilitated, the parasitic effect introduced by the word line and the bit line can be improved, and the programming current and the power supply requirement of the phase change memory are reduced. Further, when the word lines, the bit lines and the phase change memory cells are all implemented by using a single exposure technique, the process complexity and cost caused by using a double patterning technique to fabricate the word lines and the bit lines in the prior art can be further avoided. In addition, the contact plugs for leading out the word lines and the bit lines can be arranged on the periphery of the array formed by the phase change memory cells, so that the overall size of the phase change memory can be further reduced, and the storage density can be further improved.

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 3, the present embodiment provides a method for manufacturing a three-dimensional phase change memory, which includes the following steps:

s1, forming a first interlayer dielectric layer by adopting a first wiring process, wherein a plurality of first wirings and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer;

s2, forming a plurality of phase change memory cells spaced from each other on the first interlayer dielectric layer, wherein each phase change memory cell is provided with a bottom electrode and a top electrode, and the bottom electrodes are aligned with and electrically contacted with the corresponding first contacts;

s3, forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills gaps between adjacent phase change memory cells and buries the tops of the phase change memory cells;

s4, forming a second contact in the second interlayer dielectric layer by using a second wiring process, and forming a plurality of second wirings on the second interlayer dielectric layer, where each of the second contacts is aligned with and electrically contacts with the corresponding top electrode of the phase change memory cell, and each of the second wirings is electrically connected to the corresponding top electrode of the phase change memory cell through the corresponding second contact, where the first wirings are bit lines and the second wirings are word lines, or the first wirings are word lines and the second wirings are bit lines.

First, referring to fig. 4A, in step S1, a substrate 100 is provided, and then a first interlayer dielectric layer 101, a plurality of first wires 102 extending along a first direction Y, and a plurality of first contacts 103 on each first wire 102 may be formed on the substrate 100 by using a first wiring process.

The substrate 100 may be a wafer material that has been processed through a series of integrated circuit manufacturing processes, and the wafer material may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds, which may also be a multilayer structure or be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeO), and the like. The substrate 100 may have an active or passive electronic element such as a MOS transistor, a diode, or a resistor, may have a device isolation structure, or may further have a multilayer metal interconnection structure. When the three-dimensional phase change memory to be formed has two or four or more stacked phase change memory cells, the fabrication of some layers of the phase change memory cells and their electrically connected word lines and/or bit lines in the substrate 100 may also be completed.

When the first wirings 102 are used as bit lines, a column of phase change memory cells are formed over the first contacts 103 on each of the first wirings 102, and when the first wirings 102 are used as word lines, a row of phase change memory cells is formed over the first contacts 103 on each of the first wirings 102.

The process of step S1 and the subsequent steps S2 to S4 will be described in detail below, taking as an example that the first wiring 102 serves as a bit line and the second wiring formed subsequently serves as a word line.

As an example, in step S1, the process of forming the first interlayer dielectric layer 101, the first wiring 102, and the first contact 103 includes:

first, a first dielectric layer 1011 is formed on the substrate 100 by a suitable process such as chemical vapor deposition, spin coating, etc., wherein the material of the first dielectric layer 1011 includes any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, etc. The first dielectric layer 1011 is preferably a low-k dielectric having a dielectric constant k less than 3, so as to reduce the parasitic effect introduced by the first wire.

Next, using a bit line mask, the first dielectric layer 1011 is subjected to photolithography and etching to form a plurality of first trenches (not shown) extending along the first direction Y.

Then, a conductive material is filled into each of the first trenches by a suitable process such as chemical vapor deposition, sputter deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, or the like, and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP) which stops on the top surface of the first dielectric layer 1011 to form the first wire 102 filled in each of the first trenches, whereby the material of the first wire 102 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, metal silicide, or the like.

Next, by using a suitable process such as chemical vapor deposition and spin coating, a second dielectric layer 1012 is covered on the first dielectric layer 1011 and the first wire 102, the first interlayer dielectric layer 101 is formed by the second dielectric layer 1012 and the first dielectric layer 1011, and the material of the second dielectric layer 1012 may be the same as or different from that of the first dielectric layer 1011.

Thereafter, the second dielectric layer 1012 may be subjected to contact hole lattice lithography and etching by means of a corresponding mask capable of defining a contact hole lattice, so as to form a plurality of first contact holes (not shown) on each first wire 102, which expose top surfaces of corresponding positions of the first wires 102. When the size and the shape of the phase change memory cell to be formed are substantially the same as those of the first contact 103 to be formed, the mask capable of defining the contact hole lattice is a mask for manufacturing the phase change memory cell array.

Then, by a suitable process such as chemical vapor deposition, sputtering deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, etc., the first contact holes are filled with a conductive material, and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP), which stops on the top surface of the second dielectric layer 1012, to form the first contacts 103 filled in the first contact holes. The material of the first contact 103 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, and the like. The material of the first contact 103 may be the same as or different from that of the first wiring 102, and for example, the first wiring 102 is made of copper and the first contact 103 is made of tungsten. The phase change memory cells connected to the same first wiring 102 through the first contact 103 subsequently constitute a column of phase change memory cells.

Of course, the first wiring process may not be limited to the above example, and in another example of the present embodiment, the process of forming the first interlayer dielectric layer 101, the first wiring 102 and the first contact 103 by the first wiring process may include forming a plurality of first wirings 102 separated from each other and extending along the first direction Y on the substrate 100 by a metal lift-off (lift-off) process, in which a patterned photoresist layer is formed on the substrate 100, a metal layer is then covered on the patterned photoresist layer and the gaps thereof, and then the patterned photoresist layer is stripped, the metal layer filled in the gaps of the patterned photoresist layer is the first wiring 102, and the metal layers except the gaps are removed along with the stripping of the photoresist layer; then, a first interlayer dielectric layer 101 is covered on the gap of the first wire 102 and the top surface of the first wire 102, the first interlayer dielectric layer 101 may fill the gap of the first wire 102, then holes are punched in the first interlayer dielectric layer 101 at corresponding positions of the first wire 102 to form first contact holes arranged in an array, the first contact holes expose the top surface of the first wire 102, and then the first contacts 103 filled in the first contact holes are further formed according to the method of the foregoing example.

Alternatively, the first wiring process may be a copper wiring process (e.g., a copper interconnect process or a rewiring process using copper wires, etc.).

The first wire 102 can be realized by a single patterning technique (also referred to as a single patterning technique, a single photolithography technique, etc.) without a double patterning technique, and has a few process steps and a low cost.

With continued reference to fig. 4A to 4D, in step S2, a plurality of phase change memory cells spaced apart from each other are formed on the first interlayer dielectric layer 101, each phase change memory cell has a bottom electrode (i.e., 1041) layer and a top electrode (i.e., 1045 layer), and the bottom electrodes are aligned with and electrically contact with the corresponding first contacts 103. The specific process of the step is as follows:

first, a first interlayer dielectric layer 10 is formed by a suitable process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition1, a bottom electrode layer 1041, a gate layer 1042, an intermediate electrode layer 1043, a phase change memory layer 1044, a top electrode layer 1045, and a hard mask layer 1046 are sequentially stacked from bottom to top to form a phase change memory stack layer 104, as shown in fig. 4A. The bottom electrode layer 1041, the middle electrode layer 1043, and the top electrode layer 1045 may be made of the same or different materials, and may be respectively selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, and Ni. The gate layer 1042 may include an Ovonic Threshold Switch (OTS) material. The material of the phase-change storage layer 1044 may be any suitable phase-change material, and may include at least one of a Ge-Sb-Te based phase-change material (also referred to as GST), a Ge-Te based phase-change material, a Ge-Sb based phase-change material, a Si-Sb-Te based phase-change material, a Sb-based phase-change material, and the like, a combination of two phase-change materials, a combination of three phase-change materials, or a combination of more phase-change materials, for example. Wherein the Ge-Sb-Te based phase change material is composed of three elements of Ge, Sb and Te, which can include but not limited to Ge₃Sb₄Te₈、Ge₂Sb₂Te₅、Ge₂Sb₂Te₄、GeSb₂Te₄And the Ge-Te based phase change material consists of two elements of Ge and Te. Wherein, the Ge-Sb based phase-change material consists of two elements of Ge and Sb, and the Si-Sb-Te based phase-change material consists of three elements of Si-, Sb and Te, which can include but are not limited to Si₁₁Sb₅₇Te₃₂、Si₁₈Sb₅₂Te₃₀、Si₂₄Sb₄₈Te₂₈And the like. Therefore, based on the fact that the phase change material contained in the phase change storage layer 1044 may be a single phase change material or a combination of multiple phase change materials, the number of layers of the phase change storage layer 1044 is not particularly limited, and may be a single layer or multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers or even more, the crystallization temperature and the threshold voltage of two adjacent layers of phase change materials may be different, and when the pulse voltage or the pulse current for generating the phase change corresponding to the phase change material with the crystallization temperature and the threshold voltage being different are also different, in this way, under a pulse voltage or the pulse current of a specific magnitude, the phase change of all layers of the phase change storage layer 1044 may be caused to be differentThe phase change materials may be in a low resistance state, or all the layers of the phase change storage layer 1044 may be in a high resistance state, or some of the layers of the phase change materials may be in a low resistance state, and some of the layers of the phase change materials may be in a high resistance state. The hard mask layer 1046 may be made of one or a combination of oxide, nitride, metal, or the like.

Then, a single exposure technique or a multiple pattern exposure technique may be selected according to the size of the phase change memory cell to be formed, so as to perform corresponding photolithography (including glue coating, exposure, development, and the like) and etching on the hard mask layer 1046, so as to form a pattern for defining each phase change memory cell in the hard mask layer 1046. When a single exposure technique (also referred to as a single patterning technique, a single photolithography technique, etc.) is used, a photomask having a pattern corresponding to each phase change memory cell may be used to perform a photolithography and a corresponding etching on the hard mask layer 1046 of the phase change memory stack layer 104, so as to form a pattern for defining each phase change memory cell in the hard mask layer 1046. When a multiple pattern exposure technology is adopted, the multiple pattern exposure technology can be a lithography-etching-lithography-etching (lithography-Etch-lithography-Etch, LELE) technology, an original layer of lithography pattern is split onto two or more masks, and the superposition of pattern density in the hard mask layer 1046 is realized; the multiple pattern exposure technique may also be a lithography-cure-lithography-Etch (LFLE) technique, which uses two lithography steps and one etching step to achieve pattern density doubling in the hard mask layer 1046; the multiple pattern exposure technique may also be a Self-Aligned Double Patterning (SADP) technique, in which an axis pattern is formed by a single photolithography and etching process, then a sidewall pattern is formed on the sidewall by an atomic layer deposition and etching process, the axis layer (i.e., sacrificial layer) is removed, and a hard mask layer 1046 pattern in the form of a sidewall with a halved size (pitch) is formed. Therefore, no matter what kind of lithography is used in this step, the hard mask layer 1046 is finally patterned, and the pattern in the hard mask layer 1046 corresponds to the phase change memory cell and the array formed by the phase change memory cell, and the size and shape of each pattern meet the manufacturing requirements of the size and shape of each phase change memory cell. When the single exposure technique is used to form the pattern for defining each phase-change memory cell in the hard mask layer 1046, the process steps are fewer and the cost is lower than that of the double-pattern exposure technique or the multiple-pattern exposure processing technique, but the limit size of the phase-change memory cell formed by the single exposure technique is limited by the limit size of the single exposure technique.

Then, with the patterned hard mask layer 1046 as a mask, the etching of the top electrode layer 1045 and the phase change storage layer 1044 is stopped on the top surface of the middle electrode layer 1043 to form a stacked body 104a distributed in an array, as shown in fig. 4B. Each of the stacks 104a has an island shape, and may be a square column shape, a cylindrical shape, or the like. Each of the stacks 104a is located at an intersection of the first wiring 102 and a second wiring to be formed later, with a gap 105 between adjacent stacks 104 a.

Then, the first interface protection layer 106 may be sequentially formed on the sidewall surface of each of the stacks 104a by a deposition method or a plasma reaction method, as shown in fig. 4C. The first interface protection layer 106 may be formed as a sidewall of the stacked body 104a in the subsequent process, which may protect the sidewall of the stacked body 104a from being damaged in the subsequent process, and may also improve adhesion between the subsequent gap filling layer and the sidewall of the stacked body 104a, and block element diffusion between the stacked body 104a and the subsequently formed gap filling layer, thereby preventing material composition of each film layer from changing, and ensuring device performance. In the present embodiment, the first interface protective layer 106 has a first interface layer 1061 and a second interface layer 1062 sequentially stacked on the sidewall surface of each stack 104 a. The material of the first interface layer 1061 may be a nitride (e.g., silicon nitride, etc.), and the material of the second interface layer 1062 may be an oxide (e.g., silicon oxide, etc.), for example.

Next, under the protection of the hard mask layer 1046 and the first interface protection layer 106 on the sidewall of the stacked body 104a, the second interface layer 1062, the first interface layer 1061, the middle electrode layer 1043, the gate layer 1042, and the bottom electrode layer 1041 are sequentially etched along the gap 105 from top to bottom until the top surface of the second dielectric layer 1012 is exposed, thereby forming a plurality of phase change memory cells spaced apart from each other and arranged in an array, and the gap 105 between adjacent phase change memory cells extends to the top surface of the second dielectric layer 1012, as shown in fig. 4D. The bottom electrode layer 1041 in the phase change memory cell is the bottom electrode thereof, the middle electrode layer 1043 in the phase change memory cell is the middle electrode thereof, and the top electrode layer 1045 in the phase change memory cell is the top electrode thereof.

Referring to fig. 4D to fig. 4G, in step S3, a second interlayer dielectric layer 107 is formed, where the second interlayer dielectric layer 107 fills the gap 105 between adjacent phase change memory cells and buries the top of each phase change memory cell therein, and the method specifically includes:

first, a second interfacial protection layer 1071 is formed on sidewalls of each phase change memory cell, as shown in fig. 4D. The second interface protection layer 1071 may be a single-layer dielectric or a multi-layer dielectric, and the material thereof includes, for example, silicon nitride.

Then, a gap-fill layer 1072 is deposited in the gap 105 between adjacent phase change memory cells and on the top surface of the hard mask layer 1046 by a suitable material deposition process such as chemical vapor deposition, high aspect ratio vapor deposition, etc., and the deposited gap-fill layer 1072 may fill the gap 105 or may close the gap 105 into a structure with an air gap (which may reduce parasitic capacitance), as shown in fig. 4E. The gap fill layer 1072 may be made of a material including, for example, one or more of silicon oxide, tetraethylorthosilicate, low-k dielectric (including organic or inorganic porous materials), and the like.

Next, the top of the gap fill layer 1072 is cmp polished until the top surface of the top electrode of each phase change memory cell is exposed, as shown in fig. 4F.

Then, a third dielectric layer 1073 is deposited on the gap fill layer 1072 and the top electrode layer 1045 to form a second interlayer dielectric layer 107, wherein the second interlayer dielectric layer 107 includes a second interface protection layer 1071, a gap fill layer 1072 and a third dielectric layer 1073, as shown in fig. 4G. The material of the third dielectric layer 1073 may include any one or combination of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or low k dielectrics, among others. Preferably, the third dielectric layer 1073 is a low-k dielectric with a dielectric constant k less than 3 to facilitate reducing parasitic effects introduced by the second wire.

Referring to fig. 4G and 5, in step S4, a second contact 108 is formed in the third dielectric layer 1073 and a second wire 109 is formed on the third dielectric layer 1073 using a second wire process. When the first wirings are used as bit lines, the second wirings 109 are used as word lines, and each second wiring 109 is electrically connected to a plurality of second contacts 108 arranged in a row along the second direction X, that is, the phase change memory cells connected to the same second wiring 109 through the second contacts 108 form a row of phase change memory cells.

The second wiring process can be implemented by a single patterning technology (also referred to as a single patterning technology, a single photolithography technology, etc.), and does not require a double patterning technology, so that the process steps are few and the cost is low.

In this embodiment, the second wire 109 and the first wire 102 intersect perpendicularly, the contact array formed by the second contact 108 and the contact array formed by the first contact 103 are aligned, the cross sections of the second contact 108, the first contact 103 and the phase change memory cell along the X-Y plane are all circular, the radius of the cross-sectional circle of the second contact 108 and the first contact 103 is smaller than that of the cross-sectional circle of the phase change memory cell, that is, the size of the second contact 108 and the first contact 103 is smaller than that of the phase change memory cell. As can be seen from fig. 5, since the patterning process of the phase change memory cell and the patterning process of the word line and the bit line are not related any more in this embodiment, the finally formed phase change memory cell may be a cylindrical structure having a smaller line width than the word line and the bit line.

As an example, referring to fig. 4G, the process of implementing the second wiring process in this step includes:

first, the third dielectric layer 1073 may be subjected to photolithography and etching of a contact hole lattice with the aid of a corresponding mask that can be used to define the contact hole lattice to form a number of second contact holes (not shown) in the third dielectric layer 1073. The mask may be the same mask as the mask used to form the first contact in step S1, so as to reduce the cost of the mask and improve the alignment accuracy between the first contact and the second contact to be formed.

Then, the second contact holes are filled with a conductive material by a suitable process such as chemical vapor deposition, sputter deposition, electroplating, electroless plating, metal silicide fabrication, doped polysilicon deposition, etc., and the filled conductive material is further subjected to Chemical Mechanical Polishing (CMP) which stops on the top surface of the third dielectric layer 1073 to form the second contacts 108 filled in the second contact holes. The material of the second contact 108 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, and the like.

Thereafter, several second wirings 109 extending in the second direction X direction may be formed on the third dielectric layer 1073 in a manner similar to the method of forming the first dielectric layer 1011 on the substrate 100 and forming the first wirings 102 in the first dielectric layer 1011.

It should be noted that, in another example of the present embodiment, the second wiring process may include a process of forming the second contact 108 through a contact hole process and a process of forming the second wiring 109 through a metal stripping process, and specifically, reference may be made to the description of another embodiment of the first wiring process, and details are not repeated here. In another example of this embodiment, the second wiring process may also be a dual damascene process, which includes: a trench for forming the second wire 109 is etched in the dielectric layer and a second contact hole exposing the top surface of the corresponding top electrode is etched in the bottom of the trench, and then the second contact hole and the trench are filled together to form the second contact 108 and the second wire 109 together.

It should be understood that, in the above embodiments, only one layer of phase change memory cells and the fabrication of the electrically connected word lines and bit lines thereof is shown, when the architecture of the three-dimensional phase change memory to be fabricated in the present invention includes two stacked layers of phase change memory cells, then according to the fabrication method in the above embodiments, a corresponding contact array is fabricated above the second wiring, then the upper layer of phase change memory cells is fabricated above the contact array, and then another contact array and a third wiring electrically connected to the another contact array are fabricated on the upper layer of phase change memory cells, the second wiring and the third wiring intersect, and the third wiring may be parallel to the first wiring; alternatively, according to the manufacturing method in the above embodiment, a lower-layer phase-change memory cell and a fourth wiring electrically connected to the lower-layer phase-change memory cell may be manufactured under the first wiring, the fourth wiring connects to the bottom electrode of the lower-layer phase-change memory cell through a corresponding contact in a contact array, the first wiring connects to the top electrode of the lower-layer phase-change memory cell through a corresponding contact in another contact array, the fourth wiring intersects with the first wiring, and the fourth wiring may be parallel to the second wiring.

Therefore, when the architecture of the three-dimensional phase-change memory required to be fabricated by the present invention includes three, four or more layers of phase-change memory cells stacked along the Z direction perpendicular to the direction X, Y, the sequential structure of wiring-contact-phase-change memory cell-contact-wiring … in the above embodiment may be repeated along the Z direction until the fabrication of the phase-change memory cells of all layers and the word lines and bit lines electrically connected thereto is completed.

It should be noted that, referring to fig. 6 and 7, a substrate 100 generally has a memory area I and a peripheral area II, where the memory area I is mainly used for forming a phase-change memory array to store data, and the peripheral area II is mainly used for forming a peripheral circuit to implement functional control of operations (read operation, write operation, etc.) of the phase-change memory array. In some embodiments, the peripheral circuits in the peripheral region II are digital, analog and/or mixed signal circuits formed in advance in the substrate for the operation of the phase change memory array, and these signal circuits include control logic elements, data buffers, decoders (also referred to as decoders), drivers, read/write circuits, etc., and these peripheral circuits need to be electrically connected to the word lines and bit lines finally through a multi-layer metal interconnection structure formed in the substrate and electrical connection structures such as contact plugs formed in the peripheral region II and located at the periphery of the memory region.

The first wiring process and the second wiring process of the present embodiment are implemented separately from the manufacturing process of the electrical connection structure for implementing electrical connection of the peripheral circuit and the word line or the bit line in the substrate of the peripheral region. However, the technical solution of the present invention is not limited thereto, and in other implementations of the present invention, the first wiring process and the second wiring process may be implemented in a manufacturing process of an electrical connection structure for electrically connecting a peripheral circuit and a word line or a bit line in a substrate for implementing a peripheral region.

Specifically, referring to fig. 6 and 7, another embodiment of the invention provides a method for manufacturing a three-dimensional memory, which also includes the steps S1 to S4 as described above. The substrate 100 provided in step S1 has a memory area I and a peripheral area II located outside the memory area I, where the substrate of the peripheral area II has formed therein a desired peripheral circuit for realizing functional control of the operation (read operation, write operation, etc.) of the phase-change memory cell. The manufacturing method of the present embodiment further includes: a multilayer metal interconnection structure is formed in the substrate 100 in the peripheral region II through a multilayer metal interconnection process, wherein the first wiring process in step S1 is a formation process of a certain layer of metal wiring in the multilayer metal interconnection process, and the second wiring process in step S4 is a formation process of another layer of metal wiring in the multilayer metal interconnection process, so that the first wiring 102 and the one layer of metal wiring in the multilayer metal interconnection structure are the same layer of metal, and the second wiring 109 and the other layer of metal wiring in the multilayer metal interconnection structure are the same layer of metal. At this time, the manufacture of the phase change memory can be embedded in the manufacturing process of the peripheral integrated circuit. When the multilayer metal interconnection process is a copper interconnection process, the first wiring 102 and the second wiring 109 may both be copper, and the first contact 102 and the second contact 108 may both be tungsten plugs.

As an example, in step S1, while forming the first wiring 102 as a bit line in the memory area I by the first wiring process, a first-layer word line peripheral circuit wiring 102 'is formed in the peripheral area II, and while forming the first contact 103 in the memory area I, a peripheral contact 103' that is located on the first-layer word line peripheral circuit wiring 102 'and electrically contacts the first-layer word line peripheral circuit wiring 102' is also formed in the peripheral area II; simultaneously with the formation of the second contact 108 in the memory area I by the second wiring process in step S4, a peripheral contact 108 'that is located on the peripheral contact 103' and is electrically contacted with the peripheral contact 103 'is also formed in the peripheral area II, and simultaneously with the formation of the second wiring 109 in the memory area I, a second-layer word line peripheral circuit wiring 109' that is located on the peripheral contact 108 'and is electrically contacted with the peripheral contact 108' is also formed in the peripheral area II, whereby the peripheral contacts 103 'and 108' form a word line contact plug (i.e., a second contact plug), and the first-layer word line peripheral circuit wiring 102 ', the peripheral contacts 103' and 108 ', and the second-layer word line peripheral circuit wiring 109' are sequentially connected to form an electrical connection structure for electrically connecting the second wiring (i.e., the word line) 109 and the corresponding peripheral circuit in the peripheral area II.

It should be understood that the first layer of word line peripheral circuit wiring 102 ' is electrically isolated from the first wiring 102, the second layer of word line peripheral circuit wiring 109 ' may be integrated with the second wiring 109, that is, the second layer of word line peripheral circuit wiring 109 ' is a portion of the second wiring 109 extending into the peripheral region II, the second layer of word line peripheral circuit wiring 109 ' may be separated from the second wiring 109, and the second layer of word line peripheral circuit wiring 109 ' may be electrically connected to the second wiring 109 only by a subsequent wiring process or a metal interconnection process.

Likewise, when the first wiring 102 is led out outward from the top surface of the peripheral region II, in step S1, the first wiring 102 is formed as a bit line in the storage region I by the first wiring process, while a first-layer bit line peripheral circuit wiring (not shown) is formed in the peripheral region II, and a first peripheral contact (not shown) which is located on the first-layer bit line peripheral circuit wiring and is electrically contacted with the first-layer bit line peripheral circuit wiring is also formed in the peripheral region II while the first contact 103 is formed in the storage region I; simultaneously with the formation of the second contact 108 in the memory area I by the second wiring process in step S4, a second peripheral contact (not shown) that is located on the first peripheral contact and electrically contacts the first peripheral contact is also formed in the peripheral area II, and simultaneously with the formation of the second wiring 109 in the memory area I, a second level of bit line peripheral circuit wiring (not shown) that is located on the second peripheral contact and electrically contacts the second peripheral contact is also formed in the peripheral area II, whereby the first peripheral contact and the second peripheral contact form a bit line contact plug (i.e., a first contact plug), and the first level of bit line peripheral circuit wiring, the first peripheral contact and the second peripheral contact, and the second level of bit line peripheral wiring are sequentially connected to form an electrical connection structure for electrically connecting the first wiring (i.e., the word line) 102 and the corresponding peripheral circuit in the peripheral area II.

It should also be understood that the second level bitline peripheral circuit wiring is electrically isolated from the second wiring 109. The first layer of bit line peripheral circuit wiring may be integrated with the first wiring 102, that is, the first layer of bit line peripheral circuit wiring is a portion of the first wiring 102 extending into the peripheral region II, the first layer of bit line peripheral circuit wiring may also be electrically insulated and isolated from the first wiring 102, and the first layer of word line peripheral circuit wiring and the first wiring 102 may be electrically connected only through a subsequent wiring process or a metal interconnection process, that is, through an electrical connection structure including the second layer of bit line peripheral circuit wiring.

That is, in the present embodiment, the substrate 100 has the storage region I and the peripheral region II located at the periphery of the storage region I, the first wiring 102 and the second wiring 109 each extend from the storage region I into the peripheral region II, and the manufacturing method of the present embodiment further includes: while the first wiring process and the second wiring process are respectively performed in the storage area I, corresponding electrical connection structures are also formed in the peripheral area II together, so that the manufacturing of the second contact 108 is completed in the storage area I, and the manufacturing of the first contact plug and the second contact plug is completed in the peripheral area II, so that the second wiring 109 extending into the peripheral area II is electrically connected with the second contact plug, and the first wiring 102 extending into the peripheral area II is electrically connected with the first contact plug.

Referring to fig. 7, in the method for manufacturing a three-dimensional phase-change memory of this embodiment, the contact plugs required by the word lines and the bit lines can be uniformly distributed in the peripheral region II, that is, the second contact plug CT1 required by the second wire 109, the first contact plug CT2 required by the first wire 102, and the third contact plug CT3 required by the third wire (for example, the top bit line TBL) are uniformly distributed in the peripheral region II, so that the problem that the memory area is occupied by the word line contact plugs and the bit line contact plugs in the prior art can be avoided, thereby facilitating further shrinking the overall size of the phase-change memory and further improving the storage density.

Based on the same inventive concept, an embodiment of the present invention further provides a three-dimensional phase change memory, which is preferably manufactured by using the manufacturing method of the three-dimensional phase change memory according to any of the above embodiments of the present invention, and of course, a person skilled in the art may also use corresponding process steps to replace corresponding process steps in the manufacturing method of the three-dimensional phase change memory according to the present invention, so as to manufacture the same structure.

Referring to fig. 3 to 7, the three-dimensional phase change memory of the present embodiment includes:

a first interlayer dielectric layer 101 formed on a substrate 100, wherein a plurality of first wirings 102 and a plurality of first contacts 103 located on each first wiring 102 are formed in the first interlayer dielectric layer 101;

a plurality of phase change memory cells formed on the first interlayer dielectric layer 101, wherein each phase change memory cell has a bottom electrode 1041 and a top electrode 1045, and the bottom electrode 1041 is aligned with and electrically contacts the corresponding first contact 102;

a second interlayer dielectric layer 107, wherein the second interlayer dielectric layer 107 fills gaps between adjacent phase change memory cells and buries the tops of the phase change memory cells, a plurality of second contacts 108 are formed in the second interlayer dielectric layer 107, and each second contact 108 is aligned with and electrically contacted with the top electrode 1045 of the corresponding phase change memory cell;

a plurality of second wires 109 intersecting the first wires 102, formed on the second interlayer dielectric layer 107 and the second contacts 108, and each of the second wires 109 is electrically connected to the top electrode 1045 of the corresponding phase change memory cell through the corresponding second contact 108;

the first wiring 102 is a bit line and the second wiring 109 is a word line, or the first wiring 102 is a word line and the second wiring 109 is a bit line.

Optionally, the substrate 100 has a storage region I and a peripheral region II located at the periphery of the storage region I, a multi-layer metal interconnection structure (not shown) is formed in the peripheral region II, the first wiring 102 and one layer of metal wiring (e.g., 102 'in fig. 6) in the multi-layer metal interconnection structure are the same layer of metal, and the second wiring 109 and another layer of metal wiring (e.g., 109' in fig. 6) in the multi-layer metal interconnection structure are the same layer of metal.

Alternatively, the substrate 100 has a storage region I and a peripheral region II located at the periphery of the storage region I, the first wiring 102 and the second wiring 109 both extend from the storage region I into the peripheral region II, and a second contact plug (not shown) electrically connected to the second wiring 109 and a first contact plug (not shown) electrically connected to the first wiring 102 are formed in the peripheral region II.

Alternatively, the materials of the first wire 102 and the second wire 109 respectively include at least one of Cu, Al, Pt, Au, and Ag, and the materials of the second contact 108 and the first contact 103 respectively include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, and metal silicide.

It should be understood that, for the specific structure of each film layer in the three-dimensional phase change memory of this embodiment, reference may be made to the description of the corresponding film layer in the above manufacturing method of the three-dimensional phase change memory, and details are not described here again.

In summary, according to the three-dimensional phase change memory and the manufacturing method thereof provided by the invention, the word lines and the bit lines required by each layer of phase change memory cells are manufactured through the corresponding wiring process, the patterning manufacturing of the phase change memory cells is completed after the first wiring is formed and before the second wiring is formed, and the word lines and the bit lines are respectively electrically connected with the corresponding contacts and the corresponding electrodes of the phase change memory cells, so that the shape and the size of the phase change memory cells are not completely dependent on the overlapping condition at the intersections of the word lines and the bit lines, the realization of smaller device size and higher storage density is facilitated, the parasitic effect introduced by the word lines and the bit lines is improved, and the programming current and the power supply requirements of the phase change memory are reduced. And when the corresponding single exposure technology is respectively adopted to manufacture the bit line, the phase change memory unit and the word line, the process complexity and cost brought by the double patterning technology used for manufacturing the word line and the bit line in the prior art can be avoided. In addition, the contact plugs for leading out the word lines and the bit lines can be arranged on the periphery of the array formed by the phase change memory cells, so that the overall size of the phase change memory can be further reduced, and the storage density can be further improved.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A method for manufacturing a three-dimensional phase change memory, comprising:

forming a first interlayer dielectric layer by adopting a first wiring process, wherein a plurality of first wirings and a plurality of first contacts positioned on each first wiring are formed in the first interlayer dielectric layer;

2. The method of manufacturing of claim 1, wherein the step of forming the first interlayer dielectric layer, the first wire, and the first contact using a first wire process comprises:

forming first wirings filled in the first trenches;

and forming first contacts filled in the first contact holes.

3. The method of claim 1, wherein forming a plurality of phase change memory cells spaced apart from one another on the first interlayer dielectric layer comprises:

and carrying out corresponding photoetching and etching on the phase change storage stack layer by adopting a single exposure technology or a multiple pattern exposure technology until the bottom electrode layer is patterned into bottom electrodes which are spaced from each other so as to form a plurality of phase change storage units which are spaced from each other.

4. The manufacturing method according to claim 3, wherein a bottom electrode layer, a gate layer, an intermediate electrode layer, a phase change memory layer, a top electrode layer, and a hard mask layer are sequentially stacked on the first interlayer dielectric layer and the first contact to form the phase change memory stack layer; the steps of photoetching and etching the phase change storage stack layer by adopting a single exposure technology or a multiple pattern exposure technology comprise:

forming a first interface protection layer on a sidewall of the stack;

5. The method of manufacturing of claim 1, wherein forming the second interlevel dielectric layer comprises:

6. The manufacturing method according to claim 5, wherein the step of forming the second contact and the second wiring using a second wiring process comprises:

forming second contacts filled in the second contact holes;

and forming the second wiring on the third dielectric layer.

7. The manufacturing method according to any one of claims 1 to 6, wherein the first interlayer dielectric layer and the first wiring are formed over a substrate having a memory region and a peripheral region located at a periphery of the memory region, the manufacturing method further comprising: forming a multilayer metal interconnection structure in the peripheral area through a multilayer metal interconnection process, wherein the first wiring process is a forming process of a certain layer of metal wiring in the multilayer metal interconnection process, and the second wiring process is a forming process of another layer of metal wiring in the multilayer metal interconnection process, so that the first wiring and the metal wiring in the layer of metal interconnection structure are the same layer of metal, and the second wiring and the metal wiring in the layer of metal interconnection structure are the same layer of metal;

8. A three-dimensional phase change memory, comprising:

9. The three-dimensional phase change memory according to claim 8, further comprising a substrate on which the first interlayer dielectric layer and the first wiring are formed, the substrate having a storage region and a peripheral region located at a periphery of the storage region, the peripheral region having a multi-layered metal interconnection structure formed therein, the first wiring being a same layer of metal as one layer of metal wiring in the multi-layered metal interconnection structure, the second wiring being a same layer of metal as another layer of metal wiring in the multi-layered metal interconnection structure;

10. The three-dimensional phase change memory according to claim 8, wherein the material of the first wire and the second wire respectively comprises at least one of Cu, Al, Pt, Au, Ag, and the material of the second contact and the first contact respectively comprises at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, and metal silicide.