CN111326539B - Resistive random access memory and forming method thereof - Google Patents

Abstract

The invention provides a resistance random access memory and a forming method thereof, wherein the forming method comprises the steps of forming a film stack; patterning the film stack to form a plurality of stack structures; forming a protective layer along the sidewall of the stacked structure; forming a first isolation structure between the stacked structures; forming at least one groove in at least one stacking structure to define a plurality of physically separated electric wire units in the at least one stacking structure; and forming a second isolation structure in the at least one groove. The film stack comprises a bottom electrode layer and a resistance conversion layer positioned on the bottom electrode layer. The invention can solve the problem of soft error bit of the resistance random access memory.

Description

Resistive random access memory and forming method thereof

Technical Field

The present invention relates to semiconductor manufacturing technologies, and more particularly, to a resistive random access memory and a method for forming the same.

Background

The rram has advantages of low power consumption, low operating voltage, short write and erase time, long endurance, long data retention time, non-destructive read operation, multi-state (multi-state), simple manufacturing and expandable property, and thus is an emerging mainstream of the non-volatile memory. The basic structure of the resistive random access memory comprises a metal-insulator-metal (MIM) stack of a bottom electrode, a resistive switching layer and a top electrode. When a forward SET voltage is applied to the rram, a conductive path may be formed in the resistive switching layer to transition from a high resistance state to a low resistance state, which is referred to as a SET (SET) operation. When a reverse RESET voltage is applied to the rram, the conductive path in the resistive switching layer is broken to transition from a low resistance state to a high resistance state, which is referred to as a RESET (RESET) operation. Therefore, the resistance is controlled by the difference of the polarity of the applied voltage, thereby achieving the purpose of information storage.

Due to the high integration of modern memory chips, the structure of a single memory cell is small enough to be susceptible to cosmic rays and/or alpha particles, which can cause bit flips, resulting in data errors. The error caused by these phenomena is called soft error (soft error), so it is highly desirable to provide further improvement to the soft error of the rram.

Disclosure of Invention

The embodiment of the invention provides a method for forming a resistance random access memory, which is used for solving the problem of soft error bits of the resistance random access memory. The method includes forming a film stack, patterning the film stack to form a plurality of stack structures, forming a protective layer along sidewalls of the stack structures, forming first isolation structures between the stack structures, forming at least one recess in at least one stack structure to define a plurality of physically separated electrical wire units in the at least one stack structure, and forming a second isolation structure in the at least one recess. The film stack comprises a bottom electrode layer and a resistance conversion layer positioned on the bottom electrode layer.

The embodiment of the invention provides a resistance random access memory, which comprises a plurality of stacked structures, wherein the stacked structures are respectively separated from each other by first isolation structures. Each of the stacked structures includes a bottom electrode, a plurality of electric wire units, and a passivation layer. The plurality of electric wire units are arranged on the bottom electrode and are physically separated from each other by at least one second isolation structure, and each electric wire unit comprises a resistance conversion structure which is positioned on the bottom electrode. The protective layer is along the sidewall of the stacked structure.

The embodiment of the invention can solve the problem of soft error bits of the resistance random access memory. Multiple wire cells are formed in a single memory cell, and multiple bits can be formed without increasing the volume of the memory cell. Therefore, when the sensing method is used together with the combination mode/differential mode, the occurrence rate of soft error bits can be reduced. In addition, the protective layer formed on the side wall of the memory unit can form energy band difference with the isolation structure between the memory units, thereby avoiding the interference of the adjacent memory units and ensuring the functionality of the resistance random access memory.

The RRAM of the present invention can be applied to various types of semiconductor devices, and in order to make the aforementioned objects, features, and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

Drawings

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily increased or reduced to clearly illustrate the features of the present disclosure.

FIGS. 1A-1I are cross-sectional views illustrating different intermediate stages in the production of a resistive random access memory according to some embodiments;

FIGS. 2A-2G are schematic cross-sectional views illustrating different intermediate stages of an apparatus for manufacturing an RRAM according to other embodiments.

The symbols of the drawings are as follows:

10. 20-RRAM 210, 210' -Top electrode layer

210A, 210B to top electrode 202' to resistance conversion structure

100 to substrate 211, 215 to photoresist layer

101 intermetal dielectric layer 212 protective layer

102. 108-conductive structure 214-first isolation structure

104 dielectric layer 216 recess

106. 304 to conductive layer 217 to insulating layer

200 bottom electrode layer 217A notch

200' to bottom electrode 218 to electric wire unit

202. 202 '- resistive switching layers 220, 220' -second isolation structure

204. 204' first barrier layer 222 to third isolation structure

204 "-first barrier structure 300-intermetal dielectric layer

206. 206' oxygen exchange layer 302 conductive contact

206' -oxygen exchange structure 400-transistor

208. 208' second barrier layer 406 source/drain region

208' -second barrier structures W1, W2-width

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements thereof are disclosed below to simplify the present disclosure. Of course, these specific examples are not intended to be limiting of the disclosure. For example, the following summary of the present specification describes forming a first feature over or on a second feature, i.e., embodiments in which the formed first and second features are in direct contact, and embodiments in which additional features may be formed between the first and second features, i.e., the first and second features are not in direct contact. Moreover, various examples throughout this disclosure may use repeated reference numerals. These reference numerals are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the configurations described.

Although the steps in some of the described embodiments are performed in a particular order, these steps may be performed in other logical orders. In various embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and/or after the steps described in embodiments of the invention. Other features may be added to the RRAM of embodiments of the present invention. Some features may be replaced or omitted in different embodiments.

A Resistive Random Access Memory (RRAM) device of a transistor-resistor (1 transistor-1 resistor,1t1 r) structure has only one wire unit (i.e., wire transmission channel) in a single memory cell (cell). After the wire is formed, the 1T1R structure is easy to generate soft error bits in the set/reset process, and because the soft error bits are randomly generated and are not expected to occur, the current method mostly adopts a two-transistor-two-resistor (2T 2R) structure, so that the resistance random access memory of the 2T2R structure has two wire units in a single memory unit, and the circuit design uses a sensing method (sensing method) in combination mode or differential mode (differential mode) to solve the problem. However, the size of the memory cell also increases, and the problem of soft errors still remains.

The invention provides a resistive random access memory and a forming method thereof, in particular to a resistive random access memory which is provided with a plurality of electric wire units in a single memory unit with a 1T1R structure. Because a plurality of electric wire units are arranged in a single memory unit, the number of bits generated by the single memory unit can be increased under the condition of not increasing the size of the memory unit, and the probability of soft error bits is further improved. For example, when the sensing method is used in the combination mode, even if the soft error bit occurs, the other transmission channels are still reserved to reduce the probability of the soft error bit.

FIGS. 1A-1I are cross-sectional views illustrating different intermediate stages in the manufacture of a resistive random access memory, according to some embodiments. Referring to fig. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, a silicon-on-insulator substrate. For example, the material of the semiconductor substrate may include a doped or undoped semiconductor material, such as silicon, germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, or the like. In addition, the substrate 100 may be formed with active devices and/or passive devices. The active devices may include transistors, diodes, etc., and the passive devices may include resistors, capacitors, inductors, etc. In some embodiments, the substrate 100 may include memory control devices (as will be described in detail later with respect to fig. 1I), including active control devices (e.g., transistors) and interconnect structures (e.g., conductive layers, contacts, etc.).

As shown in fig. 1A, an inter-metal dielectric layer 101 is formed on a substrate 100. The inter-metal dielectric layer 101 may include or be one of an oxide (e.g., silicon oxide, silicon dioxide), a nitride, a low dielectric constant (low-K) dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorine-doped silicate glass, organosilicate glass, siOxCy, carbon-silicon material, or any combination thereof. In one embodiment, the thickness of the IMD layer 101 may be from about 300nm to about 400nm. In addition, the IMD 101 is formed with a conductive structure 102 for connecting the RRAM to the active control device and/or interconnect structure in the substrate 100. In an embodiment, the conductive structure 102 may comprise aluminum, copper, tungsten, or other suitable conductive material.

With continued reference to fig. 1A, next, a layer stack is formed on the inter-metal dielectric layer 101. Specifically, the formed film stack may include a bottom electrode layer 200, a resistive switching layer (resistive switching layer) 202, a first barrier layer 204, an oxygen exchange layer (oxygen exchange layer) 206, a second barrier layer 208, and a top electrode layer 210, which are sequentially formed.

In one embodiment, the bottom electrode layer 200 may comprise one or any combination of tungsten, platinum, aluminum, titanium, and titanium nitride, and may have a thickness of about 25nm to about 35nm. In an embodiment, the resistive switching layer 202 may include a transition metal oxide, such as one or any combination of hafnium oxide, titanium oxide, tungsten oxide, tantalum oxide, and zirconium oxide, and may have a thickness of about 3nm to 10nm. In one embodiment, the first barrier layer 204 and the second barrier layer 208 may comprise aluminum oxide (Al) ₂ O ₃ ) Or silicon nitride (SiN) ₄ ) And may be about 0.4nm to 1nm thick. In one embodiment, the first barrier layer 204 is thicker than the second barrier layer 208. In one embodiment, the conductive oxygen storage layer 206 may comprise aluminum, titanium, or a combination thereof, and may have a thickness of about 20nm to about 40nm. In one embodiment, the method can be implemented byThe bottom electrode layer 200, the resistive switching layer 202, the first barrier layer 204, the oxygen exchange layer 206, and the second barrier layer 208 for film stack are sequentially formed by e-beam evaporation, sputtering, or physical vapor deposition.

Referring to fig. 1B, a patterning process is performed on the film stack to form stack structures respectively corresponding to the conductive structures 102. In detail, a patterned photoresist layer 211 exposing a portion of the top surface of the film stack may be formed on the film stack. Next, a patterning process is performed on the film stack by the patterned photoresist layer 211 to sequentially pattern the bottom electrode layer 200, the resistive switching layer 202, the first barrier layer 204, the oxygen exchange layer 206, the second barrier layer 208, and the top electrode layer 210, so as to form a plurality of stack structures on the inter-metal dielectric layer 101. Each stack structure is a memory cell. Each stacked structure includes a bottom electrode 200', a resistive switching layer 202', a first barrier layer 204', an oxygen exchange layer 206', a second barrier layer 208', and a top electrode layer 210' sequentially stacked on the intermetal dielectric layer 101. Then, the patterned photoresist layer 211 may be removed by a process such as ashing or wet stripping.

In one embodiment, a photoresist layer may be formed on the film stack by, for example, a spin-on process, and the photoresist patterned by exposing the photoresist using an appropriate mask. The exposed or unexposed portions of the photoresist may then be removed, depending on whether a positive or negative photoresist is used, to form the patterned photoresist layer 211.

Next, referring to fig. 1C, a passivation layer 212 is conformally formed along the sidewalls of the stacked structures and on the top surface of the stacked structures, and a first isolation structure 214 is formed between each stacked structure. In some embodiments, the first isolation structures 214 are formed, for example, by first forming the insulating material blanket over the substrate 100, and then performing a planarization process on the insulating material until the passivation layer 212 on the stacked structures is exposed, so as to form the first isolation structures 214 between the stacked structures (see fig. 1C). In other embodiments, the planarization process may be performed until the top surface of the stacked structure is exposed (i.e., patterned)Top electrode layer 210') such that the top surface of the stacked structure is flush with the insulating material (not shown). In some embodiments, the planarization process may include a chemical mechanical polishing process or an etch back (etchback) process. The passivation layer 212 and the first isolation structure 214 comprise different materials, and the energy band difference between the two can prevent electron migration, thereby preventing adjacent memory cells from interfering with each other to ensure the functionality of the rram. The protective layer 212 may include a metal oxide, such as aluminum oxide (Al) ₂ O ₃ ) Or silicon nitride (SiN) ₄ ) And may be about 0.4nm to 1nm thick. The protection layer 212 may be formed by an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof. The first isolation structure 214 may comprise or be an insulating material, such as one of an oxide (e.g., silicon oxide), a nitride, or any combination thereof. The insulating material may be filled between the stacked structures by, for example, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or any suitable deposition technique.

As shown in fig. 1D, a patterned photoresist layer 215 is formed on the stacked structure. In some embodiments, the mask used to form the patterned photoresist layer 215 may be the same as the mask used to form the patterned photoresist layer 211 of FIG. 1B, without using an additional mask. For example, different types of photoresist are used to form a patterned photoresist layer 215 having a complementary pattern that is the inverse of the patterned photoresist layer 211 in FIG. 1B. In some embodiments, the patterned photoresist layer 211 is a positive photoresist and the patterned photoresist layer 215 is a negative photoresist. In other embodiments, an additional mask may be used to form the patterned photoresist layer 215.

With continued reference to fig. 1D, an insulating layer 217 is then formed on the patterned photoresist layer 215 by a suitable deposition process, such as chemical vapor deposition or atomic layer deposition. In some embodiments, the insulating layer 217 may include or be an oxide (e.g., silicon oxide), a nitride (nitride), or a combination thereof. As shown in FIG. 1D, the insulating layer 217 has a plurality of recesses 217A, wherein the bottom of the recesses 217A has a width W1, and the width W1 is about 1/20 to 3/20 of the width W2 of the top surface of the stacked structure.

Referring to fig. 1E, the stacked structure is etched by using the combination of the patterned photoresist layer 215 and the insulating layer 217 as an etching mask to form a groove 216. The recess 216 extends through the stacked structure to the bottom electrode 200 'and exposes a portion of the bottom electrode 200'. The groove 216 defines two physically separated wire units 218 and a top electrode 210A respectively located on each wire unit 218 in the stacked structure. As shown in fig. 1E, the electrical filament unit 218 includes a resistive switching structure 202", a first barrier structure 204", an oxygen exchange structure 206", a second barrier structure 208". The wire unit 218 is a wire transmission channel. The oxygen exchange structure 206 "may assist the resistive switching structure 202" in forming a wire. Specifically, after forming the electrical filaments in the resistive switching structure 202", free oxygen ions may be stored in the oxygen exchange structure 206". In addition, the first barrier structure 204 "and the second barrier structure 208" may help confine free oxygen ions in the oxygen exchange structure 206 "to allow more stable electrical wires to be formed in the electrical wire unit 218 and to provide the resistive random access memory with better electrical wire reproducibility. In some embodiments, the step of etching the stacked structure may include any suitable anisotropic dry etching process, such as reactive ion etching, neutral Beam Etching (NBE), or a combination thereof. Then, the patterned photoresist layer 215 and the insulating layer 217 are removed. For example, the patterned photoresist layer 215 may be removed using, for example, an ashing or a wet strip process. For example, the insulating layer 217 may be removed using, for example, a wet strip process or a suitable etch process. In some embodiments, the width of the groove 216 is about 1/20 to 3/20 of the width W2 of the stacked structure.

Although one recess 216 is shown in each stacked structure in fig. 1E, in other embodiments, more than two recesses 216 may be formed in each stacked structure. In other words, more than three wire units 218 may be defined in each stacked structure. For example, two grooves 216 may be formed in each stacked structure to form three wire units 218.

As shown in fig. 1F-1 and 1F-2, a second isolation structure 220 is formed in the recess 216 and an inter-metal dielectric layer 300 is formed on the stacked structure. In some embodiments, the second isolation structure 220 may include or be an insulating material, such as one of an oxide (e.g., silicon oxide), a nitride, or any combination thereof. In some embodiments, the intermetal dielectric layer 300 may include a material that is an oxide (e.g., silicon oxide, silicon dioxide), a nitride, a low-k dielectric material (e.g., a material with a dielectric constant lower than silicon dioxide), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorine-doped silicate glass, organosilicate glass, siOxCy, carbon-silicon material, combinations thereof, or any combination thereof. In some embodiments, the thickness of the IMD layer 300 may be in the range of about 200nm to about 400nm.

In some embodiments, as shown in FIG. 1F-1, the second isolation structure 220 and the IMD layer 300 may be formed in different steps. In this embodiment, the insulating material may be filled into the recess 216 by any suitable deposition process (e.g., HDP-CVD or FCVD) and the stacked structure may be covered by an excess of the insulating material. A planarization process (e.g., a chemical mechanical polishing process or an etch-back process) is then performed on the insulating material to remove the excess insulating material on the stacked structure, such that the top surface of the stacked structure is flush with the insulating material, thereby forming a second isolation structure 220 in the recess 216. Then, an intermetal dielectric layer 300 may be formed on the stacked structure and the second isolation structure 220 using any suitable deposition process.

In other embodiments, as shown in FIG. 1F-2, the second isolation structure 220' and the IMD layer 300 may be formed in the same deposition process. In this embodiment, the above-mentioned insulating material may be deposited at least on the stacked structure by any suitable deposition process to form the inter-metal dielectric layer 300 on the stacked structure. Compared to the deposition process described with respect to fig. 1F-1, a deposition process and/or parameters with high gap-filling capability may not be required, and thus the insulating material may not fill the recess 216 or may only partially fill the recess 216 to form a second isolation structure 220' comprising an air gap, as illustrated in fig. 1F-2. It should be noted that although the second isolation structure 220 is completely filled in the structure shown in fig. 1F-1, the second isolation structure 220 including an air gap may also be formed during the process.

Referring to fig. 1G, a conductive contact 302 is formed through the intermetal dielectric layer 300 and the passivation layer 212 corresponding to each top electrode 210A. Specifically, openings corresponding to and exposing the top electrodes 210A may be formed in the inter-metal dielectric layer 300 and the passivation layer 212 by photolithography and etching processes. Then, a liner layer (such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the opening. The liner layer may comprise titanium, titanium nitride, tantalum nitride. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel. A planarization process, such as a chemical mechanical polishing, may then be performed to remove the liner and conductive material on the intermetal dielectric layer 300 and form a conductive contact 302 in the opening, as shown in fig. 1G. In other embodiments, the conductive contact 302 may also be formed using, for example, a damascene process.

Next, referring to fig. 1H, a plurality of conductive layers 304 are formed on the inter-metal dielectric layer 300. In some embodiments, conductive layer 304 may be formed using a damascene process or a dual damascene process, among other methods. The conductive layer 304 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or similar material.

FIG. 1I is a diagram illustrating an example of a resistance random access memory 10 including a control device according to an embodiment of the present invention. As shown in fig. 1I, in addition to the structure shown in fig. 1H, the rram 10 further includes a transistor 400 formed on the substrate 100, source/drain regions 406 located at two sides of the transistor 400, a dielectric layer 104 between the substrate 100 and the inter-metal dielectric layer 101, a conductive layer 106 formed in the dielectric layer 104 for electrically connecting the conductive structure 102 to the source/drain regions 406, and a conductive structure 108.

In the embodiment shown in fig. 1A-1I, the rram includes a plurality of memory cells, wherein the memory cells are separated from each other by first isolation structures 214. Each memory cell includes a bottom electrode 200', a plurality of wire units 218 disposed on the bottom electrode 200', a top electrode 210A formed on each wire unit 218, a second isolation structure 220, and a protection layer 212 formed along sidewalls of the bottom electrode 200', the wire units 218, and the top electrode 210A that are coplanar. The material of the first isolation structure 214 is different from the material of the protection layer 212, and the energy band difference between the two materials can prevent electron migration, thereby preventing adjacent memory cells from interfering with each other and ensuring the functionality of the rram.

The wire units are physically separated from each other by a second isolation structure 220. Each electrical filament cell comprises a resistance converting structure 202 'located on the bottom electrode 200', a first barrier structure 204 'located on the resistance converting structure 202', an oxygen exchange structure 206 'located on the first barrier structure 204', and a second barrier structure 208 'located on the oxygen exchange structure 206'. With physically separate wire cells in each memory cell, multiple bits can be formed without increasing the volume of the memory cell. Therefore, when the sensing method is used together with the combined mode/differential mode, the occurrence rate of soft error bits can be reduced.

FIGS. 2A-2G are cross-sectional views illustrating different intermediate stages in the production of a RRAM, according to other embodiments. This embodiment is similar to the previous embodiments of FIGS. 1A-1I, except that in this embodiment, multiple wire cells in a single memory cell share a common top electrode. Details regarding this embodiment that are similar to previously described embodiments will not be repeated here.

Referring to fig. 2A, a substrate 100 is provided. Next, an inter-metal dielectric layer 101 is formed on the substrate 100. The IMD layer 101 comprises a conductive structure 102 for connecting the RRAM to active control elements and/or interconnect structures in the substrate 100. Next, a film stack is formed on the inter-metal dielectric layer 101, wherein the film stack may include a bottom electrode layer 200, a resistive switching layer 202, a first barrier layer 204, an oxygen exchange layer 206, and a second barrier layer 208, which are sequentially formed. The embodiment shown in FIG. 2A differs from the embodiment shown in FIG. 1A in that the top electrode layer 210 is not included in the film stack.

Next, the same or similar processes as described above with respect to fig. 1B-1E are performed to form the structure of fig. 2B. Referring to fig. 2B, as mentioned above, the groove 216 defines two physically separated electrical filament units 218 on the bottom electrode 200', and the electrical filament units 218 include a resistance conversion structure 202", a first barrier structure 204", an oxygen exchange structure 206", and a second barrier structure 208". As shown in fig. 2B, the protection layer 212 is along the coplanar sidewalls of the bottom electrode 200', the resistive switching structure 202", the first barrier structure 204", the oxygen exchange structure 206", and the second barrier structure 208", and is located on the top surface of the second barrier structure 208". In another embodiment, the protection layer 212 is only along the coplanar sidewalls of the bottom electrode 200', the resistive switching structure 202", the first barrier structure 204", the oxygen exchange structure 206", and the second barrier structure 208", but is not located on the top surface of the second barrier structure 208 "(not shown).

Next, referring to fig. 2C, a second isolation structure 220 is formed in the groove 216, and a top electrode layer 210 is formed on the wire unit 218. The process and materials for forming the top electrode layer 210A are similar to those in fig. 1A, and are not described herein again. The process and materials for forming the second isolation structure are similar to those in FIGS. 1F-1 and 1F-2, and are not repeated herein. Similar to those mentioned in FIGS. 1F-1 and 1F-2, the second isolation structure 220 may be an insulating material (FIG. 2C), or may include an air gap (not shown). For convenience, in the following fig. 2D-2G, only the second isolation structure 220 is illustrated as being completely filled.

Next, referring to fig. 2D, a patterning process is performed on the top electrode layer 210 by using a suitable patterned photoresist (not shown) to form a plurality of top electrodes 210B. As shown in FIG. 2D, each top electrode 210B corresponds to a bottom electrode 200', and covers two wire units 218 simultaneously.

It is noted that the mask used herein may be the same as the mask used in the previous step of forming the multiple stacked structures without using an additional mask. In other embodiments, when a plurality of second isolation structures 220 and a plurality of electric wire units 218 are formed on each stacked structure, the top electrode 210B covers the plurality of electric wire units 218 on the stacked structure at the same time.

Referring to fig. 2E, a third isolation structure 222 is formed between the top electrodes 210B and an inter-metal dielectric layer 300 is formed on the top electrodes 210B. In some embodiments, the third isolation structure 222 may include an insulating material, such as one or any combination of an oxide (e.g., silicon oxide), a nitride. The process and materials for forming the IMD 300 are similar to those shown in FIGS. 1F-1 and 1F-2, and are not repeated herein.

In some embodiments, the third isolation structure 222 and the inter-metal dielectric layer 300 may be formed in different steps. In this embodiment, the insulating material may be filled between the top electrodes 210B by a suitable deposition process (e.g., HDP-CVD or FCVD) such that the top electrodes 210B are covered by excess insulating material. A planarization process (e.g., a chemical mechanical polishing process or an etch-back process) is then performed to remove the excess insulating material on the top electrode 210B, so that the top surface of the top electrode 210B is flush with the insulating material, thereby forming a third isolation structure 222 between the top electrodes 210B. Next, the IMD layer 300 may be formed over the top electrode 210B using any suitable deposition process.

In other embodiments, the third isolation structure 222 and the IMD layer 300 may be formed in the same step. In this embodiment, the insulating material may be blanket formed on the substrate 100 to serve as the third isolation structure 222 and the inter-metal dielectric layer 300.

Referring to fig. 2F, conductive contacts 302 are formed through the intermetal dielectric layer 300 corresponding to the top electrodes 210B. Next, a plurality of conductive layers 304 are formed on the inter-metal dielectric layer 300. The process and materials for forming the conductive contact 302 and the conductive layer 304 are similar to those in fig. 1G and 1H, and are not repeated herein.

FIG. 2G shows an example of the RRAM 20 including control devices according to another embodiment of the present invention. In this embodiment, except that a plurality of electrical wire units in a single memory cell share a top electrode, other parts are similar to the embodiment of fig. 1I and are not repeated herein.

In the embodiment shown in fig. 2A-2G, the rram includes a plurality of memory cells, wherein the memory cells are separated from each other by first isolation structures 214. Each memory cell includes a bottom electrode 200', a plurality of wire cells 218 disposed on the bottom electrode 200', a top electrode 210B covering the plurality of wire cells 218, and a protective layer 212 formed along sidewalls coplanar with the bottom electrode 200' and the wire cells 218. The material of the first isolation structure 214 is different from the material of the protection layer 212, and the energy band difference between the two materials can prevent electron migration, thereby preventing adjacent memory cells from interfering with each other and ensuring the functionality of the rram.

The wire units 218 are physically separated from each other by at least one second isolation structure 220. Each electrical filament cell comprises a resistive switching structure 202 'located on the bottom electrode 200', a first barrier structure 204 'located on the resistive switching structure 202', an oxygen exchange structure 206 'located on the first barrier structure 204', and a second barrier structure 208 'located on the oxygen exchange structure 206'. Having physically separate wire cells in each memory cell allows multiple bits to be formed without increasing the volume of the memory cell. Therefore, when the sensing method is used together with the combination mode/differential mode, the occurrence rate of soft error bits can be reduced.

Although the embodiments shown in fig. 1A-1I and 2A-2G all show a plurality of wire units 218 sharing a bottom electrode, each wire unit 218 may have a separate bottom electrode. In other words, the plurality of wire units 218 may have independent top/common bottom electrodes (as shown in fig. 1I), common top/common bottom electrodes (as shown in fig. 2G), common top/independent bottom electrodes (not shown), or independent top/independent bottom electrodes (not shown).

The RRAM shown in FIG. 1I and FIG. 2G can be applied to solve the soft error bit problem of the RRAM with 1T1R structure. Multiple wire cells are formed in a single memory cell, and multiple bits can be formed without increasing the volume of the memory cell. Therefore, when the sensing method is used together with the combination mode/differential mode, the occurrence rate of soft error bits can be reduced. In addition, the protective layer formed on the side wall of the memory unit can form energy band difference with the isolation structure between the memory units, thereby avoiding the interference of the adjacent memory units and ensuring the functionality of the resistance random access memory.

The foregoing has outlined rather broadly the features of several embodiments of the present disclosure so that those skilled in the art may better understand the disclosure. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or achieving the same advantages of the embodiments of the present disclosure. It should also be understood that equivalent structures or processes may be substituted for those illustrated and described without departing from the spirit and scope of the present disclosure, and that such modifications, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method for forming a resistive random access memory includes

Forming a film stack, wherein the film stack comprises:

a bottom electrode layer; and

a resistance conversion layer located on the bottom electrode layer;

patterning the film stack to form a plurality of stack structures;

forming a protective layer along sidewalls of the plurality of stacked structures;

forming a first isolation structure between the plurality of stacked structures;

forming at least one groove in at least one stacking structure to define a plurality of physically separated electric wire units in the at least one stacking structure; and

and forming a second isolation structure in the at least one groove.

2. The method of claim 1, wherein the film stack further comprises:

a first barrier layer on the resistive switching layer;

an oxygen exchange layer located on the first barrier layer; and

a second barrier layer located on the oxygen exchange layer.

3. The method of claim 1, further comprising forming a plurality of conductive layers before forming the layer stack, each conductive layer electrically connected to one of the stack structures.

4. The method as claimed in claim 3, further comprising forming a plurality of transistors before forming the plurality of conductive layers, each transistor electrically connected to one of the plurality of stacked structures through each conductive layer.

5. The method of claim 2, wherein the film stack further comprises a top electrode layer on the second barrier layer, and wherein the step of forming the at least one recess further comprises forming a plurality of top electrodes on each of the plurality of wire units.

6. The method of claim 5, wherein the top electrodes are physically separated from each other.

7. The method of claim 1, further comprising:

after the at least one groove is formed, a top electrode structure is respectively formed on the plurality of stacked structures.

8. The method of claim 1, wherein the second isolation structure comprises an air gap.

9. The method of claim 1, wherein a material of the first isolation structure is different from a material of the passivation layer.

10. The method of claim 1, wherein the passivation layer comprises aluminum oxide or silicon nitride.

11. The method as claimed in claim 1, wherein the resistance switching layer comprises one or any combination of hafnium oxide, titanium oxide, tungsten oxide, tantalum oxide, and zirconium oxide.

12. The method as claimed in claim 2, wherein the oxygen exchange layer comprises one of Al and Ti or any combination thereof.

13. A Resistive Random Access Memory (RRAM) comprises

A plurality of stacked structures, wherein the plurality of stacked structures are respectively separated from each other by a first isolation structure, and wherein each stacked structure comprises:

a bottom electrode; and

a plurality of electrical wire units disposed on the bottom electrode and physically separated from each other by at least one second isolation structure, wherein the second isolation structure is in direct contact with two opposite sidewalls of the plurality of electrical wire units, and wherein each electrical wire unit includes a resistance transformation structure disposed on the bottom electrode; and

a protection layer along sidewalls of the stacked structures, wherein the sidewalls of the first isolation structure and the stacked structures are separated from each other by the protection layer.

14. The rram of claim 13 wherein the wire unit further comprises:

the first blocking structure is positioned on the resistance conversion structure;

an oxygen exchange structure located on the first barrier structure; and

a second barrier structure located on the oxygen exchange structure.

15. The rram of claim 13 further comprising a plurality of conductive layers, each electrically connected to one of the plurality of stacked structures.

16. The rram of claim 15 further comprising a plurality of transistors, each transistor electrically connected to one of the stack structures by a conductive layer.

17. The rram of claim 13 wherein each stack further comprises a plurality of top electrodes respectively disposed on the plurality of wire units.

18. The rram of claim 13 wherein each stack further comprises a top electrode on the plurality of wire units.

19. The resistive random access memory of claim 13 wherein the second isolation structure comprises an air gap.

20. The rram of claim 13 wherein the first isolation structure and the passivation layer are made of different materials.

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