CN117042445A - Memory device and method of manufacturing the same - Google Patents

Memory device and method of manufacturing the same Download PDF

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Publication number
CN117042445A
CN117042445A CN202310737247.0A CN202310737247A CN117042445A CN 117042445 A CN117042445 A CN 117042445A CN 202310737247 A CN202310737247 A CN 202310737247A CN 117042445 A CN117042445 A CN 117042445A
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China
Prior art keywords
layer
memory cell
memory device
stack
metal
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CN202310737247.0A
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Chinese (zh)
Inventor
刘朋骏
黄家恩
郑雅云
吴忠纬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/103,377 external-priority patent/US20240032274A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117042445A publication Critical patent/CN117042445A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Embodiments of the present invention provide a memory device including a semiconductor substrate. The memory device includes a channel layer stack over a semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with a channel layer stack. The memory device includes source and drain features on both sides of a channel layer stack. Embodiments of the present invention provide a method of manufacturing a memory device.

Description

Memory device and method of manufacturing the same
Technical Field
Embodiments of the present invention relate generally to the field of semiconductors, and more particularly, to memory devices and methods of fabricating the same.
Background
As the integration of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) continues to improve, the semiconductor industry has experienced a rapid growth. In most cases, this increase in integration comes from the ever decreasing minimum feature size, which allows more components to be integrated into a given area.
Disclosure of Invention
One embodiment of the present invention provides a memory device including: a semiconductor substrate; a channel layer stack over the semiconductor substrate, each channel layer comprising a conductive oxide material; a word line structure interleaved with the channel layer stack; and source and drain features located on both sides of the channel layer stack.
Another embodiment of the present invention provides a memory device including: a semiconductor substrate; and a memory cell over the semiconductor substrate, comprising: a stack of channel layers, each channel layer comprising a metal oxide; a word line structure surrounding each channel layer; and source and drain metal electrodes located on both sides of the channel layer stack.
Yet another embodiment of the present invention provides a method of manufacturing a memory cell, comprising: forming a stack of alternating sacrificial layers and channel layers over a substrate, the stack being oriented longitudinally along a first direction, wherein each channel layer comprises a metal oxide material; patterning the stack so as to form a groove in the stack, the groove being oriented longitudinally along the first direction; forming a source feature and a drain feature in the recess; selectively removing the sacrificial layer in the patterned stack to form openings between the channel layers; and forming a word line structure in the opening, wherein the word line structure surrounds each channel layer in the stack, the word line structure being oriented longitudinally along the first direction.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates a perspective view of an exemplary memory device, according to some embodiments.
FIG. 2 illustrates a perspective view showing a cross-section of a portion of the example memory device shown in FIG. 1 along line AA', in accordance with some embodiments.
FIG. 3 illustrates a top plan view of a portion of the example memory device shown in FIG. 1, in accordance with some embodiments.
Fig. 4 illustrates a cross-sectional view of a portion of the example memory device shown in fig. 1, taken along line BB', in accordance with some embodiments.
FIG. 5 illustrates exemplary waveforms associated with operating the exemplary memory device shown in FIG. 4, in accordance with some embodiments.
Fig. 6, 7, 8, 9, 10, 11, 12, and 13 illustrate cross-sectional views of portions of the example memory device shown in fig. 1 along line BB' according to some embodiments, respectively.
FIG. 14 is an example flowchart of a method for manufacturing an example memory device, according to some embodiments.
Fig. 15A, 16A, 17A, 20A, 21A, 22A, 23A, 24A, and 25A illustrate perspective views of an example memory device in various stages of manufacture of the method of fig. 14 in accordance with some embodiments.
Fig. 15B, 16B, 17B, 20B, 21B, 22B, 23B, 24B, and 25B illustrate cross-sectional views of an example memory device, such as shown in fig. 15A, 16A, 17A, 20A, 21A, 22A, 23A, 24A, and 25A, along line BB', during various stages of fabrication of the method of fig. 14, respectively, in accordance with some embodiments.
Fig. 18 and 19 illustrate cross-sectional views of an example memory device, such as shown in fig. 16A and 17A, respectively, along line BB' during various stages of fabrication of the method illustrated in fig. 14, in accordance with some embodiments.
Detailed Description
The invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Such as in the following description, forming the first component over or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms such as "under …," "under …," "lower," "over …," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The present disclosure is generally directed to back end of line (BEOL) memory devices and methods of fabricating the same. In particular, the present disclosure relates to BEOL memory devices having three-dimensional (3D) channel structures comprising stacked nano-sheets. While existing BEOL memory devices are generally adequate, they are not entirely satisfactory in all respects. For example, the planar channel structure of existing BEOL memory devices typically extends continuously between adjacent cells to avoid process problems. However, such a configuration may cause high current leakage between adjacent cells due to a potential difference between the source and the drain even when the gate is turned off. In addition, in a BEOL memory device having a planar channel structure, I is due to the smaller effective channel width on The (on-current) deficiency may be significant. Therefore, for at least these reasons, improvements in BEOL memory devices may be desirable.
Fig. 1 and 2 illustrate three-dimensional perspective views of a memory device 100 according to various embodiments of the present disclosure, respectively. It should be appreciated that the perspective views of fig. 1 and 2 are simplified, and thus, it should be understood that any other features/components may also be included in fig. 1 and 2 while remaining within the scope of the present disclosure.
As shown, the memory device 100 includes a number of memory cells 104 (e.g., four memory cells 104 are shown in the example of fig. 1) arranged as a memory array that extends in the X-direction and the Y-direction. It should be appreciated that in some embodiments, any number of such memory layers may be stacked upon one another (e.g., in the Z-direction) to form a memory array. Each memory cell 104 may include a stack of alternating WL structures and channel layers, wherein the WL structures act as gates to control the channel layers, and the channel layers are in electrical contact with a pair of source and drain features, the details of which will be discussed below.
In the present embodiment, the memory cell 104 includes a WL structure 150 over the semiconductor substrate 102, wherein the WL structure 150 extends continuously in the Y-direction (e.g., two WL structures 150 are shown in the example of fig. 1 and 2) and is separated from adjacent WL structures 150 in the X-direction. The memory cell 104 further includes a plurality of channel layers 110 electrically connected to the WL structures 150, wherein the channel layers 110 are interleaved with the WL structures 150 to form the stack 112 along the Z-direction. As shown in fig. 2, WL structure 150 wraps around each channel layer 110 within each memory cell 104, that is, channel layer 110 is discontinuous in the Y-direction between adjacent or neighboring memory cells 104. For at least this reason, the memory device 100 is referred to as a full-gate-all-around (GAA) device. In addition, since the channel layer 110 may be considered as a nano-sheet (or nano-rod), the memory device 100 may also be referred to as a nano-sheet (NS) device. Advantageously, the wrap-around structure allows the WL structure 150 to provide enhanced gate control to the channel layer 110, thereby mitigating potential leakage issues typically associated with planar memory devices for BEOL applications.
The semiconductor substrate 102 may include: elemental semiconductor materials such as silicon, germanium, diamond, other elemental semiconductor materials; compound semiconductor materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, indium gallium phosphide, other compound semiconductor materials, or combinations thereof. Several active/passive device components may be formed along the major surface of the semiconductor substrate 102 that collectively or individually function as logic circuits (e.g., transistors, capacitors, resistors, etc.).
One or more Intermetallic (IMD) layers may be embedded in a number of interconnect structures (e.g., leads, vias) to electrically connect them to device components formed over semiconductor substrate 102. Such device features formed along the major surface of semiconductor substrate 102 are commonly referred to as part of a FEOL networking/process, while those interconnect structures formed over device features of IMD layers are commonly referred to as part of a BEOL networking/process. In various embodiments, the memory device 100 disclosed herein is formed in BEOL networking. GAA devices including semiconductor (e.g., si-containing) channels may be formed along a major surface of the semiconductor substrate 102 as part of FEOL networking and electrically connected to the memory device 100 through various interconnect structures.
Still referring to fig. 1 and 2, wl structure 150 includes a conductive electrode (e.g., gate electrode) 154 over a dielectric layer (e.g., gate dielectric layer) 152. Dielectric layer 152 may include a metal oxide material, such as hafnium oxide (HfO 2 ) Silicon oxide (SiO) 2 ) Alumina (Al) 2 O 3 ) Silicon oxide (SiON), lanthanum oxide (La) 2 O 3 ) Zirconium oxide (ZrO), other suitable insulating materials, or combinations thereof. The conductive electrode 154 may include a conductive material such as copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), aluminum (Al), taN, tiN, tiAl, polysilicon, other suitable conductive materials, or combinations thereof. The conductive electrode 154 may include multiple layers, such as a metal fill layer over the barrier layer (and/or adhesion layer).
The number of channel layers 110 included in each stack 112 (i.e., in engagement with WL structure 150) is not limited by this embodiment, and may be three, four, fiveOr other suitable number. In some embodiments, the number of channel layers 110 is adjusted to provide various benefits to the performance of the memory device 100. For example, referring to fig. 2, the channel width W of each channel layer 110 is measured in the Y-direction (e.g., the length direction of the channel layer 110) within each memory cell 104. Thus, the effective channel width W 'of each memory cell 104 considers the channel width W and the number of channel layers 110 included in each memory cell 104, or W' to n×w, where n is the number of channel layers 110. In this regard, the GAA memory device 100 including three channel layers 110 in each memory cell 104 has a W' that is three times (3W) the channel width of its planar counterpart, the latter including only one channel layer. Similarly, four channel layers 110 will provide an effective channel width W' that is four times W (-4W), and so on. The increase in W' may increase I of the memory device 100 on( On-current) and in turn increases the selector charge rate of the device for high speed applications.
Unlike front-end-of-line (FEOL) GAA devices, the channel layer 110 of the memory device 100, which is a BEOL memory device, is typically configured with one or more metal oxide based semiconductor materials. For example, in some embodiments, each channel layer 110 may be configured as an N-type channel layer including Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2O 3), tin oxide (SnO 2), other suitable N-type metal oxide materials, or combinations thereof. In some embodiments, the channel layer 110 may be configured as a P-type channel layer including nickel oxide (NiO), copper oxide (Cu) 2 O), copper aluminum oxide (CuAlO) 2 ) Copper gallium oxide (CuGaO) 2 ) Copper indium oxide (CuInO) 2 ) Strontium copper oxide (SrCu) 2 O 2 ) Tin oxide (SnO), other suitable P-type metal oxide materials, or combinations thereof. Other metal oxide materials, such as indium tungsten oxide (IWO), indium Zinc Oxide (IZO), indium tungsten zinc oxide (IWZO), indium Tin Zinc Oxide (ITZO), indium Tin Oxide (ITO), and/or Indium Gallium Oxide (IGO), may also be included in the channel layer 110. In some embodiments, the oxygen concentration in the channel layer 110 may be adjusted to meet specific design requirements. In this embodiment, channel layer 110 is free or substantially free of any silicon-containing semiconductor material.
The memory cell 104 also includes a pair of drain features 140 and source features 142 (alternatively and collectively referred to as S/D features) disposed on each side of the WL structure 150 such that the channel layer 110 is interposed between the pair of S/D features. In the present disclosure, source feature 142 may alternatively be referred to as a source metal electrode, and drain feature 140 may alternatively be referred to as a drain metal electrode. As shown, the channel layer 110 connected to the WL structure 150 is in contact with a corresponding pair of drain features 140 and source features 142.
In this embodiment, the drain feature 140 and the source feature 142 include the same composition, and may include a plurality of material layers. For example, still referring to fig. 1 and 2, each of the drain feature 140 and the source feature 142 includes a contact layer 130, a metal layer 132 over the contact layer 130, and a metal layer 134 over the metal layer 132.
In this embodiment, the contact layer 130 includes a material similar to the channel layer 110 discussed in detail above. For example, the contact layer 130 may include an N-type metal oxide material, a P-type metal oxide material, other suitable materials, or combinations thereof. In some embodiments, the contact layer 130 includes the same type of metal oxide material as the channel layer 110. In a further embodiment, the oxygen concentration of each of the drain feature 140 and the source feature 142 is less than the oxygen concentration of the channel layer 110. For example, the oxygen concentration of the channel layer 110 may be about 10 18 Cm of -3 To about 10 20 Cm of -3 While the oxygen concentration of each of the drain feature 140 and the source feature 142 may be about 10 15 Cm of -3 To about 10 17 Cm of -3 . In some embodiments, the contact layer 130 is configured to reduce the contact resistance between the channel layer 110 and each of the drain feature 140 and the source feature 142. In some embodiments, the contact layer 130 is configured to prevent hydrogen generated by a subsequent device manufacturing process from entering the channel layer 110.
In this embodiment, the metal layers 132 and 134 each comprise a conductive material, such as TaN, tiN, W, al, polysilicon, ru, co, cu, mo, nb, other suitable conductive materials, or combinations thereof, and the composition of the metal layers 132 and 134 are different. In some embodiments, metal layer 134 includes a conductive material having a lower contact resistance than metal layer 132. For example, in the depicted embodiment, metal layer 132 comprises TiN and metal layer 134 comprises W. In some cases, metal layer 132 may be considered a barrier layer and metal layer 134 may be considered a metal fill layer. In some embodiments, the composition of metal layers 132 and 134 is different from the composition of conductive electrode 154.
In some embodiments, adjacent memory cells 104 are laterally separated by a dielectric layer, as depicted in fig. 1 and 2. For example, adjacent memory cells 104 are separated by dielectric layer 120 in the Y-direction, while adjacent memory cells 104 are separated by dielectric layer 126 in the X-direction, and dielectric layer 126 may be similar in composition to dielectric layer 120. Dielectric layers 120 and 126 may each comprise a silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectric material, such as SiCOH, siOCN, and/or SiOC, other suitable material, or combinations thereof. The low-k dielectric material refers to a dielectric material having a dielectric constant lower than 3.9. In some embodiments, for example as depicted in fig. 6 and 7, adjacent memory cells 104 are separated in the X-direction by stack 112, rather than by dielectric layer 126.
Each memory cell 104 of the memory device 100 may be defined as a combination of a WL structure 150, a plurality of channel layers 110 in the stack 112 interleaved with the WL structure 150, and a pair of drain features 140 and source features 142 joined to the channel layers 110. Such a memory cell 104 may be implemented as a transistor structure (sometimes referred to as a single transistor (1T) structure) having a gate, a gate oxide/dielectric, a semiconductor channel, a source, and a drain. WL structure 150, plurality of channel layers 110, drain feature 140 and source feature 142 may function as the gate, semiconductor channel, drain and source, respectively, of memory cell 104.
Fig. 3 depicts a top view of a portion of the memory device 100 as shown in fig. 1 and 2, the memory device 100 including two memory cells 104 arranged adjacent to each other. Each memory cell 104 is defined by a cell width Sx in the X-direction and a cell height Sy in the Y-direction. In some embodiments, the cell width Sx may vary according to design requirements. As shown for each memory cell 104, drain feature 140 is electrically connected to Bit Line (BL) structure 180 through one or more vias 170, and source feature 142 is electrically connected to storage capacitor 200 (e.g., as depicted in fig. 25A and 25B) through one or more vias 190. In this regard, WL structures 150 (and channel layer 110) are aligned longitudinally (i.e., elongated) along the Y-direction, and BL structures 180 are oriented longitudinally along the X-direction. In the depicted embodiment, adjacent memory cells 104 are separated by dielectric layer 126 in the X-direction such that vertical cell boundaries in the Y-direction extend through dielectric layer 126.
Fig. 4 illustrates an embodiment of a memory device 100 that includes three adjacent memory cells 104 arranged in the X-direction, wherein each memory cell 104 includes a stacked structure of three channel layers 110, similar to the embodiment depicted in fig. 1 and 2. Memory cell 104 includes WL structure 150, represented by WL0, WL1 and WL2, in engagement with their respective source members 142 (connected to respective storage capacitors S0, S1 and S2) and corresponding drain members 140. The drain feature 140 of each memory cell 104 is connected to a BL structure 180 that includes a metal layer 184 over a metal layer 182 through via 170, and the via structure includes a metal layer 174 over metal layer 172. In some examples, metal layers 172, 174, 182, and 184 may include similar conductive materials as metal layers 132 and 134, respectively, discussed in detail above.
Fig. 5 illustrates example waveforms 250 associated with the operation of the memory device 100 shown in fig. 4. In the depicted embodiment, WL1 of the selected memory cell 104 (center in FIG. 4) is turned on to generate an on-current, or I on While WL0 and WL2 of the unselected memory cells 104 are turned off. The BL structure 180 of the selected memory cell 104 is biased under various conditions to effect read and write operations. In some embodiments, an increase in the effective channel width W ', where W' to n W, may increase I on Thereby improving the charging speed of the memory device 100 for high-speed applications. In some embodiments, the stacked channel layer 110 wrapped by the WL structure 150 provides greater gate control within each memory cell 104, resulting in reduced leakage, i.e., reduced I off To enhance device performance.
Various embodiments of the memory device 100 are discussed in the following figures 6-13, which depict cross-sectional views of the memory cell 104 as shown in figure 1 along line BB'. It should be noted that the various embodiments depicted in fig. 6-13 may be modified according to specific design requirements. Further, in each of fig. 6-13, three adjacent memory cells 104 are shown, wherein the memory cells 104 include their respective WL structures 150, denoted WL0, WL1 or WL2, each of which is joined to the channel layer 110 and is interposed between a pair of drain features 140 (connected to a common BL structure 180) and source features 142 (connected to respective storage capacitors S0, S1 and S2, not shown).
The memory device 100 depicted in fig. 1-4 is a three-layer (or three-piece) GAA memory device, i.e., three channel layers 110 interleaved with WL structures 150 to form each stack 112. The memory device 100 depicted in fig. 6 is similar to fig. 1-4 in the number of channel layers 110 in the stack 112. However, unlike the descriptions of fig. 1-4, fig. 6 shows that the dielectric layer 126 between two adjacent memory cells 104 is replaced by a stack 113 that includes WL structures 150 interleaved with the channel layer 110, the WL structures 150 being configured as isolation gates (g_iso). In other words, stacks 112 each including WL structures 150 (e.g., WL0, WL1, WL2, etc.) are alternately arranged with stacks 113 along the X-direction. In this regard, the vertical cell boundaries extend through each stack 113 (i.e., each g_iso) rather than through the dielectric layer 126 as described in fig. 1-4. Advantageously, when a negative voltage is applied to g_iso, the channel layer 110 in the stack 113 is controlled by g_iso to prevent leakage of the memory device 100.
The memory device 100 depicted in fig. 7 is similar to those of fig. 1-4 in the number of channel layers 110 in the stack 112. However, unlike the descriptions of fig. 1-4, fig. 7 shows that each memory cell 104 includes a drain feature 140 that is shared with an adjacent memory cell 104, such that these drain features 140 are each referred to as a common drain feature (or common drain electrode). In this regard, each memory cell 104 includes a WL structure 150, the WL structure 150 connecting two adjacent stacks 112 together in a double gate structure 114. As shown, each of WL0, WL1 and WL2Effectively comprising a two-sided channel joined with a pair of source features 142 (connected to respective storage capacitors S0, S1 and S2) and drain features 140 (connected to BL structure 180), wherein each vertical cell boundary extends through drain feature 140. Advantageously, the double sided channel provides a greater I in each memory cell 104 than the memory cells 104 depicted in fig. 1-4 and 6 on( For example, approximately doubled) without enlarging the cell pitch.
The memory device 100 depicted in each of fig. 8-10 is a four-layer GAA memory device, i.e., four channel layers 110 interleaved with WL structures 150 to form each stack 112. Thus, the memory device 100 of fig. 8-10 demonstrates at least the advantage of an increased effective channel width W' compared to the memory device 100 depicted in fig. 1-4, 6 and 7, which is approximately four times the channel width of the planar counterpart to enhance I on Performance.
Similarly, the memory device 100 depicted in each of fig. 11-13 is a five-layer GAA memory device, i.e., five channel layers 110 interleaved with WL structures 150 to form each stack 112. Accordingly, the memory device 100 of fig. 11-13 exhibits at least an increased W as compared to the memory device 100 depicted in fig. 1-4, 6 and 7 eff Which is approximately five times that of the planar counterpart to enhance Ion performance.
Fig. 8 and 9 depict embodiments similar to those described with respect to each of fig. 1-4, respectively, in which adjacent memory cells 104 are separated by a dielectric layer 126. Fig. 9 and 11 depict embodiments similar to those depicted in fig. 6, respectively, in which adjacent memory cells 104 are separated by an isolation gate g_iso. FIGS. 10 and 13 respectively depict an embodiment similar to that depicted in FIG. 7, wherein the WL structure of each memory cell 104 is a double-gate structure 114 configured to provide a double-sided channel to enhance I on Performance.
In some embodiments, during operation of the memory device 100, the voltage V1 applied to bias the selected WL structure 150 exceeds the voltage required to implement Ion of the device, and the voltage V2 applied to bias the unselected WL structure 150 is less than the voltage required to implement Ion, V2 being less than V1. For embodiments in which the memory device 100 includes an isolated gate G_ISO (see, e.g., FIGS. 6, 9, and 12), an additional voltage V3 is applied to bias G_ISO, where V3 is less than V2 and is typically a negative voltage.
Fig. 14 illustrates a flowchart of a method 300 of forming a memory device according to various embodiments of the present disclosure. For example, at least some operations (or steps) of method 300 may be performed to fabricate, or otherwise form a memory device (e.g., memory device 100 of fig. 1). The method 300 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be appreciated that additional operations may be provided before, during, and after the method 300 of fig. 14, and thus some other operations may be described only briefly herein.
In various embodiments, the operations of the method 300 may be associated with the perspective views of the exemplary memory device 100 shown in fig. 15A-25B at various stages of fabrication, wherein fig. 15A, 16A, 17A, 20A, 21A, 22A, 23A, 24A, and 25A are three-dimensional perspective views of the memory device 100, and fig. 15B, 16B, 17B, 18, 19, 20B, 21B, 22B, 23B, 24B, and 25B are cross-sectional views of portions of the memory device 100 as shown in their respective perspective views along line BB'.
Referring to fig. 14, 15A and 15B, the method 300 forms a stack 111 of alternating sacrificial layers 106 and channel layers 110 over a semiconductor substrate 102 at operation 302, wherein the stack 111 is longitudinally oriented in a Y-direction and separated by trenches 124 in an X-direction.
In this embodiment, each sacrificial layer 106 comprises an insulating or dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable dielectric material, or a combination thereof. The composition of the channel layer 110 has been discussed in detail above. For example, the channel layer 110 may include one or more metal oxide semiconductor materials, but may be free or substantially free of any silicon-containing semiconductor material. In this embodiment, the dielectric layer 106 is compositionally different from the channel layer 110 to ensure sufficient etch selectivity therebetween. In some examples, the sacrificial layer 106 may include silicon oxide instead of the metal oxide of the channel layer 110.
To form stack 111, method 300 first deposits alternating sacrificial layers 106 and channel layers 110 to form a layered structure (not depicted) using a deposition method, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), other suitable methods, or combinations thereof. The method 300 then defines a channel width W (also depicted in fig. 2) in the channel layer 110 by performing a patterning process to form trenches (not depicted) in the layered structure, wherein the trenches are longitudinally oriented in the X-direction and are spaced apart from each other by the channel width W in the Y-direction.
The trenches may be formed by depositing a masking layer (e.g., photoresist) over the layered structure, patterning the masking layer using a suitable lithographic process (e.g., by photolithography, electron beam lithography, or any other suitable lithographic process) to form a patterned masking layer, and then performing a series of etching processes to transfer the pattern on the patterned masking layer onto the layered structure. The etching process may include a plasma etching process, a wet etching process, a Reactive Ion Etching (RIE) process, other suitable processes, or combinations thereof, which may have certain anisotropic properties. In other embodiments, the hard mask may be patterned with a mask layer and then the pattern transferred to the layered structure. After patterning the layered structure to form trenches defining the channel width W, the patterned mask layer is removed by a suitable method, such as plasma ashing or resist stripping.
Subsequently, the method 300 deposits a dielectric layer 120 over the patterned layered structure to fill the trenches, thereby longitudinally orienting the dielectric layer 120 in the X-direction. Then, the dielectric layer 120 may be planarized by a chemical mechanical polishing/planarization (CMP) process or the like such that the dielectric layer 120 is embedded in the stack 111. In this embodiment, the dielectric layer 120 is configured to isolate adjacent memory cells 104 along the Y-direction. Dielectric layer 120 may be formed by a deposition method such as CVD, flowable CVD (FCVD), spin-on, other suitable methods, or a combination thereof. In this embodiment, the composition of the dielectric layer 120 and the sacrificial layer 106 are different to ensure sufficient etch selectivity therebetween.
The layered structure with embedded dielectric layer 120 is then patterned again to form trenches 124 shown in fig. 15A and 15B, with a process similar to the patterning process discussed above for forming trenches in the layered structure. The grooves 124 separate the layered structure into stacks 111, which are oriented longitudinally in the Y-direction and are spaced apart from each other in the X-direction.
Referring to fig. 14, 16A and 16B, the method 300 forms S/D grooves 128 between stacks 111 at operation 304.
In some embodiments, forming S/D grooves 128 includes first filling trenches 124 with dielectric layer 126 and then planarizing dielectric layer 126 with a CMP process to expose topmost sacrificial layer 106 in stack 111, as depicted in fig. 16A and 16B. Dielectric layer 126 may be similar in composition to dielectric layer 120 and may be formed by deposition methods such as CVD, FCVD, spin-on, other suitable methods, or combinations thereof.
Then, the stack 111 is patterned to form S/D grooves 128 such that each S/D groove 128 is interposed between the patterned stack 111 and portions of the dielectric layer 126. In this regard, the patterned stack 111 defines a gate length L along the X-direction. The stack 111 may be patterned in a process similar to that discussed above with respect to forming trenches in a layered structure.
In an alternative embodiment, referring to fig. 18, s/D grooves 128 are formed by directly patterning stack 111 at operation 302 after depositing and planarizing dielectric layer 120, i.e., the formation of trenches 124 at operation 302 and the formation of dielectric layer 126 at operation 304 are omitted. In this regard, each S/D groove 128 is interposed between two patterned stacks 111.
Referring to fig. 14, 17A, 17B, and 19, the method 300 forms S/D features, i.e., drain features 140 and source features 142, in the S/D grooves 128 at operation 306 such that each patterned stack 111 is interposed between a pair of drain features 140 and source features 142.
In this embodiment, forming S/D features 140/142 includes conformally depositing contact layer 130 in S/D grooves 128, conformally depositing metal layer 132 over contact layer 130, and depositing metal layer 134 over metal layer 132 to fill S/D grooves 128. The composition of each of contact layer 130, metal layer 132, and metal layer 134 has been discussed in detail above. The layers of the S/D components 140/142 may be deposited by any method, such as CVD, ALD, PVD, electroless plating, electroplating, other suitable methods, or combinations thereof. Portions of contact layer 130, metal layer 132, and metal layer 134 formed on the top surface of patterned stack 111 may then be removed by one or more CMP processes to expose the topmost sacrificial layer 106, completing the formation of S/D features 140/142.
In the depicted embodiment of fig. 17B, the drain feature 140 of a memory cell 104 is separated from the source feature 142 of an adjacent memory cell 104 by a dielectric layer 126. In some embodiments, referring to fig. 19, two adjacent memory cells 104 are adjacent along one patterned stack 111, and portions of the patterned stack 111 are then replaced with WL structures 150, such that the two adjacent memory cells 104 are separated by a conductive gate structure. The conductive gate structure may be configured as the isolation gate g_iso described in fig. 6, 9, and 12, or as part of the dual gate structure 114 described in fig. 7, 10, and 13. For simplicity, the subsequent operations of method 300 are discussed with reference to the embodiment provided in fig. 17A and 17B, but in accordance with certain aspects of the present disclosure, these operations also apply to the embodiment depicted in fig. 19.
Referring to fig. 14, 20A and 20B, the method 300 selectively removes the sacrificial layer 106 from the patterned stack 111 to form openings 146 interleaved with the channel layer 110 at operation 308.
The sacrificial layer 106 may be removed by a selective etching process that removes the sacrificial layer 106 without removing or substantially without removing the channel layer 110 or other surrounding components of the memory device 100. The selective etching process may be implemented as a plasma etching process, a wet etching process, a RIE process, other suitable processes, or a combination thereof.
Referring to fig. 14, 21A and 21B, the method 300 forms the WL structure 150 in the opening 146 at operation 310. Accordingly, WL structure 150 is interleaved (or surrounding) with channel layer 110 and is joined with a pair of drain feature 140 and source feature 142 to form memory cell 104.
In this embodiment, WL structure 150 includes at least a dielectric layer 152 and a conductive electrode 154 over dielectric layer 152, the composition of which is discussed in detail above. The dielectric layer 152 and the conductive electrode 154 may each be formed by a deposition process, such as CVD, ALD, PVD, electroless plating, electroplating, or a combination thereof. Other material layers, such as an adhesive layer, may be formed over the dielectric layer 152 prior to forming the conductive electrode 154 or portions thereof. Subsequently, one or more CMP processes may be performed on portions of dielectric layer 152 and conductive electrode 154 formed over the top surface of dielectric layer 126 to complete the formation of WL structure 150 in opening 146. In this embodiment, the top surface of the WL structure 150 is formed planar with the top surface of the S/D feature 140/142.
Referring to fig. 14, 22A and 22B, the method 300 forms a via 170, which is a vertical interconnect structure, configured to electrically connect each drain feature 140 to the BL structure 180 at operation 312. In this regard, the VIA 170 may alternatively be referred to as a BL VIA.
In this embodiment, forming the via 170 includes first forming a dielectric layer 160 over the WL structure 150 of the plurality of memory cells 104. Dielectric layer 160 may be similar in composition to dielectric layer 120 and may be formed by deposition methods such as CVD, FCVD, spin-on, other suitable methods, or combinations thereof. In some examples, an etch stop layer (ESL; not depicted) may be formed over WL structure 150 prior to forming dielectric layer 160. The ESL includes a dielectric material different from dielectric layers 160, 126, and 120 to ensure adequate etch selectivity when performing subsequent etching processes.
Subsequently, a via 170 is formed in dielectric layer 160 by a suitable process, such as a dual damascene process, which may include a metal layer 172 and a metal layer 174 over metal layer 172. Metal layers 172 and 174 may include similar compositions as metal layer 132 and metal layer 134 discussed in detail above. For example, metal layer 172 may comprise TiN and metal layer 134 may comprise W. In some cases, metal layer 132 may be considered a barrier layer and metal layer 134 may be considered a metal fill layer.
The dual damascene process may generally include: patterning the dielectric layer 160 to form openings (not depicted) extending vertically to expose the underlying drain features 140; depositing one or more conductive materials in the opening; and a planarization process, such as a CMP process, is performed to remove any excess conductive material. The conductive material may be deposited by any suitable method, such as CVD, PVD, ALD, electroless plating, electroplating, or combinations thereof.
Referring to fig. 14, 23A and 23B, the method 300 forms a BL structure 180, i.e., a horizontal interconnect structure, electrically connected to the drain member 140 through the via 170 at operation 314. In this embodiment, the BL structures 180 may be regarded as global BL structures, extending in the X direction, and spaced apart from each other in the Y direction.
In this embodiment, forming BL structure 180 includes first forming dielectric layer 176 over dielectric layer 160. Dielectric layer 176 may be similar in composition to dielectric layer 120 and may be formed by deposition methods such as CVD, FCVD, spin-on, other suitable methods, or combinations thereof. In some examples, an ESL may be formed over dielectric layer 160 prior to forming dielectric layer 176. The ESL includes a dielectric material that is different from dielectric layers 176 and 160 to ensure adequate etch selectivity when performing subsequent etching processes.
BL structure 180 may include a metal layer 184 over metal layer 182, respectively. Metal layers 182 and 184 may include similar compositions as metal layer 132 and metal layer 134 discussed in detail above. For example, metal layer 182 may comprise TiN and metal layer 184 may comprise W. In some cases, metal layer 182 may be considered a barrier layer and metal layer 184 may be considered a metal fill layer. BL structure 180 is formed in a manner similar to via 170, for example by a dual damascene process as discussed in detail above, and then planarized using one or more CMP processes. In some examples, BL structure 180 and via 170 may be formed together by a dual-dual damascene process.
Referring to fig. 14, 24A and 24B, the method 300 forms a via 190 to electrically connect each source feature 142 to a subsequently formed storage capacitor 200 at operation 316. In this regard, the via 190 may alternatively be referred to as a CVIA.
In this embodiment, the via 190 is similar in structure and method of formation to the via 170. For example, via 190 may include a metal layer 192 and a metal layer 194 over metal layer 192, which may be similar in composition to metal layers 134 and 132 discussed above. In addition, the via 190 may be formed by a process similar to the via 170 discussed above. For example, dielectric layer 188 is formed over dielectric layer 176 by a suitable deposition method as discussed above, and a dual damascene process may be performed, for example, to form vias 190 in dielectric layers 188, 176, and 160. Subsequently, one or more CMP processes may be performed to expose the top surface of dielectric layer 188.
Referring to fig. 14, 25A and 25B, the method 300 forms storage capacitors 200 at operation 318, each of which is electrically connected to the source feature 142 through the via 190. In this regard, the via 190 may alternatively be referred to as a CVIA.
In some embodiments, forming storage capacitor 200 includes first forming dielectric structure 192 over dielectric layer 188 (and via 190). Dielectric structure 192 may be a layered structure including dielectric layer 194, dielectric layer 196 over dielectric layer 194, and dielectric layer 198 over dielectric layer 196, wherein dielectric layers 194, 196, and 198 may be compositionally different. Dielectric layers 194, 196 and 198 may each comprise a suitable dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ) Dielectric materials having a low dielectric constant (low-k) include SiCOH, siOCN, and/or SiOC, other suitable materials, or combinations thereof. The dielectric structure 192 may include fewer, more, or different layers, such as those provided herein. Dielectric layers 194, 196 and 198, respectively, may be formed by deposition methods such as CVD, FCVD, ALD, PVD, spin-on, other suitable methods, or combinations thereof.
Subsequently, openings (not depicted) are formed in the dielectric structure 192 to expose the vias 190, wherein each opening corresponds to a storage capacitor 200. Each storage capacitor 200 may include a bottom plate 202, a capacitor dielectric layer 204 over the bottom plate 202, and a top plate 206 over the capacitor dielectric layer 204. Each of the bottom plate 202 and top plate 204 may include a conductive material, such as TaN, tiN,W, al, ru, co, cu, mo, nb, other suitable conductive materials, or combinations thereof, while the capacitor dielectric layer 204 can comprise a suitable dielectric material, such as a dielectric material having a high dielectric constant (high-k), including hafnium oxide (HfO) 2 ) Alumina (Al) 2 O 3 ) Tantalum silicon oxide (Ta) 2 O 5 ) Zirconium oxide (ZrO) 2 ) Other suitable dielectric materials, or combinations thereof. Each layer of the storage capacitor 200 may be formed by a suitable method, such as CVD, ALD, PVD, electroless plating, electroplating, or a combination thereof.
Further, the method 300 may perform additional operations at operation 320. For example, additional interconnect features, such as vias and wires, may be formed over the memory device 100 according to various design requirements.
The present disclosure provides various embodiments of BEOL memory devices having three-dimensional nanoplatelet-based channel structures. In many embodiments, the BEOL memory device includes a stack of channel layers (i.e., nanoplatelets) bonded to a word line structure that serves as the gate of the device and is interposed between source and drain features. The channel layer includes a conductive oxide material. The word line structure may further include a metal fill layer disposed over the dielectric layer. In some embodiments, the device is disposed over a FEOL device formed along a surface of an underlying substrate. In some embodiments, the drain feature is further connected to the bit line structure through a first via and the source feature is further connected to the storage capacitor through a second via. By forming the word line structure to surround the plurality of channel layers in the stack, gate control of the memory device is improved, and an effective channel width of the memory device increases according to the number of channel layers included in the stack and the gate control, resulting in an enhancement of on-current of the memory device for high-speed applications.
In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a semiconductor substrate. The memory device includes a stack of channel layers on a semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with the channel layer stack. The memory device includes source and drain features on both sides of a channel layer stack.
In some embodiments, each channel layer is an N-type channel layer, and the conductive oxide material includes Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) Tin oxide (SnO) 2 ) Or a combination thereof.
In some embodiments, each channel layer is a P-type channel layer, and the conductive oxide material includes nickel oxide (NiO), copper oxide (Cu 2 O), aluminum copper oxide (CuAlO) 2 ) Gallium copper oxide (CuGaO) 2 ) Copper indium oxide (CuInO) 2 ) Strontium copper oxide (SrCu) 2 O 2 ) Tin oxide (SnO) or a combination thereof.
In some embodiments, the conductive oxide material is a first conductive oxide material, and the source and drain features each include a metal layer over a contact layer that includes a second conductive oxide material.
In some embodiments, the first conductive oxide material is the same as the second conductive oxide material.
In some embodiments, the first conductive oxide material includes a first oxygen concentration, the second conductive oxide material includes a second oxygen concentration, and the second oxygen concentration is less than the first oxygen concentration.
In some embodiments, the memory device further comprises: a dielectric layer is disposed along sidewalls of each of the source feature and the drain feature.
In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a semiconductor substrate and a memory cell over the semiconductor substrate. The memory cell includes a stack of channel layers, each channel layer including a metal oxide. The memory cell includes a word line structure surrounding each channel layer. The memory cell includes a source metal electrode and a drain metal electrode on both sides of a channel layer stack.
In some embodiments, the memory cell is a first memory cell, the memory device further comprises a second memory cell adjacent to the first memory cell, and the first memory cell and the second memory cell are separated by a dielectric layer.
In some embodiments, the memory cell is a first memory cell, the memory device further comprises a second memory cell adjacent to the first memory cell, and the drain metal electrode of the first memory cell is a drain electrode common between the first memory cell and the second memory cell.
In some embodiments, the memory cell is a first memory cell, the word line structure is a first word line structure, and the memory cell further includes a second word line structure disposed at a cell boundary.
In some embodiments, the memory device further comprises: and the bit line structure is electrically connected with the drain electrode metal electrode through a first through hole, and the storage capacitor is electrically connected with the source electrode metal electrode through a second through hole.
In some embodiments, the metal oxide is a first metal oxide and the source metal electrode and the drain metal electrode each include a contact layer having a second metal oxide.
In some embodiments, the metal oxide is a first metal oxide, the word line structure includes a conductive electrode over a dielectric layer having a second metal oxide, the first metal oxide and the second metal oxide having different compositions.
In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed. The method includes forming a stack of alternating sacrificial layers and channel layers on a substrate, the stack being oriented longitudinally along a first direction, wherein each channel layer includes a first metal oxide material. The method includes patterning the stack to form a groove in the stack, the groove oriented longitudinally along a first direction. The method includes forming a source feature and a drain feature in a recess. The method includes selectively removing the sacrificial layer in the patterned stack to form openings between the channel layers. The method includes forming a word line structure at the opening, wherein the word line structure surrounds each channel layer in the stack, the word line structure being oriented longitudinally along a first direction.
In some embodiments, the metal oxide material is a first metal oxide material, and forming the source feature and the drain feature comprises: depositing a contact layer in the recess, wherein the contact layer comprises a second metal oxide material that differs from the first metal oxide material in oxygen concentration; forming a first metal layer over the contact layer; and forming a second metal layer over the first metal layer to fill the recess.
In some embodiments, the first metal oxide material and the second metal oxide material each comprise Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) Tin oxide (SnO) 2 ) Nickel oxide (NiO), copper oxide (Cu) 2 O), aluminum copper oxide (CuAlO) 2 ) Gallium copper oxide (CuGaO) 2 ) Copper indium oxide (CuInO) 2 ) Strontium copper oxide (SrCu) 2 O 2 ) Tin oxide (SnO) or a combination thereof.
In some embodiments, forming the stack includes forming a dielectric layer embedded in the stack, the dielectric layer extending vertically through the stack and being oriented longitudinally in a second direction perpendicular to the first direction, and a length of a portion of the stack adjacent the dielectric layer determining a channel width of the memory cell.
In some embodiments, the method further comprises: a dielectric layer is formed over the sidewalls of the stack in a first direction prior to patterning the stack such that each recess is formed between the patterned stack and the dielectric layer.
In some embodiments, the method further comprises: forming a first via to directly contact the drain member; forming a bit line structure to directly contact the first via, electrically connecting the bit line structure with the drain feature, the bit line structure being longitudinally oriented along a second direction perpendicular to the first direction; forming a second via to directly contact the source feature; and forming a storage capacitor to directly contact the second via, thereby electrically connecting the storage capacitor with the source part.
As used herein, the terms about and about generally refer to plus or minus 10% of the value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A memory device, comprising:
a semiconductor substrate;
a channel layer stack over the semiconductor substrate, each channel layer comprising a conductive oxide material;
a word line structure interleaved with the channel layer stack; and
source and drain features are located on either side of the channel layer stack.
2. The memory device of claim 1, wherein each channel layer is an N-type channel layer and the conductive oxide material comprises Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) Tin oxide (SnO) 2 ) Or a combination thereof.
3. The memory device of claim 1, wherein each channel layer is a P-type channel layer and the conductive oxide material comprises nickel oxide (NiO), copper oxide (Cu 2 O), aluminum copper oxide (CuAlO) 2 ) Oxidation ofGallium copper (CuGaO) 2 ) Copper indium oxide (CuInO) 2 ) Strontium copper oxide (SrCu) 2 O 2 ) Tin oxide (SnO) or a combination thereof.
4. The memory device of claim 1, wherein the conductive oxide material is a first conductive oxide material, and the source and drain features each comprise a metal layer over a contact layer comprising a second conductive oxide material.
5. The memory device of claim 4, wherein the first conductive oxide material is the same as the second conductive oxide material.
6. A memory device, comprising:
a semiconductor substrate; and
a memory cell over the semiconductor substrate, comprising:
a stack of channel layers, each channel layer comprising a metal oxide;
a word line structure surrounding each channel layer; and
a source metal electrode and a drain metal electrode are located on both sides of the channel layer stack.
7. The memory device of claim 6, wherein the memory cell is a first memory cell, the memory device further comprises a second memory cell adjacent to the first memory cell, and the first memory cell and the second memory cell are separated by a dielectric layer.
8. The memory device of claim 6, wherein the memory cell is a first memory cell, the memory device further comprises a second memory cell adjacent to the first memory cell, and the drain metal electrode of the first memory cell is a drain electrode common between the first memory cell and the second memory cell.
9. A method of manufacturing a memory cell, comprising:
forming a stack of alternating sacrificial layers and channel layers over a substrate, the stack being oriented longitudinally along a first direction, wherein each channel layer comprises a metal oxide material;
patterning the stack so as to form a groove in the stack, the groove being oriented longitudinally along the first direction;
forming a source feature and a drain feature in the recess;
selectively removing the sacrificial layer in the patterned stack to form openings between the channel layers; and
A word line structure is formed in the opening, wherein the word line structure surrounds each channel layer in the stack, the word line structure being oriented longitudinally along the first direction.
10. The method of claim 9, wherein the metal oxide material is a first metal oxide material, and forming the source feature and the drain feature comprises:
depositing a contact layer in the recess, wherein the contact layer comprises a second metal oxide material that differs from the first metal oxide material in oxygen concentration;
forming a first metal layer over the contact layer; and
a second metal layer is formed over the first metal layer to fill the recess.
CN202310737247.0A 2022-07-19 2023-06-21 Memory device and method of manufacturing the same Pending CN117042445A (en)

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US18/103,377 2023-01-30
US18/103,377 US20240032274A1 (en) 2022-07-19 2023-01-30 Back-end-of-line memory devices and methods of fabricating the same

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