CN115132778A - Phase change memory - Google Patents

Abstract

An embodiment of the present disclosure provides a phase change memory, including: the phase change memory array comprises a plurality of phase change memory units which are respectively arranged in parallel along a first direction and a second direction, and the first direction is intersected with the second direction; the preset position is located at the intersection of a first edge of the phase change memory array along the first direction and a second edge of the phase change memory array along the second direction; a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction; the word line contact units are electrically connected with the word lines, and the size of the word line contact units relatively far away from the preset position is larger than that of the word line contact units relatively close to the preset position along the second direction; and/or the plurality of bit line contact units are electrically connected with the plurality of bit lines, and the size of the bit line contact unit relatively far away from the preset position is larger than that of the bit line contact unit relatively close to the preset position along the first direction.

Description

Phase change memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a phase change memory.

Background

The phase change memory is a new nonvolatile memory device, and has great advantages in many aspects such as read-write speed, read-write times, data retention time, cell area, multi-value implementation and the like.

However, as the density of the memory array is gradually increased along with the development of the phase change memory, there are many problems in performing an electrical test on the high-density memory array.

Disclosure of Invention

An embodiment of the present disclosure provides a phase change memory, including:

the phase change memory array comprises a plurality of phase change memory units which are arranged in parallel along a first direction and a plurality of phase change memory units which are arranged in parallel along a second direction; wherein the first direction intersects the second direction; the phase change memory array includes: the preset position is located at the intersection of a first edge of the phase change memory array along the first direction and a second edge of the phase change memory array along the second direction;

a plurality of word lines extending in the first direction and a plurality of bit lines extending in the second direction; each phase change memory unit is arranged at the intersection point of one bit line and one word line, the word line is electrically connected with the phase change memory units arranged along the first direction, and the bit line is electrically connected with the phase change memory units arranged along the second direction;

a plurality of word line contact units electrically connected to the plurality of word lines; the size of the word line contact unit relatively far away from the preset position is larger than that of the word line contact unit relatively close to the preset position along the second direction;

and/or the presence of a gas in the gas,

a plurality of bit line contact units electrically connected to the plurality of bit lines; the size of the bit line contact unit relatively far away from the preset position is larger than that of the bit line contact unit relatively close to the preset position along the first direction.

In some embodiments of the present invention, the,

each word line contact unit comprises a word line contact structure; each of the word line contact structures is electrically connected to one of the word lines, and different ones of the word line contact structures are electrically connected to different ones of the word lines.

In some embodiments of the present invention, the,

each bit line contact unit comprises a bit line contact structure; each of the bit line contact structures is electrically connected to one of the bit lines, and different ones of the bit line contact structures are electrically connected to different ones of the bit lines.

In some embodiments of the present invention, the,

each bit line contact unit comprises a plurality of bit line contact structures; each bit line contact structure is electrically connected with one bit line, and different bit line contact structures are electrically connected with different bit lines;

wherein the content of the first and second substances,

the sizes of the plurality of bit line contact structures included in the same bit line contact unit are the same.

In some embodiments of the present invention, the,

each word line contact unit comprises a plurality of word line contact structures; each word line contact structure is electrically connected with one word line, and different word line contact structures are electrically connected with different word lines;

wherein the content of the first and second substances,

the sizes of the plurality of word line contact structures included in the same word line contact unit are the same.

In some embodiments of the present invention, the,

when the word line contact unit comprises a word line contact structure, the cross-sectional shape of the word line contact structure comprises a circle, an ellipse, a rectangle, a square or a rhombus;

when the bit line contact unit comprises a bit line contact structure, the cross-sectional shape of the bit line contact structure comprises a circle, an ellipse, a rectangle, a square or a rhombus;

wherein the cross section is parallel to the plane of the first direction and the second direction.

In some embodiments, in the second direction along the direction far away from the preset position, the size of the word line contact unit is increased gradually, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the gas,

in the first direction along the direction far away from the preset position, the size increment of the bit line contact unit is gradually increased, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

In some embodiments, in the second direction along the direction away from the preset position, the size increments of the word line contact units are sequentially the same, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the atmosphere,

in the first direction along the direction far away from the preset position, the size increments of the bit line contact units are sequentially the same, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

In some embodiments, the range of sizes includes 1nm to 100 nm.

In some embodiments, the phase change memory comprises a three-dimensional phase change memory.

In the embodiment of the disclosure, the sizes of the word line contact unit and/or the bit line contact unit in the phase change memory are changed, so that the resistance of different positions in the phase change memory is adjusted. Specifically, along the second direction, the size of the word line contact unit relatively far away from the preset position is larger than that of the word line contact unit relatively close to the preset position; and/or, along the first direction, the size of the bit line contact unit relatively far away from the preset position is larger than that of the bit line contact unit relatively close to the preset position; the preset position is located at the intersection of a first edge of the phase change memory array in the phase change memory along a first direction and a second edge of the phase change memory array in a second direction, and the first direction is intersected with the second direction.

In this embodiment, by setting the size of the word line contact unit and/or the bit line contact unit to be relatively small when approaching the preset position and to be relatively large when departing from the preset position, the resistance of the word line contact unit and/or the bit line contact unit to be relatively large when approaching the preset position and to be relatively small when departing from the preset position. The word line contact unit resistor with the resistance value change trend opposite to that of the parasitic resistor of the word line is arranged in the phase change memory, and/or the bit line contact unit resistor with the resistance value change trend opposite to that of the parasitic resistor of the bit line is arranged in the phase change memory, so that the resistance consistency of different positions in the phase change memory is improved, and the electric deviation of the word line or the bit line caused by the load effect in the electric test is weakened. In addition, because of the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

Drawings

FIG. 1 is a partial three-dimensional schematic view of a phase change memory according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a phase change memory array in the yox axial plane for a phase change memory according to an embodiment of the present disclosure;

FIG. 3 is a diagram illustrating a predetermined position of a phase change memory in the yox axial plane according to an embodiment of the present disclosure;

FIG. 4 is a first partial schematic view of a phase change memory in the yox axial plane in accordance with an embodiment of the present disclosure;

FIG. 5 is a partial schematic view of a phase change memory according to an embodiment of the present disclosure in the yoz plane;

FIG. 6 is a second partial schematic view in the yox axial plane of a phase change memory in accordance with one embodiment of the present disclosure;

FIG. 7 is a third partial schematic view of a phase change memory in the yox axial plane in accordance with an embodiment of the present disclosure;

FIG. 8 is a partial schematic view of a phase change memory in the xoz axial plane in accordance with an embodiment of the present disclosure;

FIG. 9 is a fourth partial schematic view in the yox axial plane of a phase change memory according to an embodiment of the present disclosure;

FIG. 10 is a schematic cross-sectional view illustrating a mesa contact structure in a phase change memory according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram illustrating a simulation of the rate of change of resistance of the truncated cone-shaped contact structure shown in fig. 10.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

A Phase Change Memory (PCM) includes a Phase Change Memory array and a peripheral circuit (may be abbreviated as CMOS); among other things, the phase change memory array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical application, the phase change memory array and the peripheral circuit can be formed in different areas on the same plane; or the phase change memory array and the peripheral circuits may form a stacked structure, i.e., they are formed on different planes. For example, the phase change memory array may be formed over peripheral circuitry to reduce chip size.

The phase change memory has the advantages of good radiation resistance, high random access speed, high read throughput rate, high storage density, good data retention property, strong size reduction capability and the like, and is compatible with the traditional CMOS process. However, as the process size is gradually reduced and the integration level of the phase change memory is gradually increased, the reliability problem of the phase change memory cell and the phase change memory array is more and more prominent. Such as parasitic capacitance, parasitic resistance, and thermal crosstalk effects.

Specifically, when the high-density phase change memory is electrically tested, parasitic resistances in series are introduced into a test loop by word lines, bit lines and Contact Structures (CTs) in the phase change memory array, which may cause consistency degradation of operating parameters (such as resistance, threshold voltage, etc.) of phase change memory cells at different positions in the phase change memory array, thereby affecting accuracy of an electrical test result.

The present disclosure finds that in a test loop of an electrical test, the parasitic resistance introduced by the contact structure is independent of the position of the contact structure in the phase change memory array, and the parasitic resistance introduced by the contact structure is relatively stable. Depending on the architecture of the phase change memory array, the main cause of the variation in resistance at different locations in the phase change memory array is the parasitic resistance introduced by the word lines or bit lines.

It should be noted that the loading effect is due to the additional resistance in the test loop. Taking current drive as an example: for a memory cell (cell) in actual operation, after a current signal is output from a driving end to the memory cell, a voltage signal of the memory cell is read to judge the storage state of the memory cell, and at the moment, the read voltage signal is influenced by an additional resistor in a test loop. Additional resistances may include resistance of the connections driving the terminals to the array, resistance of the word lines, resistance of the bit lines, resistance of the contact structures, and resistance of the memory cells. The resistance of the connecting line from the driving end to the array can be regarded as a constant for the same group of storage arrays; the electrical resistance of the contact structure, due to the fixed dimensions and materials of the contact structure, can generally be considered to be a constant value. Therefore, the loading effect mainly results from the resistance of the word line, the resistance of the bit line, and the resistance of the memory cell in the test loop.

Here, the loading effect of the bit line or the word line is mainly due to the influence of the relative distance of the memory cell and the bit line contact structure or the word line contact structure. The distances of the memory cells in the array relative to the contact structures are different, so that the lengths of the bit lines and the word lines required for connecting the memory cells in the test loop are different, and the resistance of the bit lines or the resistance of the word lines introduced into the test loop is changed by the coordinate change of the memory cells. Specifically, the farther the memory cell is from the contact structure, the more significant the loading effect is, and the bit line or the word line is connected to the driving terminal through different contact structures, the loading effect of the bit line or the word line may be superimposed, and thus, there is a loading distribution phenomenon approximately along the diagonal direction in the phase change memory.

It can be understood that, due to the word line or bit line loading effect, the uniformity of the resistance parameters of the phase change memory cells at different positions in the phase change memory array is degraded, and thus, the problem of electrical deviation occurs during the electrical test of the phase change memory.

Accordingly, the disclosed embodiments provide another phase change memory.

FIG. 1 is a partial three-dimensional schematic diagram illustrating a phase change memory according to an exemplary embodiment. Referring to fig. 1 to 3, a phase change memory 100 includes:

a phase change memory array 110 including a plurality of phase change memory cells 120 arranged in parallel along a first direction, and a plurality of phase change memory cells 120 arranged in parallel along a second direction; wherein the first direction intersects the second direction; the phase change memory array 110 includes: a preset position 130, located at an intersection of a first edge of the phase change memory array 110 along the first direction and a second edge of the phase change memory array 110 along the second direction;

a plurality of word lines 140 extending in a first direction and a plurality of bit lines 150 extending in a second direction; each phase change memory cell 120 is disposed at an intersection of one bit line 150 and one word line 140, the word line 140 is electrically connected to the plurality of phase change memory cells 120 arranged along the first direction, and the bit line 150 is electrically connected to the plurality of phase change memory cells 120 arranged along the second direction;

a plurality of word line contact units 160 electrically connected to the plurality of word lines 140; in the second direction, the size of the word line contact unit 160 relatively far from the predetermined position 130 is larger than the size of the word line contact unit 160 relatively close to the predetermined position 130.

Here, the phase change memory array 110 may be disposed on a substrate (not shown), which may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or other materials.

Note that the x-axis and the y-axis are included in fig. 1 to show the direction in which two of the substrate planes intersect. The first direction comprises an x-direction and the second direction comprises a y-direction, the z-direction being perpendicular to the xoy-plane. The same concepts for describing spatial relationships are applied throughout this disclosure and will not be described further herein. It should be noted that the first direction intersects the second direction, and the included angle between the first direction and the second direction includes an acute angle, a right angle or an obtuse angle. Preferably, the first direction is perpendicular to the second direction.

Referring to fig. 1 and 2, a phase change memory array is partially described, and fig. 1 is a partial three-dimensional schematic diagram of a phase change memory according to an embodiment of the disclosure. Referring to fig. 1, the phase change memory 100 includes a Bit Line (BL) 150, a phase change memory cell 120, and a Word Line (WL) 140 stacked in this order from bottom to top. As can be seen in fig. 1, word line 140 is perpendicular to bit line 150; meanwhile, the phase change memory cell 120 is perpendicular to both the bit line 150 and the word line 140.

It is understood that the phase change memory 100 may include a plurality of bit lines 150 over a substrate, and that the bit lines 150 may be parallel to each other and in the same plane. In some embodiments, the plurality of parallel bit lines 150 each extend in the y-direction (second direction) in fig. 2. The phase change memory 100 may also include a plurality of word lines 140 over bit lines 150. The word lines 140 may be parallel to each other and in the same plane. In some embodiments, a plurality of parallel word lines 140 each extend in the x-direction (first direction) in fig. 2.

Here, the bit line 150 and the word line 140 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The bit line 150 and the word line 140 may have the same conductive material or may have different conductive materials. In some embodiments, each of the bit line 150 and the word line 140 comprises a conductive material such as tungsten.

In some embodiments, phase change memory 100 also includes a plurality of phase change memory cells 120 each disposed at an intersection of a respective one of bit lines 150 and a respective one of word lines 140. Each phase change memory cell 120 may be individually accessed by a current applied through a corresponding word line 140 and a corresponding bit line 150 that are in contact with the phase change memory cell 120.

In particular, each phase change memory cell 120 may include a stacked phase change memory element, a gate, and a plurality of electrodes (not shown). The phase change memory element may store data by applying a current to repeatedly switch the phase change material of the phase change memory between two phases using a difference between resistivities of an amorphous phase and a crystalline phase in the phase change material based on electrothermal heating and quenching of the phase change material.

In some embodiments, two electrodes of the plurality of electrodes may be disposed between the gate and the phase change memory element and between the phase change memory element and the word line 140, respectively. That is, the two electrodes may be arranged on opposite sides (e.g., above and below) of the phase change memory element to separate the phase change memory element from other components without making direct contact.

It should be understood that the structure of the phase change memory cell 120 is not limited to the examples described above for illustration. In one example, the relative positions of the gates and the phase change memory elements may be switched. In another example, the number and relative positions of electrodes in phase change memory cell 120 may be varied.

According to some embodiments, the material of the phase change memory element comprises a chalcogenide-based alloy, such as a germanium antimony telluride (GeSbTe or GST) alloy, or any other phase change material. The electrodes may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the plurality of electrodes comprises carbon, such as amorphous carbon.

FIG. 2 shows a schematic diagram of a phase change memory array of a phase change memory in the yox axial plane. Referring to fig. 2, an arrangement of a word line 140, a word line contact unit 160, a bit line 150, and a bit line contact unit 170 is exemplarily shown. It should be noted that the word line contact unit 160 and the bit line contact unit 170 are not visible from the yox axial plane, and for convenience of illustration, the areas where the word line contact unit 160 and the bit line contact unit 170 are shown in the form of dashed boxes. In addition, structures other than the word line 140, the word line contact unit 160, the bit line 150, and the bit line contact unit 170 are omitted here. Here, two word line contact units 160a and 160b are exemplified for explanation.

Referring to fig. 3, the preset position 130 is located at an intersection of a first edge of the phase change memory array 110 along the first direction and a second edge of the phase change memory array 110 along the second direction. Referring to fig. 2 and 3, the size of the word line contact unit 160b relatively far from the predetermined position 130 is larger than the size of the word line contact unit 160a relatively close to the predetermined position 130 along the y-direction.

Illustratively, one word line contact unit 160 may include one or more word line contact structures 161. Referring to fig. 2, each word line 140 is electrically connected to one word line contact structure 161, and different word lines 140 are electrically connected to different word line contact structures 161. The word line contact structure 161 is not visible from the yox axis plane, and for convenience of illustration and description, the area where the word line contact structure 161 is located is shown in a circular form. Here, the Dimension includes a Critical Dimension (CD) of the word line contact unit, and the Critical Dimension includes a width of the etched trench or a diameter of the etched hole. Here, the shape of the word line contact structure 161 includes a cylinder, and the critical dimension may be a bottom diameter. Since the parasitic resistance of the word line contact structure 161 is affected by the critical dimension, for example, the critical dimension increases and the parasitic resistance of the word line contact structure 161 decreases, the critical dimension of the word line contact structure 161 in the word line contact unit 160b is larger than the critical dimension of the word line contact structure 161 in the word line contact unit 160a, so that the resistance of the word line contact structure 161 in the word line contact unit 160b is smaller than the resistance of the word line contact structure 161 in the word line contact unit 160 a.

It should be noted that the shape of the word line contact structure 161 includes a rectangular parallelepiped, and the size may be a length or a width; the shape of the word line contact structure 161 includes a truncated cone, which may be sized to have a bottom radius; the shape of the word line contact structure 161 includes a prism, and the size may be a bottom area, or the like.

The present disclosure finds that the actual measured resistance of the phase change memory cell may be approximated as the sum of the resistance of the phase change memory cell, the resistance of the contact cell, and the parasitic resistance; the parasitic resistance refers to a parasitic resistance of a word line or a bit line. Due to the word line or bit line load effect, the actually measured resistances of the phase change memory cells close to the preset position and far from the preset position have a large difference, for example, the parasitic resistance of the word line or bit line is relatively small when being close to the preset position and relatively large when being far from the preset position, which causes the consistency degradation of the operating parameters (such as resistance) of the phase change memory cells at different positions in the phase change memory array, and therefore, when the phase change memory is electrically tested, the problem of electrical deviation occurs due to the large difference of the resistances at different positions.

In this embodiment, the size of the word line contact unit is relatively small when being close to the preset position and relatively large when being far away from the preset position, so that the resistance of the word line contact unit is relatively large when being close to the preset position and relatively small when being far away from the preset position. The word line contact unit with the resistance value change trend opposite to that of the parasitic resistance of the word line is arranged in the phase change memory, so that the resistance consistency of different positions in the phase change memory is improved, and the reduction of the electrical deviation of the word line caused by the load effect in the electrical test is realized. In addition, because of the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

In some embodiments, the phase change memory 100 includes:

a phase change memory array 110 including a plurality of phase change memory cells 120 arranged in parallel along a first direction, and a plurality of phase change memory cells 120 arranged in parallel along a second direction; wherein the first direction intersects the second direction; the phase change memory array 110 includes: a preset position 130, located at an intersection of a first edge of the phase change memory array 110 along the first direction and a second edge of the phase change memory array 110 along the second direction;

a plurality of word lines 140 extending in a first direction and a plurality of bit lines 150 extending in a second direction; each phase change memory cell 120 is disposed at an intersection of one bit line 150 and one word line 140, the word line 140 is electrically connected to the plurality of phase change memory cells 120 arranged along the first direction, and the bit line 150 is electrically connected to the plurality of phase change memory cells 120 arranged along the second direction;

a plurality of bit line contact units 170 electrically connected to the plurality of bit lines 150; in the first direction, the dimension of the bit line contact unit 170 relatively far from the predetermined position 130 is larger than the dimension of the bit line contact unit 170 relatively close to the predetermined position 130.

Referring to fig. 2, two bit line contact units 170a and 170b are illustrated as an example.

In conjunction with fig. 2 and 3, the dimension of the bit line contact unit 170b relatively far from the preset position 130 is larger than the dimension of the bit line contact unit 170a relatively close to the preset position 130 along the x-direction.

One bit line contact unit 170 may include one or more bit line contact structures 171. Referring to fig. 2, each bit line 150 is electrically connected to one bit line contact structure 171, and different bit lines 150 are electrically connected to different bit line contact structures 171. The bit line contact structure 171 is not visible from the yox axial plane, and for convenience of illustration, the area of the bit line contact structure 171 is shown in a circular form.

Here, since the parasitic resistance of the bit line contact structure 171 is affected by the critical dimension, for example, the critical dimension increases and the parasitic resistance of the bit line contact structure 171 decreases, the resistance of the bit line contact structure 171 in the bit line contact unit 170b is made smaller than the resistance of the bit line contact structure 171 in the bit line contact unit 170a by setting the critical dimension of the bit line contact structure 171 in the bit line contact unit 170b larger than the critical dimension of the bit line contact structure 171 in the bit line contact unit 170 a.

It should be noted that the shape and size of the bit line contact structure 171 can refer to the shape and size of the word line contact structure 161, and are not described herein again.

In this embodiment, by setting the size of the bit line contact structure 171 in the bit line contact unit 170 to be relatively small when approaching the predetermined position 130 and to be relatively large when departing from the predetermined position 130, the resistance of the bit line contact structure 171 in the bit line contact unit 170 is relatively large when approaching the predetermined position 130 and to be relatively small when departing from the predetermined position 130. By providing the bit line contact unit 170 having a resistance variation trend opposite to that of the parasitic resistance of the bit line 150 in the phase change memory, the resistance uniformity of different positions in the phase change memory is improved, thereby reducing the electrical deviation of the bit line due to the load effect during the electrical test. In addition, because of the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

In some embodiments, it is preferable that the size of the word line contact cell relatively distant from the preset position is larger than the size of the word line contact cell relatively close to the preset position along the second direction, and the size of the bit line contact cell relatively distant from the preset position is larger than the size of the bit line contact cell relatively close to the preset position along the first direction. According to the above analysis, in the preferred embodiment, the word line contact unit with the resistance value variation trend opposite to that of the parasitic resistor of the word line is arranged in the phase change memory, and the bit line contact unit with the resistance value variation trend opposite to that of the parasitic resistor of the bit line is arranged in the phase change memory, so that the resistance consistency of different positions in the phase change memory can be significantly improved, and the electrical deviation of the word line or the bit line caused by the load effect during the electrical test can be reduced or even basically eliminated. In addition, because of the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

In some embodiments, each word line contact cell 160 includes one word line contact structure 161; each word line contact structure 161 electrically connects one word line 140, and different word line contact structures 160 electrically connect different word lines 140.

Fig. 4 shows a first partial schematic view of a phase change memory in the yox-axis plane, and referring to fig. 4, the layout of a word line 140, a word line contact unit 160, and a word line contact structure 161 is schematically shown. It should be noted that the word line contact structure 161 cannot be seen from the yox axial plane, and the word line contact structure 161 is shown here for convenience of showing the positional relationship between the word line 140 and the word line contact structure 161. In addition, structures other than the word line 140, the word line contact unit 160, and the word line contact structure 161 are omitted here.

Here, the word line contact structure 161 is illustrated as a circular cross-sectional shape, the cross-section being parallel to the yox axial plane. The cross-sectional shape of the word line contact structure 161 is exemplary only and not intended to limit the embodiments of the present disclosure, and in practical applications, the cross-sectional shape of the word line contact structure 161 may include a diamond shape, a rectangle shape, a square shape, an oval shape, and the like.

In conjunction with fig. 3 and 4, the dimension of the word line contact structure 161 relatively far from the predetermined position 130 is larger than the dimension of the word line contact structure 161 relatively close to the predetermined position 130 along the y-direction. FIG. 5 is a partial schematic view of a phase change memory in the yoz plane, and referring to FIG. 5, the bottom radii of the word line contact structures 161 along the y direction relatively far from the predetermined position 130 are r ₁ 、r ₂ 、r ₃ 、r ₄ 、r ₅ 、r ₆ . Here, r ₁ ＜r ₂ ＜r ₃ ＜r ₄ ＜r ₅ ＜r ₆ . The parasitic resistance of the word line contact structure 161 decreases with increasing size, and thus, is away from the predetermined position by being disposed in the y-directionThe size of the 130 word line contact structure 161 is increased so that the resistance of the word line contact structure 161 is reduced.

In some embodiments, it is preferable that the sizes of the word line contact structures 161 away from the preset position 130 are gradually increased along the y direction, that is, the sizes of each of the word line contact structures 161 are different and the sizes of the word line contact structures 161 away from the preset position 130 are increased along the y direction. According to the above analysis, in the preferred embodiment, the word line contact structure 161 having a resistance value variation trend opposite to that of the parasitic resistor of the word line 140 is disposed in the phase change memory, so that the resistance uniformity at different positions in the phase change memory can be significantly improved, and the electrical deviation of the word line caused by the load effect during the electrical test can be reduced or even substantially eliminated. In addition, due to the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

In some embodiments, each bit line contact unit 170 includes one bit line contact structure 171; each bit line contact structure 170 electrically connects one bit line 150, and different bit line contact structures 170 electrically connect different bit lines 150.

Fig. 6 illustrates a second partial schematic view of a phase change memory in the yox axial plane, and referring to fig. 6, the layout of bit line 150, bit line contact unit 170, and bit line contact structure 171 is schematically illustrated. Here, the bit line contact structure 171 is not visible from the yox axial plane, and the bit line contact structure 171 is shown here for convenience of showing the positional relationship between the bit line 150 and the bit line contact structure 171. In addition, structures other than the bit line 150, the bit line contact unit 170, and the bit line contact structure 171 are omitted here.

Here, the cross-sectional shape of the bit line contact structure 171 is illustrated as a circle, and the cross-section is parallel to the yox axial plane.

In conjunction with fig. 3 and 6, the dimension of the bit line contact structure 171 relatively far from the predetermined location 130 is larger than the dimension of the bit line contact structure 171 relatively close to the predetermined location 130 along the x-direction. The parasitic resistance of the bit line contact structure 171 decreases as the size increases, and thus, the size of the bit line contact structure 171 increases away from the preset position 130 by being disposed in the x-direction, so that the resistance of the bit line contact structure 171 decreases.

In some embodiments, it is preferable that the sizes of the bit line contact structures 171 far from the preset position 130 are gradually increased along the x direction, that is, the sizes of each bit line contact structure 171 are different and the sizes of the bit line contact structures 171 far from the preset position 130 are increased along the x direction. According to the above analysis, in the preferred embodiment, the bit line contact structure 171 with a resistance value variation trend opposite to that of the parasitic resistance of the bit line 150 is disposed in the phase change memory, so that the resistance uniformity of different positions in the phase change memory can be significantly improved, and the electrical deviation of the bit line caused by the load effect during the electrical test can be reduced or even substantially eliminated. In addition, due to the relatively uniform resistance distribution, the influence of parasitic effects such as parasitic resistance can be reduced, and therefore, the technical scheme provided by the embodiment can improve the working reliability of the phase change memory.

In some embodiments, each bit line contact unit 170 includes a plurality of bit line contact structures 171; each bit line contact structure 171 is electrically connected to one bit line 150, and different bit line contact structures 171 are electrically connected to different bit lines 150;

the bit line contact units 170 include a plurality of bit line contact structures 171 having the same size.

Fig. 7 illustrates a third partial schematic view of a phase change memory in the yox axial plane, and referring to fig. 7, the layout of bit line 150, bit line contact unit 170, and bit line contact structure 171 is schematically shown. Here, three bit line contact units 170 are illustrated, and each bit line contact unit 170 includes two bit line contact structures 171.

In conjunction with fig. 3 and 7, the dimension of the bit line contact unit 170 relatively far from the preset position 130 is larger than the dimension of the bit line contact unit 170 relatively close to the preset position 130 along the x-direction. The two bit line contact structures 171 in the same bit line contact unit 170 have the same size.

Referring to fig. 8, which shows a partial view of a phase change memory in the xoz axial plane, the bottom radii of the bit line contact structure 171 relatively far from the predetermined position 130 along the x direction are r1, r2, r3, r4, r5 and r6, respectively. Here, r1 ═ r2 < r3 ═ r4 < r5 ═ r 6. The parasitic resistance of the bit line contact structure 171 decreases as the size increases, and thus, the size of the bit line contact unit 170 increases away from the preset position 130 by being disposed in the x-direction, so that the resistance of the bit line contact unit 170 decreases.

In some embodiments, it is preferable that the bit line contact units 170 away from the preset position 130 have gradually increasing sizes along the x direction, that is, the sizes of each bit line contact unit 170 are different and the sizes of the bit line contact units 170 away from the preset position 130 increase along the x direction, and the sizes of two bit line contact structures 171 in the same bit line contact unit 170 are the same.

According to the above analysis, in the preferred embodiment, the bit line contact structure 171 with a resistance value variation trend opposite to that of the parasitic resistance of the bit line 150 is disposed in the phase change memory, so that the resistance uniformity of different positions in the phase change memory can be significantly improved, and the electrical deviation of the bit line caused by the load effect during the electrical test can be reduced or even substantially eliminated. Also, the bit line contact structure 171 is preferably easier to fabricate than a bit line contact structure with an increasing size.

In some embodiments, each word line contact unit 160 includes a plurality of word line contact structures 161; each word line contact structure 161 is electrically connected to one word line 140, and different word line contact structures 161 are electrically connected to different word lines 140;

the plurality of word line contact structures 161 included in the same word line contact unit 160 have the same size.

Referring to FIG. 9, FIG. 9 illustrates a fourth partial view of a phase change memory in the yox axial plane, schematically showing the layout of the word line 140, the word line contact unit 160, and the word line contact structure 161. Here, three word line contact units 160 are illustrated, and each word line contact unit 160 includes two word line contact structures 161.

For a detailed analysis of the structure of each bit line contact unit 170 including a plurality of bit line contact structures 171, the detailed description is omitted here.

In some embodiments, when the word line contact unit includes the word line contact structure, a cross-sectional shape of the word line contact structure includes a circle, an ellipse, a rectangle, a square, or a diamond;

when the bit line contact unit comprises a bit line contact structure, the cross section of the bit line contact structure is circular, oval, rectangular, square or rhombic;

wherein the cross section is parallel to the plane of the first direction and the second direction.

It should be noted that the cross-sectional shapes of the word line contact structures or the bit line contact structures are merely exemplary and are not intended to limit the embodiments of the disclosure. The word line contact structure or the bit line contact structure having different shapes has different resistance variations, and here, the word line contact structure is described as a truncated cone.

Referring to fig. 10, the equation (1) can be calculated by the resistance

And calculating the resistance of the truncated cone-shaped word line contact structure, wherein rho represents the resistivity, l represents the height of the truncated cone, and S represents the cross-sectional area of the truncated cone. Resistance calculation formula (2) for obtaining a truncated cone-shaped word line contact structure by integrating formula (1)

Wherein α ═ tan θ represents a cross section of the word line contact structure; beta is H/r ₀ Represents the aspect ratio of the word line contact structure, H represents the height of the truncated cone, r ₀ Representing the radius of the bottom surface of the truncated cone.

With reference to fig. 10 and 11, it can be known from simulation experiments that the resistance of the truncated cone-shaped word line contact structure varies with the critical dimension, and the rate of change of the resistance of the truncated cone-shaped word line contact structure is as follows:

wherein Δ R represents a resistance change rate, R _CD+ Representing the resistance after critical dimension growth, R ₀ Representing critical dimensionsResistance before growth.

Here, the abscissa in fig. 11 represents the bottom critical dimension (in nm), and the ordinate represents the resistance change rate. The present disclosure has found that the parasitic resistance of the truncated-cone-shaped word line contact structure is mainly affected by the critical dimension, the bottom critical dimension (radius r as shown in fig. 10) of the word line contact structure ₀ ) For every 1nm increase, the resistance drops by approximately 8%.

In some embodiments, in the second direction along the direction away from the preset position, the size increment of the word line contact unit is gradually increased, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the gas,

in the first direction along the direction far away from the preset position, the size increment of the bit line contact unit is gradually increased, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

It should be noted that each word line contact unit may include one or more word line contact structures. In one example, each word line contact unit includes a word line contact structure, for example, the size of the word line contact structure may be 10nm, and the size of the word line contact unit is 10 nm. In another example, each word line contact unit includes a plurality of word line contact structures, and the plurality of word line contact structures included in the same word line contact unit have the same size, for example, the same word line contact unit includes three word line contact structures, and the size of each of the three word line contact structures is 12nm, so that the size of the word line contact unit is 12nm that is the size of any one of the word line contact structures.

Here, the trend of the variation in the size of the word line contact cell is exemplarily shown. For example, in the second direction along the direction away from the preset position, each word line contact unit 160 may include two word line contact structures 161, and the two word line contact structures 161 included in the same word line contact unit 160 have the same size, and exemplarily, in the second direction along the direction away from the preset position, the word line contact structures 161 may have sizes of 10nm, 12nm, 15nm, and the word line contact units 160 relatively far from the preset position 130 may have sizes of 10nm, 12nm, and 15nm, and then the word line contact units have size increments of 2nm and 3nm, respectively, and the word line contact units have size increments that are gradually increased. In this way, the resistance consistency of different positions in the phase change memory can be obviously improved, so that the electrical deviation of the word line caused by the load effect in the electrical test can be weakened or even basically eliminated, the size difference between adjacent word line contact units can be enlarged, and the preparation difficulty can be reduced.

It should be noted that each bit line contact unit may include one or more bit line contact structures. In one example, each bit line contact unit includes a bit line contact structure, for example, the size of the bit line contact structure may be 10nm, and the size of the bit line contact unit is 10 nm. In another example, each bit line contact unit includes a plurality of bit line contact structures, and the plurality of bit line contact structures included in the same bit line contact unit have the same size, for example, the same bit line contact unit includes three bit line contact structures, and the size of each bit line contact structure is 12nm, so that the size of the bit line contact unit is 12nm that is the size of any one of the bit line contact structures.

Here, the trend of the variation in the size of the bit line contact cell is exemplarily shown. For example, in the first direction along the direction away from the preset position, each bit line contact unit 170 may include two bit line contact structures 171, and the two bit line contact structures 171 included in the same bit line contact unit 170 have the same size, and for example, in the first direction along the direction away from the preset position, the bit line contact structures 171 may have sizes of 10nm, 12nm, 15nm, and the bit line contact units 170 relatively far from the preset position 130 may have sizes of 10nm, 12nm, and 15nm, and then the bit line contact units 170 have size increments of 2nm and 3nm, respectively, and the size increments of the bit line contact units 170 gradually increase. In this way, the consistency of the resistance at different positions in the phase change memory can be remarkably improved, so that the electrical deviation of the bit line caused by the load effect in the electrical test can be weakened or even basically eliminated.

In some embodiments, in the second direction along the direction away from the preset position, the size increments of the word line contact units are sequentially the same, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the gas,

in the first direction along the direction far away from the preset position, the size increment of the bit line contact units is the same in sequence, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

It should be noted that each word line contact unit may include one or more word line contact structures. In one example, each word line contact unit includes a word line contact structure, for example, the size of the word line contact structure may be 10nm, and the size of the word line contact unit is 10 nm. In another example, each word line contact unit includes a plurality of word line contact structures, and the plurality of word line contact structures included in the same word line contact unit have the same size, for example, the same word line contact unit includes three word line contact structures, and the sizes of the three word line contact structures are all 11nm, so that the size of the word line contact unit is the size of any one of the word line contact structures, that is, 11 nm.

Here, the trend of the variation in the size of the word line contact cell is exemplarily shown. For example, in the second direction along the direction away from the preset position, each word line contact unit 160 may include two word line contact structures 161 having the same size, and in the y direction, for example, in the second direction along the direction away from the preset position, the size of each word line contact structure 161 may be 10nm, 11nm, 12nm, and the size of each word line contact unit 160 relatively far from the preset position 130 may be 10nm, 11nm, and 12nm, so that the size increments of the word line contact units are all 1nm, and the size increments of the word line contact units are sequentially the same. In this way, the consistency of the resistance at different positions in the phase change memory can be remarkably improved, so that the electrical deviation of the word line caused by the load effect in the electrical test can be weakened or even basically eliminated.

It should be noted that each bit line contact unit may include one or more bit line contact structures. In one example, each bit line contact unit includes a bit line contact structure, for example, the size of the bit line contact structure may be 10nm, and the size of the bit line contact unit is 10 nm. In another example, each bit line contact unit includes a plurality of bit line contact structures, and the plurality of bit line contact structures included in the same bit line contact unit have the same size, for example, the same bit line contact unit includes three bit line contact structures, and the size of each bit line contact structure is 11nm, so that the size of the bit line contact unit is the size of any one bit line contact structure, that is, 11 nm.

Here, the trend of the variation in the size of the bit line contact cell is exemplarily shown. For example, in the first direction, the bit line contact units 170 may include two bit line contact structures 171, and the two bit line contact structures 171 included in the same bit line contact unit 170 have the same size, and referring to fig. 7, in the x direction, the bit line contact structures 171 may have the same size, and in the first direction, the bit line contact units 170 may have the same size, and in the first direction, the bit line contact structures 171 may have the size of 10nm, 11nm, 12nm, and the bit line contact units 170 relatively far from the preset positions 130 may have the size of 10nm, 11nm, and 12nm, and then the bit line contact units 170 have the size increment of 1nm, and the bit line contact units 170 have the same size increment. In this way, the consistency of the resistance at different positions in the phase change memory can be remarkably improved, so that the electrical deviation of the bit line caused by the load effect in the electrical test can be weakened or even basically eliminated.

In some embodiments, the range of sizes includes 1nm to 100 nm.

It is understood that the word line contact structure or the bit line contact structure is formed by means of etching using a mask layer, but not limited thereto. Specifically, a mask layer is formed on a dielectric layer after the dielectric layer is formed on a substrate, the mask layer is used for etching the dielectric layer to form a contact hole, and a conductive material is filled in the contact hole to form a word line contact structure or a bit line contact structure.

Here, the mask layer may include a photoresist mask or a hard mask patterned based on a photolithography mask. In some embodiments, the material of the mask layer comprises carbon.

Here, the method of forming the mask layer includes, but is not limited to, Chemical Vapor Deposition (CVD).

Here, the pattern on the mask layer may be understood with reference to the top views shown in fig. 4 to 7. It should be noted that the shape of the pattern on the mask layer is merely exemplary and is not intended to limit the embodiments of the present disclosure, and in practical applications, the shape of the pattern of the word line contact structure or the bit line contact structure on the mask layer may refer to other patterns formed by combining the above embodiments.

Here, the size range includes 1nm to 100nm, which is merely exemplary and not intended to limit the embodiments of the disclosure, and in the actual phase change memory manufacturing process, a person skilled in the art may reasonably set the size range according to design requirements, for example, the size range may be obtained according to the size of the memory array, the parasitic resistance of the word line or the bit line, and the resistance of the word line or the bit line contact structure.

In some embodiments, the phase change memory comprises a three-dimensional phase change memory.

Based on the structure of the phase change memory, the embodiment of the present disclosure further provides a three-dimensional phase change memory, including:

the phase change memory comprises a bit line, a phase change memory unit and a word line which are sequentially stacked on a first region of a substrate; the bit lines and the word lines are parallel to the same plane and are vertical to each other; the phase change memory unit comprises a first electrode, a phase change memory element, a second electrode, a gating element and a third electrode which are sequentially stacked; the first electrode, the first functional element, the second electrode, the second functional element and the third electrode are all vertical to the bit line and the word line;

providing a contact structure on a second region of the substrate; the second region is provided with a peripheral circuit, the contact structure is in contact with the peripheral circuit, the contact structure is in contact with and vertical to the word line, and the contact structure is in contact with and vertical to the bit line.

For details of the contact structure of the three-dimensional phase change memory, reference may be made to the word line contact structure and the bit line contact structure in the above-described embodiments of the phase change memory, and details thereof are not repeated here.

It should be appreciated that reference throughout this specification to "some embodiments" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in some embodiments" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (10)

1. A phase change memory, comprising:

the phase change memory array comprises a plurality of phase change memory units which are arranged in parallel along a first direction and a plurality of phase change memory units which are arranged in parallel along a second direction; wherein the first direction intersects the second direction; the phase change memory array includes: the preset position is located at the intersection of a first edge of the phase change memory array along the first direction and a second edge of the phase change memory array along the second direction;

a plurality of word lines extending in the first direction and a plurality of bit lines extending in the second direction; each phase change memory unit is arranged at the intersection point of one bit line and one word line, the word line is electrically connected with the phase change memory units arranged along the first direction, and the bit line is electrically connected with the phase change memory units arranged along the second direction;

a plurality of word line contact units electrically connected to the plurality of word lines; wherein, along the second direction, the size of the word line contact unit relatively far away from the preset position is larger than the size of the word line contact unit relatively close to the preset position;

and/or the presence of a gas in the atmosphere,

a plurality of bit line contact units electrically connected to the plurality of bit lines; the size of the bit line contact unit relatively far away from the preset position is larger than that of the bit line contact unit relatively close to the preset position along the first direction.

2. The phase change memory according to claim 1,

each word line contact unit comprises a word line contact structure; each of the word line contact structures is electrically connected to one of the word lines, and different ones of the word line contact structures are electrically connected to different ones of the word lines.

3. The phase change memory according to claim 1,

each bit line contact unit comprises a bit line contact structure; each of the bit line contact structures is electrically connected to one of the bit lines, and different ones of the bit line contact structures are electrically connected to different ones of the bit lines.

4. The phase change memory according to claim 1,

each bit line contact unit comprises a plurality of bit line contact structures; each bit line contact structure is electrically connected with one bit line, and different bit line contact structures are electrically connected with different bit lines;

wherein the content of the first and second substances,

the sizes of the plurality of bit line contact structures included in the same bit line contact unit are the same.

5. The phase change memory according to claim 1,

each word line contact unit comprises a plurality of word line contact structures; each word line contact structure is electrically connected with one word line, and different word line contact structures are electrically connected with different word lines;

wherein the content of the first and second substances,

the sizes of the plurality of word line contact structures included in the same word line contact unit are the same.

6. The phase change memory according to claim 2 or 3,

when the word line contact unit comprises a word line contact structure, the cross section of the word line contact structure is circular, oval, rectangular, square or rhombic;

when the bit line contact unit comprises a bit line contact structure, the cross-sectional shape of the bit line contact structure comprises a circle, an ellipse, a rectangle, a square or a rhombus;

wherein the cross section is parallel to the plane of the first direction and the second direction.

7. The phase change memory according to any one of claims 2 to 5,

in the second direction along the direction far away from the preset position, the size increment of the word line contact unit is gradually increased, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the gas,

in the first direction along the direction far away from the preset position, the size increment of the bit line contact unit is gradually increased, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

8. The phase change memory according to any one of claims 2 to 5,

in the second direction along the direction far away from the preset position, the size increments of the word line contact units are sequentially the same, and the sizes of the word line contact structures in the same word line contact unit are the same;

and/or the presence of a gas in the gas,

in the first direction along the direction far away from the preset position, the size increments of the bit line contact units are sequentially the same, and the sizes of the bit line contact structures in the same bit line contact unit are the same.

9. The phase change memory of claim 1, wherein the range of sizes includes 1nm to 100 nm.

10. The phase change memory of claim 1, wherein the phase change memory comprises a three-dimensional phase change memory.

Images