CN114256248A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The application discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; a gate stack structure on the substrate; a plurality of openings through the gate stack; a trench penetrating the gate stack structure; the sacrificial layer, the barrier layer and the contact structure are positioned in the groove; and the insulating layer is used for forming a first air gap in the plurality of openings and realizing electrical isolation among the barrier layer, the contact structure and the gate stack structure, wherein the contact structure penetrates through the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and part of the barrier layer extends to be above the sacrificial layer. The semiconductor device improves the distance between the first end part and the second end part of the barrier layer and the contact structure, thereby greatly reducing the possibility that the second air gap is contacted with the contact structure and improving the yield and the reliability of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

The direction of development in semiconductor technology is the reduction of feature size and the increase of integration. For the memory device, the increase in the memory density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher.

In the manufacturing process of semiconductor devices, air gaps (air gaps) are increasingly used as dielectric layers, which has many advantages, for example, the use of air gaps is beneficial to reducing the feature size, and in the manufacturing process of NAND flash memory chips, the use of air gaps is beneficial to reducing the mutual interference between word lines, thereby being beneficial to reducing the signal interference in the flash memory chips to a lower level.

However, in the process of forming the air gap, parasitic voids are often formed at the same time, and as the feature size of the semiconductor manufacturing process becomes smaller, the yield and reliability of the semiconductor device are greatly reduced or even become unusable once the parasitic voids are close to the critical structure of the semiconductor device. Referring to fig. 1, fig. 1 is a cross-sectional image of a NAND semiconductor device observed by a scanning electron microscope, in the process step of forming an air gap 1, parasitic voids 2 and 2 'are formed between the select transistors, and the voids 2 and 2' are respectively close to contact structures 3 and 3 '(contact holes) between the select transistors, wherein the voids 2' and the contact structures 3 'are already close to each other and thus the voids 2' have a great adverse effect on the semiconductor device. This is very common in the fabrication of semiconductor devices.

Therefore, it is desirable to further improve the semiconductor device and the manufacturing method thereof to improve the yield and reliability of the semiconductor device.

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which is advantageous for increasing the distance between the first end portion and the second end portion of the barrier layer and the contact structure, thereby reducing the possibility of the second air gap and the contact structure contacting each other, and improving the yield and reliability of the semiconductor device.

According to the present disclosure, there is provided a semiconductor device including: a substrate; a gate stack structure on the substrate; a plurality of openings penetrating the gate stack structure to form a plurality of word lines spaced apart from each other in the gate stack structure; a slot penetrating through the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line; the sacrificial layer, the barrier layer and the contact structure are positioned in the groove; a bit line over the substrate, the bit line electrically connected to the common source drain region of the adjacent select transistor via the contact structure; and the insulating layer is used for forming a first air gap in the plurality of openings and realizing electrical isolation among the barrier layer, the contact structure and the gate stack structure, wherein the contact structure penetrates through the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and part of the barrier layer extends to be above the sacrificial layer.

Optionally, there is a second air gap at the first end and/or the second end of the barrier layer.

Optionally, the insulating layer includes a first oxide layer, a third oxide layer, a fourth oxide layer, and a fifth oxide layer, the first oxide layer, the sacrificial layer, the third oxide layer, the barrier layer, and the fourth oxide layer are sequentially stacked on the substrate, and the fifth oxide layer is at least filled in a cavity formed by removing the sacrificial layer and the barrier layer on the sidewall of the trench, so as to form the second air gap.

Optionally, the sacrificial layer and the barrier layer are of the same material.

Optionally, the thickness of the barrier layer is less than the thickness of the sacrificial layer.

Optionally, the semiconductor device further comprises a third air gap located over the sacrificial layer.

According to the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a plurality of openings penetrating through the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure; forming a slot penetrating through the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection tubes in the gate stack structure, wherein the slot isolates the first selection control gate line from the second selection control gate line; forming a first oxide layer, wherein the first oxide layer covers the side walls of the word lines and the side walls of the first selection control grid line and the second selection control grid line; forming a sacrificial layer which fills and covers gaps between the side walls of the word lines and the first oxidation layer; forming a second oxide layer covering the sacrificial layer; partially removing the sacrificial layer, the first oxide layer and the second oxide layer in the groove to form an injection window; removing the remaining second oxide layer; sequentially forming a third oxide layer, a barrier layer and a fourth oxide layer; partially removing the sacrificial layer and the barrier layer to form a first air gap between the plurality of word lines; forming a fifth oxide layer covering the gate stack structure, the opening and the slot; forming a contact structure located within the slot.

Optionally, the sacrificial layer and the barrier layer are made of the same material

Optionally, after the forming the sacrificial layer, the method further includes: and carrying out ion implantation on the substrate through the implantation window to form a common source drain region of the adjacent selection tubes.

Optionally, after forming the implantation window, the sacrificial layer in the trench is in an "L" shape.

Optionally, the contact structure penetrates through the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a portion of the barrier layer extends above the sacrificial layer.

A semiconductor device according to the present disclosure is characterized by comprising: a substrate; the gate stack structure is positioned on the substrate and comprises gate stacks of the storage units and gate stacks of the selection tubes; the grid stacking layers of two adjacent selection tubes comprise a sacrificial layer, a barrier layer, an insulating layer and a contact structure penetrating through the barrier layer and the insulating layer, the contact structure is connected with the common source drain region of the two adjacent selection tubes, the sacrificial layer and the barrier layer are separated by the insulating layer, and part of the barrier layer extends to the position above the sacrificial layer.

Optionally, the semiconductor device further comprises a first air gap between the gate stacks of adjacent memory cells.

Optionally, the sacrificial layer and the barrier layer are of the same material.

Optionally, the thickness of the barrier layer is less than the thickness of the sacrificial layer.

Optionally, the semiconductor structure further comprises a second air gap located on both sides of the barrier layer.

Optionally, the semiconductor device is a NAND flash memory.

According to the semiconductor device and the manufacturing method thereof provided by the invention, the thickness of the side wall of the sacrificial layer is reduced, so that the third oxide layer and the barrier layer correspondingly deviate towards the direction far away from the contact structure, and therefore, in the finally formed semiconductor device, the barrier layer is step-shaped, the distances between the first end part and the second end part of the barrier layer and the contact structure are increased, and the second air gap is connected to the contact structure through the barrier layer, so that the possibility of the contact between the second air gap and the contact structure is greatly reduced, and the yield and the reliability of the semiconductor device are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a cross-sectional image of a semiconductor device according to the prior art;

fig. 2 shows a layout diagram example of a semiconductor device according to an embodiment of the present invention;

FIG. 3 shows a partial perspective view of a memory cell string;

FIG. 4a shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention taken along line A-A' of FIG. 2;

FIG. 4b shows a close-up view of the BB area of FIG. 4 a;

fig. 5a to 5h show schematic cross-sectional views of stages of a method of manufacturing a semiconductor device according to an embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 2 shows a layout diagram example of a semiconductor device according to an embodiment of the present invention; FIG. 3 shows a partial perspective view of a memory cell string; FIG. 4a shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention taken along line A-A' of FIG. 2; fig. 4b shows a partial enlargement of the BB area in fig. 4 a.

The semiconductor device of the present application may be a nonvolatile memory such as a NAND flash memory, a NOR flash memory, an EEPROM, or the like. In the NOR flash memory, each memory cell is independently connected to a bit line and a word line, and thus the NOR flash memory has an excellent random access time. In the NAND flash memory, since memory cells are connected in series and one memory cell string (string) has only one contact hole with a bit line, the NAND flash memory has excellent integration characteristics and is generally used in a high density flash memory. The following description will be given taking a semiconductor device as an example of a NAND flash memory.

As shown in fig. 2 and 3, the active regions 11 of the semiconductor device 100 may extend parallel to each other in the first direction. The plurality of word lines WL and the gate lines SL of the select transistors extend in the second direction and are arranged in the first direction, and the word lines WL and the gate lines SL of the select transistors may be disposed perpendicular to the bit lines BL. Each active region 11 has a plurality of memory cells formed therein, and the plurality of memory cells are connected in series to form a memory cell string, and each memory cell is connected to a corresponding word line WL. The memory cell may be implemented by a field effect transistor having a charge trapping layer, which may be a floating gate or a charge trapping dielectric layer, sandwiched between two dielectric layers. Adjacent active regions 11 are isolated, for example, by Shallow Trenches (STI). The memory cell string also has a first selection transistor and a second selection transistor formed at both ends thereof, and the word lines WL are arranged between the gate lines of the first selection transistor and the second selection transistor. The common source line CSL may be disposed between the gate lines GSL of the second select tubes of the adjacent memory cell strings to extend in the second direction. The bit line BL may be arranged to extend in the first direction and electrically connected to the drain region between the first select transistors of the adjacent memory cell strings through the bit line contact structure DC. That is, adjacent memory cell strings may share a contact hole of a bit line or a contact hole of a common source line CSL. According to an exemplary embodiment of the present disclosure, as shown in fig. 3, 4a and 4b, a semiconductor device 100 includes a substrate 101 and a gate stack structure 110 over the substrate. The gate stack structure 110 includes a plurality of gate stacks of memory cells, a gate stack of a first select transistor (a first select control gate line), and a gate stack of a second select transistor (a second select control gate line). The first and second selection pipes shown in fig. 4a belong to two adjacent memory cell strings. Referring to fig. 4b, the BB region in fig. 4a, i.e., the gate stack of one memory cell, includes a floating gate 111, an isolation layer 112, and a control gate 113, which are sequentially stacked. In the gate stack of the first selection transistor and the gate stack of the second selection transistor, the isolation layer 112 is partially or completely removed, and the material forming the floating gate 111 and the material forming the control gate 113 are connected together to serve as a gate.

The floating gate 111 is, for example, silicon, polysilicon, germanium or other semiconductor material, the isolation layer 112 is, for example, silicon oxide or silicon nitride, the control gate 113 is, for example, silicon, polysilicon, germanium or other semiconductor material, and optionally, the floating gate 111 and the control gate 113 are made of the same material. The isolation layer 112 may be a dielectric layer having a high dielectric constant (k), for example, the isolation layer 112 may include at least one of an oxide/nitride/oxide (ONO) layer, an aluminum oxide layer, a hafnium aluminum oxide layer, and a zirconium oxide layer. Control gate 113 may include a doped polysilicon layer and/or a metal silicide layer. The control gate 113 may have a pattern formed therein, and for example, the control gate 113 may include a word line WL and a gate line SL of a select transistor shown in fig. 2.

According to an exemplary embodiment, an opening and a trench are formed through the gate stack structure 110, and the surface of the gate stack structure 110 is covered with an insulating layer 148, the insulating layer 148 above the opening is used to form the first air gap 122, the insulating layer 148 filled in the trench separates the gate stacks of the select transistors of the adjacent memory cell strings, and the insulating layer 148 may be a silicon oxide layer. The openings are used to form a first air gap 122, providing good isolation between word lines WL; the trenching is used to form the contact structure 150, and the bit line contact structure DC may be formed after the contact structure 150 connects the metal conductors.

In this embodiment, the insulating layer 148 is formed in steps during the process of forming the first air gap 122 and the contact structure 150, which may form a parasitic second air gap 134 between the select transistor and the contact structure 150. Specifically, the trench further includes a sacrificial layer 142 and a barrier layer 145, the sacrificial layer 142 and the barrier layer 145 are separated by an insulating layer, and at least a portion of the barrier layer 145 is located on the sacrificial layer 142, so that the barrier layer 145 is stepped; the first end portion and the second end portion of the barrier layer 145 are respectively adjacent to the first select control gate line and the second select control gate line, and respectively extend in a step shape in a direction away from the contact structure 150, and the contact structure 150 penetrates through a portion of the barrier layer 145 between the first end portion and the second end portion and the insulating layer 148; the bit line BL is electrically connected via a contact structure 150 to an active region 103 within the substrate 101, the active region 103 being a common source-drain region of the select transistors of two adjacent memory cell strings. Optionally, the sacrificial layer 142 and the barrier layer 145 are made of the same material. Optionally, the thickness of the sacrificial layer 142 is 2 times the thickness of the barrier layer 145. For example, the thickness of the sacrificial layer 142 is

The barrier layer 145 has a thickness of

Optionally, the semiconductor device further includes a third air gap located in the trench above the sacrificial layer 142, where the third air gap is also a parasitic air gap.

In this embodiment, since the first air gap 122 is filled with air, the dielectric constant of the first air gap 122 may be lower than that of the silicon oxide layer. Accordingly, the first air gap 122 may significantly reduce parasitic capacitance between memory cells adjacent to each other. That is, the first air gap 122 may minimize an interference effect between adjacent memory cells.

Fig. 5a to 5h show schematic cross-sectional views of stages of a method of manufacturing a semiconductor device according to an embodiment of the invention.

The manufacturing method of the semiconductor device of the embodiment of the invention starts with a semiconductor structure in which a tunneling oxide layer 102 and a gate stack structure 110 are formed on the surface of a semiconductor substrate 101, wherein the gate stack structure 110 comprises gate stacks of a plurality of memory cells, a gate stack of a first selection tube and a gate stack of a second selection tube, and the gate stacks of the memory cells comprise a floating gate 111, an isolation layer 112 and a control gate 113 which are sequentially stacked. As shown in fig. 5a, in this step, a plurality of openings 120 and trenches 130 are also formed through the tunnel oxide layer 102 and the gate stack structure 110, the openings 120 separating the gate stacks of the plurality of memory cells and separating the gate stacks of the select transistors and the gate stacks of the memory cells, the trenches 130 separating adjacent memory cell strings, and referring to fig. 5h, a contact structure 150 is formed in the trenches 130. The contact structure 150 is used to connect bit lines or common gate lines.

As an example, the semiconductor substrate 101 is selected from any one or more of silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), the tunnel oxide layer 153 is silicon oxide, the floating gate 111 is silicon, polysilicon, germanium, or other semiconductor material, the isolation layer 112 is silicon oxide or silicon nitride, the control gate 113 is silicon, polysilicon, germanium, or other semiconductor material, and optionally, the floating gate 111 and the control gate 113 are made of the same material. In this embodiment, the isolation layer 112 is an ONO structure (oxide-nitride-oxide). For example, the floating gate 111 and the isolation layer 112 are sequentially formed on the active region; the isolation layer 112 of the select transistor region is partially removed and a control gate 113 is formed.

In this step, the bottom tunnel oxide Layer 102 and the gate stack structure 110 are formed by, for example, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), and preferably, the bottom tunnel oxide Layer 102 and the gate stack structure 110 are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).

Further, a first oxide layer 141 (the first oxide layer 141 covers sidewalls of the plurality of word lines WL and sidewalls of the first and second select gate lines) and a sacrificial layer 142 (the sacrificial layer 142 fills a gap between the sidewalls of the plurality of word lines WL and the first oxide layer 141) are formed in the plurality of openings 120, the first oxide layer 141, the sacrificial layer 142, and a second oxide layer 143 (the second oxide layer 143 covers the sacrificial layer 142) are formed in the trench 130, and the active region 103 is formed on the substrate 101, as shown in fig. 5 b.

As an example, the first oxide layer 141 and the second oxide layer 143 are made of the same material, for example, the first oxide layer 141 and the second oxide layer 143 are both made of silicon oxide, and the sacrificial layer 142 is made of silicon nitride, for example. In this embodiment, an "L" shaped sacrificial layer 142 is formed, reducing the sacrificial layer 142 thickness on the sidewalls of the select tubes. In alternative embodiments, the shape of sacrificial layer 142 need not be "L" shaped.

In this step, first, a first oxide layer 141 is formed to cover the sidewalls and the bottom of the plurality of openings 120 and the trenches 130, and the first oxide layer 141 forms hollow pillars having openings in the plurality of openings 120 and the trenches 130; further, in the step of filling the sacrificial layer 142 in the hollow cylinder formed by the first oxide layer 141 in the plurality of openings 120 and forming the sacrificial layer 142 on the sidewall and the bottom of the hollow cylinder formed by the first oxide layer 141 in the trench 130, since the sizes of the openings 120 and the trench 130 are different greatly and the size of the openings 120 is much smaller than that of the trench 130, the sacrificial layer 142 can completely fill the openings 120 while the sacrificial layer 142 covers the bottom and the sidewall of the trench 130. Further, a second oxide layer 143 is deposited. Alternatively, by controlling the time and deposition rate of the deposition process for forming the sacrificial layer 142 and the second oxide layer 143, the total thickness of the sacrificial layer 142 and the second oxide layer 143 on the sidewall of the selection pipe is a predetermined value. Optionally, after forming the second oxide layer 143, performing a planarization process on the surface of the semiconductor structure; further, a groove 140 penetrating through the first oxide layer 141, the sacrificial layer 142 and the second oxide layer 143 is formed in the trench 130, the groove 140 serves as an implantation window, and the substrate 101 is ion-implanted through the groove 140, so as to form the active region 103, wherein the active region 103 can serve as a common source/drain region of adjacent select transistors. In this step, the recess 140 may be formed using anisotropic etching, for example, using dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, for example, by controlling the etching time such that the etching stops near the surface of the substrate 101.

Further, the second oxide layer 143 in the recess 140 is removed, as shown in fig. 5 c.

In this step, the second oxide layer 143 may be removed by anisotropic etching or isotropic etching, and the first oxide layer 141 partially located in the opening 120 is removed while the second oxide layer 143 is removed. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

Further, a third oxide layer 144 is formed to cover the surface of the semiconductor structure, a barrier layer 145 is formed on the surface of the third oxide layer 144, and a fourth oxide layer 146 is formed in the cavity formed by the barrier layer 145, as shown in fig. 5 d. Optionally, the barrier layer 145 is about one-half the thickness of the sacrificial layer 142. For example, the thickness of the sacrificial layer 142 is

The barrier layer 145 has a thickness of

In this embodiment, the thickness of barrier layer 145 should be less than the thickness of sacrificial layer 142, and barrier layer 145 and sacrificial layer 142 are the same material. In this step, for example, atomic layer deposition, physical vapor deposition or chemical vapor deposition is used to sequentially form the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146, and then the surface of the semiconductor structure is subjected to chemical mechanical polishing.

Further, the first oxide layer 141, the sacrificial layer 142, the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146 are etched back, as shown in fig. 5 e.

In this step, the first oxide layer 141, the sacrificial layer 142, the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146 may be etched back by using an anisotropic etching or an isotropic etching, so that the etching stops at a certain depth inside the semiconductor structure, and the sidewalls of the etched first oxide layer 141, sacrificial layer 142, third oxide layer 144, barrier layer 145 and fourth oxide layer 146 are perpendicular or approximately perpendicular to the substrate 101 as viewed from the cross-section shown in fig. 5 e.

Further, a part of the sacrificial layer 142 and a part of the barrier layer 145 are removed to form the first cavity 121, the second cavity 131 and the third cavity 132, as shown in fig. 5 f.

In this embodiment, the sacrificial layer 142 in the opening 120 is completely removed to form the first cavity 121, and a portion of the sacrificial layer 142 and a portion of the barrier layer 145 in the trench 130 are removed to form the second cavity 131 and the third cavity 132, respectively, wherein the second cavity 131 has a smaller size than the third cavity 132, and the width of the second cavity 131 is smaller than the width of the third cavity 132 when viewed in the cross-section shown in fig. 5 f.

Further, a fifth oxide layer 147 is formed overlying the semiconductor structure to form the first air gap 122 and the second air gap 134, as shown in FIG. 5 g. In this step, since the size of the second cavity 131 is smaller than that of the third cavity 132, the fifth oxide layer 147 completely fills the third cavity 132, thereby forming a second air gap 134 at the bottom of the second cavity 131; the size of the first cavity 121 is much smaller than that of the second cavity 131, so the fifth oxide layer 147 cannot completely fill the first cavity 121, and the fifth oxide layer 147 closes the top of the first cavity 121, thereby forming the first air gap 122.

Further, a contact structure 150 is formed through the insulating layer 148 and the barrier layer 145, the location of the contact structure 150 being connected to the active region 103, as shown in fig. 5 h. It should be understood that, for clarity of the drawing, the first oxide layer 141, the third oxide layer 144, the fourth oxide layer 146, and the fifth oxide layer 147 shown in fig. 5g are shown in fig. 5h as a whole, and the first oxide layer 141, the third oxide layer 144, the fourth oxide layer 146, and the fifth oxide layer 147 are collectively referred to as an insulating layer 148.

In this step, preferably, the etching process for forming the contact structure 150 is performed in a distributed manner, for example, using the barrier layer 145 as an etching stop layer to form the upper half of the contact hole, and then, the barrier layer 145 is etched and the insulating layer 148 between the barrier layer 145 and the substrate 101 is further etched, and then, the contact hole is filled with a metal conductor, such as metal tungsten, to form the contact structure 150, wherein the metal conductor provides an electrical connection path from the substrate 101 to a bit line (see the bit line contact structure DC shown in fig. 2). The step-wise etching step described above facilitates defining the location of etch stops in the etching process of the contact structure 150, thereby reducing the probability of underetching or overetching problems for the regions.

In this embodiment, since the L-shaped sacrificial layer 142 is formed in the step shown in fig. 5b, the sidewall thickness of the sacrificial layer 142 is reduced, and thus the third oxide layer 144 and the barrier layer 145 are correspondingly offset in a direction away from the contact structure 150, in the finally formed semiconductor device, the barrier layer 145 is stepped, the distance between the first end and the second end of the barrier layer 145 and the contact structure is increased, and since the second air gap 134 is connected to the contact structure 150 via the barrier layer 145, the possibility that the second air gap 134 is in contact with the contact structure is greatly reduced, and the yield and reliability of the semiconductor device are improved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (17)

1. A semiconductor device, comprising:

a substrate;

a gate stack structure on the substrate;

a plurality of openings penetrating the gate stack structure to form a plurality of word lines spaced apart from each other in the gate stack structure;

a slot penetrating through the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line;

the sacrificial layer, the barrier layer and the contact structure are positioned in the groove;

a bit line over the substrate, the bit line electrically connected to the common source drain region of the adjacent select transistor via the contact structure;

an insulating layer for forming a first air gap within the plurality of openings and for achieving electrical isolation between the barrier layer, the contact structure and the gate stack structure,

wherein the contact structure penetrates through the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and part of the barrier layer extends to the upper part of the sacrificial layer.

2. The semiconductor device of claim 1, wherein there is a second air gap at the first end and/or the second end of the barrier layer.

3. The semiconductor device according to claim 1, wherein the insulating layer comprises a first oxide layer, a third oxide layer, a fourth oxide layer, and a fifth oxide layer, the first oxide layer, the sacrificial layer, the third oxide layer, the barrier layer, and the fourth oxide layer are sequentially stacked on the substrate, and the fifth oxide layer is at least filled in a cavity formed by removing the sacrificial layer and the barrier layer on the sidewall of the trench, so as to form the second air gap.

4. The semiconductor device according to claim 1, wherein the sacrificial layer and the barrier layer are the same material.

5. The semiconductor device of claim 1, wherein a thickness of the barrier layer is less than a thickness of the sacrificial layer.

6. The semiconductor device of claim 1, further comprising a third air gap over the sacrificial layer.

7. A method of manufacturing a semiconductor device, comprising:

forming a gate stack structure on a substrate;

forming a plurality of openings penetrating through the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure;

forming a slot penetrating through the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection tubes in the gate stack structure, wherein the slot isolates the first selection control gate line from the second selection control gate line;

forming a first oxide layer, wherein the first oxide layer covers the side walls of the word lines and the side walls of the first selection control grid line and the second selection control grid line;

forming a sacrificial layer which fills and covers gaps between the side walls of the word lines and the first oxidation layer;

forming a second oxide layer covering the sacrificial layer;

partially removing the sacrificial layer, the first oxide layer and the second oxide layer in the groove to form an injection window;

removing the remaining second oxide layer;

sequentially forming a third oxide layer, a barrier layer and a fourth oxide layer;

partially removing the sacrificial layer and the barrier layer to form a first air gap between the plurality of word lines;

forming a fifth oxide layer covering the gate stack structure, the opening and the slot; forming a contact structure located within the slot.

8. The manufacturing method according to claim 7, wherein the material of the sacrificial layer and the barrier layer is the same.

9. The manufacturing method according to claim 7, further comprising, after forming the sacrifice layer:

and carrying out ion implantation on the substrate through the implantation window to form a common source drain region of the adjacent selection tubes.

10. The method of claim 7, wherein the sacrificial layer in the trench is "L" shaped after the implantation window is formed.

11. The method of manufacturing of claim 7, wherein the contact structure extends through the insulating layer and the barrier layer, the sacrificial layer and the barrier layer being separated by the insulating layer, a portion of the barrier layer extending over the sacrificial layer.

12. A semiconductor device, comprising:

a substrate;

the gate stack structure is positioned on the substrate and comprises gate stacks of the storage units and gate stacks of the selection tubes;

wherein, a sacrificial layer, a barrier layer, an insulating layer and a contact structure penetrating through the barrier layer and the insulating layer are arranged between the gate stacks of two adjacent selection tubes, the contact structure is connected with the common source drain region of the two adjacent selection tubes,

the sacrificial layer and the barrier layer are separated by the insulating layer, with a portion of the barrier layer extending over the sacrificial layer.

13. The semiconductor device of claim 12, further comprising a first air gap between gate stacks of adjacent memory cells.

14. The semiconductor device according to claim 12, wherein the sacrificial layer and the barrier layer are the same material.

15. The semiconductor device of claim 12, wherein a thickness of the barrier layer is less than a thickness of the sacrificial layer.

16. The semiconductor device of claim 12, wherein the semiconductor structure further comprises a second air gap located on both sides of the barrier layer.

17. The semiconductor device according to any one of claims 12 to 16, wherein the semiconductor device is a NAND flash memory.

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