CN114253790A

CN114253790A - MCU double-wire debugging circuit and MCU double-wire debugging method

Info

Publication number: CN114253790A
Application number: CN202111357769.5A
Authority: CN
Inventors: 王浩远
Original assignee: Foshan Jusheng Microelectronics Co ltd
Current assignee: Foshan Jusheng Microelectronics Co ltd
Priority date: 2021-11-15
Filing date: 2021-11-15
Publication date: 2022-03-29

Abstract

The invention discloses an MCU double-wire debugging circuit and an MCU double-wire debugging method, wherein the MCU double-wire debugging circuit comprises a communication protocol processing module and an event processing module; the communication protocol processing module is used for carrying out information interaction with an off-chip debugger according to a communication protocol; the event processing module is electrically connected with the communication protocol processing module and is used for executing corresponding actions according to the received debugging instructions, wherein the actions include at least one of controlling a CPU of the MCU, accessing an SRAM in the MCU and accessing a FLASH in the MCU, and internal data are transmitted to the debugger through the communication protocol processing module. According to the MCU double-line debugging circuit, the communication protocol processing module provides a high-reliability communication interaction mode, and communication can be completed only by using two IO interfaces; the event processing module provides rich debugging functions, and facilitates program debugging of software developers.

Description

MCU double-wire debugging circuit and MCU double-wire debugging method

Technical Field

The invention relates to the technical field of chip debugging, in particular to an MCU (microprogrammed control unit) double-line debugging circuit and an MCU double-line debugging method.

Background

With the rapid development of chip design technology, the requirements of MCU chips on PIN functions are higher and higher, and solution manufacturers tend to implement richer application functions with chips with fewer PINs.

The mainstream debugging interfaces of the existing MCU chip in the market have three types: four wire debug, two wire debug and single wire debug. The four-wire debugging interface is generally a standard JTAG interface, needs to occupy four IO interfaces in a chip, causes that the four IO interfaces cannot be used as a function PIN in a debugging process, is unfriendly for simulation debugging in a scheme development process, and increases hardware complexity in the debugging process by the four wires. The single-wire debugging interface reduces the IO occupancy rate to the minimum, but is difficult to implement, and the reliability and the debugging speed are difficult to guarantee. The two-wire debugging is the most mainstream debugging mode in the current market, but a unified implementation scheme is not provided, and the SWD debugging interface of the ARM core has the highest popularity, but is only suitable for chips using the ARM core. Therefore, it is important to provide a low-cost, fast and reliable debugging interface in the MCU chip design.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides the MCU two-wire debugging circuit, which improves the debugging efficiency and the reliability.

The invention also provides an MCU double-line debugging method.

In a first aspect, an MCU two-wire debug circuit according to an embodiment of the present invention includes: the communication protocol processing module and the event processing module are electrically connected in sequence; the communication protocol processing module is used for carrying out information interaction with an off-chip debugger according to a communication protocol; the event processing module is used for executing corresponding actions according to the received debugging instructions, including but not limited to controlling a CPU of the MCU, accessing an SRAM in the MCU, accessing a FALSH in the MCU, and transmitting the acquired internal data to the debugger through the communication protocol processing module; wherein, the communication protocol processing module comprises: the level detection circuit is electrically connected with the debugger through two IO interfaces of the MCU, wherein one IO interface is used for transmitting a clock signal, the other IO interface is used for transmitting a debugging instruction, and the level detection circuit is used for detecting the level state of the debugging instruction according to the clock signal; the shift register is electrically connected with the level detection circuit and is used for carrying out serial-parallel conversion on the debugging instruction; the level state counter is electrically connected with the level detection circuit and is used for counting the high/low level state of the debugging instruction; the debugging instruction judging circuit is electrically connected with the shift register and the level state counter respectively and used for judging whether the debugging instruction which completes serial-parallel conversion accords with a preset instruction code or not; the communication mode state machine is electrically connected with the debugging instruction judging circuit, and when the debugging instruction accords with a preset instruction code, the communication mode state machine enters a corresponding state according to the corresponding debugging instruction; the debugging instruction transmitter is electrically connected with the communication mode state machine and transmits the debugging instruction to the event processing module after the communication mode state machine enters a corresponding state; the data buffer is used for buffering the internal data sent by the event processing module; and the communication encoder is electrically connected with the data buffer and is used for encoding the internal data and sending the internal data to the debugger.

The MCU double-line debugging circuit provided by the embodiment of the invention at least has the following beneficial effects: the communication protocol processing module provides a high-reliability communication interaction mode, and communication can be completed only by using two IO interfaces; the event processing module provides rich debugging functions, and facilitates program debugging of software developers; besides the behavior of the CPU and the type and the number of breakpoints can be controlled, the internal SRAM and FALSH can be directly accessed, and the richness of debugging functions is outstanding.

According to some embodiments of the present invention, the communication protocol processing module further includes a response processing circuit, an input terminal of the response processing circuit is electrically connected to an output terminal of the communication mode state machine, an output terminal of the response processing circuit is electrically connected to the debugger, and the response processing circuit is configured to send a response signal to the debugger every time a piece of communication data is received.

According to some embodiments of the invention, the event processing module comprises: the debugging instruction receiver is used for receiving the debugging instruction sent by the communication protocol processing module; the event processing state machine is electrically connected with the debugging instruction receiver and used for entering a corresponding event state according to the debugging instruction; the CPU control interface is electrically connected with the event processing state machine and the CPU respectively; the SRAM access interface is electrically connected with the event processing state machine and the SRAM respectively; and the FALSH access interface is electrically connected with the event processing state machine and the FALSH respectively.

According to some embodiments of the invention, the event processing module further comprises an internal register access interface for accessing internal registers of the event processing module.

In a second aspect, the MCU two-wire debugging method according to the embodiments of the present invention includes the following steps: the debugger outside the chip sends a clock signal and a debugging instruction to the level detection circuit; the level detection circuit detects the level state of the debugging instruction according to the clock signal and sends the debugging instruction to a shift register for serial-parallel conversion; the debugging instruction judging circuit judges whether the debugging instruction which completes the serial-parallel conversion accords with a preset instruction code, and if so, the debugging instruction is sent to the event processing module through the communication mode state machine and the debugging instruction sender; and the event processing module executes corresponding actions according to the debugging instructions and sends the obtained internal data to the debugger through the data buffer and the communication encoder.

The MCU double-line debugging method provided by the embodiment of the invention at least has the following beneficial effects: for traditional four-wire debugging interface, this design only need occupy two IO interfaces and just can accomplish the debugging function, and an IO interface is used for transmitting clock signal, and an IO interface is used for transmitting the debugging instruction, and the debugging instruction is according to clock beat transmission, consequently, need not rely on MCU's clock communication itself, also need not reserve the sampling window simultaneously, has also improved the reliability when improving communication efficiency.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic structural diagram of an MCU two-wire debugging circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a communication protocol processing module according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an event processing module according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating steps of a MCU two-wire debugging method according to an embodiment of the present invention;

reference numerals:

the device comprises a communication protocol processing module 100, a level detection circuit 110, a shift register 120, a level state counter 130, a debugging instruction judging circuit 140, a communication mode state machine 150, a debugging instruction transmitter 160, a data buffer 170, a communication encoder 180, a response processing circuit 190, an event processing module 200, a debugging instruction receiver 210, an event processing state machine 220, a CPU control interface 230, an SRAM access interface 240, a FLASH access interface 250, an internal register access interface 260, a CPU300, an SRAM400 and a FLASH 500.

Detailed Description

Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

In a first aspect, as shown in fig. 1, an MCU two-wire debug circuit according to an embodiment of the present invention includes a communication protocol processing module 100 and an event processing module 200; the communication protocol processing module 100 is configured to perform information interaction with an off-chip debugger according to a communication protocol; the event processing module 200 is electrically connected to the communication protocol processing module 100, and the event processing module 200 is configured to execute corresponding actions according to the received debugging instruction, including but not limited to controlling the CPU300 of the MCU, accessing the SRAM400 inside the MCU, accessing the false sh500 inside the MCU, and transmitting the obtained internal data to the debugger through the communication protocol processing module 100. The communication protocol processing module 100 specifically includes a level detection circuit 110, a shift register 120, a level state counter 130, a debug instruction determination circuit 140, a communication mode state machine 150, a debug instruction transmitter 160, a data buffer 170, and a communication encoder 180. The level detection circuit 110 is electrically connected to the debugger through two IO interfaces of the MCU, one of the IO interfaces is used for transmitting a clock signal DEBUG _ CLK, the other IO interface is used for transmitting a DEBUG instruction DEBUG _ DAT, and the level detection circuit 110 is used for detecting a level state of the DEBUG instruction according to the clock signal, that is, detecting a level state of the DEBUG _ DAT on a rising edge of the clock; under the default condition, the IO interface corresponding to the DEBUG _ CLK is in an internal pull-up state, and interference caused by unstable level state due to floating is avoided. The shift register 120 is electrically connected to the level detection circuit 110, and is configured to perform serial-to-parallel conversion on the DEBUG instruction, that is, buffer the single bit signal input by DEBUG _ DAT, and complete serial-to-parallel conversion. The level state counter 130 is electrically connected to the level detection circuit 110, and the level state counter 130 is used for counting the DEBUG command DEBUG _ DAT maintained in a high/low level state, so that the system can determine whether the data transmission is incorrect. The debug instruction determining circuit 140 is electrically connected to the shift register 120 and the level state counter 130, respectively, and is configured to determine whether the debug instruction that has completed serial-to-parallel conversion matches a preset instruction code; for each instruction code, there is a fixed header, so that for the data that completes serial-to-parallel conversion, it is first determined whether its header conforms to the agreed protocol, and then it is determined whether the debug instruction following the header is the agreed instruction code. When the received data conforms to the communication protocol and conforms to the predetermined command code, the communication mode state machine 150 enters a corresponding state according to the corresponding debugging command. After the communication mode state machine 140 enters the corresponding state, the debug instruction transmitter 160 transmits a debug instruction to the event processing module 200. The data buffer 170 is used to buffer the internal data that the MCU needs to send to the off-chip debugger. The communication encoder 180 is used to encode the internal data and send it to the debugger off-chip.

Specifically, the communication protocol processing module 100 is responsible for communicating with an off-chip debugger, including interpreting and judging a received signal according to a communication protocol, and outputting internal data; the event processing module 200 is responsible for executing corresponding control actions on the received instructions, including controlling the CPU300, accessing the internal SRAM400, accessing the internal FLASH500, and the like. The whole MCU double-line debugging circuit is a bridge for communication between an external debugger and the interior of the MCU, the external debugger initiates communication, the communication protocol processing module 100 receives communication signals, interprets a protocol and transmits an obtained correct instruction to the event processing module 200; the event processing module 200 respectively executes corresponding control operations on the CPU300, the SRAM400, the FLASH500, and the like according to the instruction task; when internal data needs to be transmitted to an external debugger through a debug interface, the event processing module 200 obtains the data, and then transmits the data to the communication protocol processing module 100 for outward transmission according to a conventional communication protocol.

According to the MCU two-wire debugging circuit disclosed by the embodiment of the invention, compared with the traditional four-wire debugging interface, the debugging function can be completed only by occupying two IO interfaces, one IO interface is used for transmitting a clock signal DEBUG _ CLK, the other IO interface is used for transmitting a debugging instruction DEBUG _ DAT, and the debugging instruction is transmitted according to the clock beat, so that clock communication of the MCU is not required to be relied on, a sampling window is not required to be reserved, and the reliability is improved while the communication efficiency is improved.

Further, as shown in fig. 2, in some embodiments of the present invention, the communication protocol processing module 100 further includes a response processing circuit 190, an input terminal of the response processing circuit 190 is electrically connected to an output terminal of the communication mode state machine 150, an output terminal of the response processing circuit 190 is electrically connected to the debugger, and the response processing circuit 190 is configured to send a response signal to the debugger every time a piece of communication data is received. The accuracy of communication is ensured by the response signal fed back to the debugger outside the chip by the response processing circuit 190.

As shown in fig. 3, the event processing module 200 includes a debug instruction receiver 210, an event processing state machine 220, a CPU control interface 230, an SRAM access interface 240, and a FLASH access interface 250; the debug instruction receiver 210 is configured to receive a debug instruction sent by the communication protocol processing module 100; the event processing state machine 220 is used for entering a corresponding event state according to the debugging instruction; the CPU control interface 230 is electrically connected to the event processing state machine 220 and the CPU300, respectively; the SRAM access interface 240 is electrically connected to the event processing state machine 220 and the SRAM400, respectively; the FLASH access interface 250 is electrically connected to the event processing state machine 220 and the FLASH500, respectively.

Specifically, the event processing module 200 operates in a high frequency clock domain, asynchronous to the clock of the communication protocol processing module 100, and therefore, an asynchronous transition needs to be made at the debug instruction receiver 210. The event states that are primarily processed by the event processing state machine 220 include, but are not limited to: the CPU300 is controlled to operate through the CPU control interface 230, the SRAM400 is accessed through the SRAM access interface 240, and the FLASH500 is accessed through the FLASH access interface 250. The CPU control interface 230 is used for controlling the CPU300 to suspend running, run at full speed, reset, execute a single step, and the like, and can set the breakpoint type, the breakpoint position, the breakpoint number, and the like during the running of the CPU 300. And an SRAM access interface 240 for generating a read/write control signal for the SRAM400 to perform a single access or a continuous access to the SRAM 400. And a FLASH access interface 250 for generating read/write control signals of the FLASH500 to perform single access or continuous access to the false sh 500. Finally, the acquired internal data is sent to the communication protocol processing module 100, and the communication protocol processing module 100 sends the internal data to an external debugger.

In addition, as shown in fig. 3, the event processing module 200 further includes an internal register access interface 260, and the internal register access interface 260 is used for reading/writing special function registers inside the event processing module 200.

In summary, the MCU two-wire debugging circuit according to the embodiment of the present invention:

1. the communication protocol processing module 100 provides a high-reliability communication interaction mode, and communication can be completed only by using two IO interfaces;

2. the event processing module 200 provides rich debugging functions, which is convenient for software developers to debug programs. Besides the behavior of the CPU300 and the type and number of breakpoints can be controlled, the internal SRAM400 and false sh500 can be directly accessed, and the richness of the debugging function is prominent.

3. The communication protocol processing module 100 and the event processing module 200 work in different clock domains, which not only can ensure the reliability of communication, but also can enable the internal event processing to be executed at high speed, and ensure the debugging efficiency.

In a second aspect, as shown in fig. 4, the MCU two-wire debugging method according to the embodiment of the present invention includes the following steps:

s100: the off-chip debugger sends the clock signal DEBUG _ CLK and the DEBUG command DEBUG _ DAT to the level detection circuit 110;

s200: the level detection circuit 110 detects the level state of the debug instruction according to the clock signal, and sends the debug instruction to the shift register 120 for serial-to-parallel conversion;

the level detection circuit 110 detects the level state of DEBUG _ DAT at the rising edge of the clock by using DEBUG _ CLK as the working clock; under the default condition, the IO interface corresponding to the DEBUG _ CLK is in an internal pull-up state, and interference caused by unstable level state due to floating is avoided. Subsequently, the level detection circuit 110 sends the debug instruction to the shift register 120 and the level state counter 130; the shift register 120 is used for caching the single bit signal of DEBUG _ DAT and completing serial-parallel conversion; the level state counter 130 is used to count that DEBUG _ DAT remains in a high/low state.

S300: the debug instruction determining circuit 140 determines whether the debug instruction having completed the serial-to-parallel conversion meets a preset instruction code, and if yes, sends the debug instruction to the event processing module 200 through the communication mode state machine 150 and the debug instruction transmitter 160;

for each instruction code, there is a fixed header, so as to determine whether the header of the data that completes serial-to-parallel conversion conforms to the agreed protocol, and then determine whether the debug instruction following the header is the agreed instruction code. When the received data conforms to the communication protocol and conforms to the predetermined command code, the communication mode state machine 150 enters a corresponding state according to the corresponding debugging command. After communication mode state machine 150 enters the corresponding state, debug instruction transmitter 160 transmits debug instructions to event processing module 200.

S400: the event processing module 200 executes corresponding actions according to the debugging instructions, and sends the obtained internal data to the debugger through the data buffer 170 and the communication encoder 180.

The event processing module 200 includes a debug instruction receiver 210, an event processing state machine 220, a CPU control interface 230, an SRAM access interface 240, a FLASH access interface 250, and an internal register access interface 260. The event processing module 200 operates in a high frequency clock domain, asynchronous to the clock of the communication protocol processing module 100, and therefore, an asynchronous transition needs to be made at the debug instruction receiver 210. The event states that are primarily processed by the event processing state machine 220 include, but are not limited to: the CPU300 is controlled to operate through the CPU control interface 230, the SRAM400 is accessed through the SRAM access interface 240, the FLASH500 is accessed through the FLASH access interface 250, and the internal register of the time processing module 200 is accessed through the internal register access interface 260. The CPU control interface 230 is used for controlling the CPU300 to suspend running, run at full speed, reset, execute a single step, and the like, and can set the breakpoint type, the breakpoint position, the breakpoint number, and the like during the running of the CPU 300. And an SRAM access interface 240 for generating a read/write control signal for the SRAM400 to perform a single access or a continuous access to the SRAM 400. And a FLASH access interface 250 for generating read/write control signals of the FLASH500 to perform single access or continuous access to the false sh 500. The internal register access interface 260 is used to read/write special function registers inside the event processing module 200. The event processing module 200 finally sends the acquired internal data to the data buffer 170 of the communication protocol processing module 100, the data buffer 170 buffers the internal data, and the communication encoder 180 encodes the internal data and sends the encoded internal data to the off-chip debugger.

According to the MCU two-wire debugging method disclosed by the embodiment of the invention, compared with the traditional four-wire debugging interface, the debugging function can be completed only by occupying two IO interfaces, one IO interface is used for transmitting the clock signal DEBUG _ CLK, the other IO interface is used for transmitting the debugging instruction DEBUG _ DAT, and the debugging instruction is transmitted according to the clock beat, so that clock communication of the MCU is not required to be relied on, a sampling window is not required to be reserved, and the reliability is improved while the communication efficiency is improved.

In the description herein, references to the description of "one embodiment," "a further embodiment," "some specific embodiments," or "some examples," etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. The MCU double-line debugging circuit is characterized by comprising a communication protocol processing module and an event processing module which are electrically connected in sequence; the communication protocol processing module is used for carrying out information interaction with an off-chip debugger according to a communication protocol; the event processing module is used for executing corresponding actions according to the received debugging instructions, including but not limited to controlling a CPU of the MCU, accessing an SRAM in the MCU, accessing a FALSH in the MCU, and transmitting the acquired internal data to the debugger through the communication protocol processing module;

wherein, the communication protocol processing module comprises:

the level detection circuit is electrically connected with the debugger through two IO interfaces of the MCU, wherein one IO interface is used for transmitting a clock signal, the other IO interface is used for transmitting a debugging instruction, and the level detection circuit is used for detecting the level state of the debugging instruction according to the clock signal;

the shift register is electrically connected with the level detection circuit and is used for carrying out serial-parallel conversion on the debugging instruction;

the level state counter is electrically connected with the level detection circuit and is used for counting the high/low level state of the debugging instruction;

the debugging instruction judging circuit is electrically connected with the shift register and the level state counter respectively and used for judging whether the debugging instruction which completes serial-parallel conversion accords with a preset instruction code or not;

the communication mode state machine is electrically connected with the debugging instruction judging circuit, and when the debugging instruction accords with a preset instruction code, the communication mode state machine enters a corresponding state according to the corresponding debugging instruction;

the debugging instruction transmitter is electrically connected with the communication mode state machine and transmits the debugging instruction to the event processing module after the communication mode state machine enters a corresponding state;

the data buffer is used for buffering the internal data sent by the event processing module;

and the communication encoder is electrically connected with the data buffer and is used for encoding the internal data and sending the internal data to the debugger.

2. The MCU double-line debugging circuit of claim 1, wherein the communication protocol processing module further comprises a response processing circuit, an input terminal of the response processing circuit is electrically connected to an output terminal of the communication mode state machine, an output terminal of the response processing circuit is electrically connected to the debugger, and the response processing circuit is configured to send a response signal to the debugger when each piece of communication data is received.

3. An MCU two-wire debug circuit according to claim 1 or 2, wherein the event processing module comprises:

the debugging instruction receiver is used for receiving the debugging instruction sent by the communication protocol processing module;

the event processing state machine is electrically connected with the debugging instruction receiver and used for entering a corresponding event state according to the debugging instruction;

the CPU control interface is electrically connected with the event processing state machine and the CPU respectively;

the SRAM access interface is electrically connected with the event processing state machine and the SRAM respectively;

and the FALSH access interface is electrically connected with the event processing state machine and the FALSH respectively.

4. The MCU two-wire debugging circuit of claim 3, wherein the event processing module further comprises an internal register access interface for accessing internal registers of the event processing module.

5. An MCU two-wire debugging method based on the MCU two-wire debugging circuit of any one of claims 1 to 4, comprising the steps of:

the debugger outside the chip sends a clock signal and a debugging instruction to the level detection circuit;

the level detection circuit detects the level state of the debugging instruction according to the clock signal and sends the debugging instruction to a shift register for serial-parallel conversion;

the debugging instruction judging circuit judges whether the debugging instruction which completes the serial-parallel conversion accords with a preset instruction code, and if so, the debugging instruction is sent to the event processing module through the communication mode state machine and the debugging instruction sender;

and the event processing module executes corresponding actions according to the debugging instructions and sends the obtained internal data to the debugger through the data buffer and the communication encoder.