CN114244116B - Mode discrimination circuit for BUCK-BOOST controller - Google Patents

Mode discrimination circuit for BUCK-BOOST controller Download PDF

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Publication number
CN114244116B
CN114244116B CN202111570446.4A CN202111570446A CN114244116B CN 114244116 B CN114244116 B CN 114244116B CN 202111570446 A CN202111570446 A CN 202111570446A CN 114244116 B CN114244116 B CN 114244116B
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mos tube
electrode
circuit
voltage
buck
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CN114244116A (en
Inventor
廖鹏飞
雷旭
杨丰
李鹏
黄晓宗
王国强
霍改青
曾欣
刘婷
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CETC 24 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the field of power management circuits, and particularly relates to a mode judging circuit for a BUCK-BOOST controller, which comprises the following components: the voltage-to-current circuit, the logic operation circuit, the sawtooth wave generation circuit and the comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive electrode input end of the comparator, and the sawtooth wave generating circuit is connected with the negative electrode input end of the comparator to form a mode distinguishing circuit; the invention designs a mode judging circuit applied to a BUCK-BOOST controller, which outputs a signal according to the relation between input voltage and output voltage in the BUCK-BOOST controller, and the signal can control a BUCK-BOOST controller chip to work in three different working states so as to realize smooth switching between modes, and maintain the stability of a loop and the constancy of the output voltage.

Description

Mode discrimination circuit for BUCK-BOOST controller
Technical Field
The invention belongs to the field of power management circuits, and particularly relates to a mode judging circuit for a BUCK-BOOST controller.
Background
A switching power supply is a power supply that maintains a stable output voltage, and is generally composed of a Pulse Width Modulation (PWM) control IC and a MOSFET. With the development and innovation of power electronics technology, the technology of switching power supplies is also continuously innovating. At present, a switching power supply can be divided into a BUCK-type (BUCK) converter, a BOOST-type (BOOST) converter and a BOOST-type (BUCK-BOOST) converter according to the relation between an input voltage and an output voltage, wherein the BUCK converter can only realize a BUCK function, and the BOOST converter can only realize a BOOST function; the traditional BUCK-BOOST converter can realize the BUCK function and the BOOST function, as shown in fig. 1, when the input voltage is far higher than the output voltage, VG2 can be turned off through logic control, at the moment, the BUCK-BOOST converter is simplified into a BUCK controller, and when the BUCK-BOOST converter works, VG1 is only in switching action, so that the loss of a circuit is reduced, and the conversion efficiency is improved; when the input voltage is close to the output voltage or the input voltage is lower than the output voltage, the power supply works in a BUCK-BOOST mode; the mode discrimination circuit is therefore a critical circuit in the multi-mode BUCK-BOOST controller; the conventional mode discriminating circuit directly compares the input voltage with the output voltage through the comparator, outputs a signal representing two states of "0" and "1", and can only control two modes, and for controlling other modes, a mode discriminating circuit capable of controlling a plurality of modes is urgently needed.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a mode discrimination circuit for a BUCK-BOOST controller, the circuit comprising: the voltage-to-current circuit, the logic operation circuit, the sawtooth wave generation circuit and the comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive electrode input end of the comparator, and the sawtooth wave generating circuit is connected with the negative electrode input end of the comparator to form the mode distinguishing circuit.
Preferably, the voltage-to-current circuit comprises two resistors, four MOS transistors and two current sources; first current source I BIAS1 One end of the first MOS tube M1 is connected with the voltage input end VDD, and the other end of the first MOS tube M1 is connected with the drain electrode of the fourth MOS tube M4; the grid electrode of the first MOS tube M1 is respectively connected with the grid electrode and the drain electrode of the second MOS tube M2, and the source electrode of the first MOS tube M1 is connected with the first resistor R1; second current source I BIAS2 One end of the first capacitor is connected with the voltage input end VDD, and the other end is connected with the second capacitorA drain electrode of the MOS tube M2; the source electrode of the second MOS tube M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with the voltage input end V IN The grid electrode is connected with a voltage input end VDD, and the source electrode is connected with the source electrode of the first MOS tube M1; drain electrode of fourth MOS tube M4 and current output end I OUT The source electrode is connected with the source electrode of the second MOS tube M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit.
Further, the resistance values of the first resistor R1 and the second resistor R2 in the voltage-to-current circuit are equal.
Preferably, the logic operation circuit comprises 14 MOS tubes, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS tube M6; the source electrode of the sixth MOS tube M6 is connected with the drain electrode of the seventh MOS tube M7, and the grid electrode is respectively connected with the grid electrode of the eighth MOS tube M8, the grid electrode of the tenth MOS tube M10, the grid electrode of the eleventh MOS tube M11, the grid electrode of the fourteenth MOS tube M14 and the second capacitor C C And the drain electrode of the eighteenth MOS tube M18 is connected; the source electrode of the seventh MOS tube M7 is connected with the current output end I OUT The method comprises the steps of carrying out a first treatment on the surface of the One end of the third resistor R3 is connected with the voltage input end, and the other end of the third resistor R3 is connected with the drain electrode of the eighth MOS tube M8; the source electrode of the eighth MOS tube M8 is respectively connected with the grid electrode of the thirteenth MOS tube M13 and the drain electrode of the ninth MOS tube M9; the source electrode of the ninth MOS transistor M9 is connected with the current input end I IN The grid electrode is connected with the grid electrode of the seventh MOS tube M7 and then connected with the source electrode of the tenth MOS tube M10; the drain electrode of the tenth MOS tube M10 is connected with the voltage input end, and the grid electrode of the tenth MOS tube M11 is connected with the grid electrode; the source electrode of the eleventh MOS tube M11 is connected with the drain electrode of the twelfth MOS tube M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode is connected with the drain electrode of the seventh MOS tube M7; the source electrode of the fifteenth MOS tube M15 and the drain electrode of the sixteenth MOS tube M16 are respectively connected with the voltage input end, and the grid electrodes of the M15 and the M16 are respectively connected with the grid electrode of the nineteenth MOS tube M19 and the source electrode of the M15 after being connected with each other; the drain electrode of the fourteenth MOS tube M14 is respectively connected with the source electrode of the M15 and the second capacitor C C Is connected with one end of the second capacitor C C The source electrode is connected with the drain electrode of the thirteenth MOS tube M13; the grid electrode of the thirteenth MOS tube M13 is connected with the source electrode of the ninth MOS tube M9The source electrode is connected with a fifth resistor R5, and the resistor R5 is grounded; sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source I BIAS4 The input end of the seventeenth MOS tube M17, the drain electrode of the seventeenth MOS tube M17 and the grid electrode of the seventeenth MOS tube M17 are connected; the grid of M17 is connected with the grid of an eighteenth MOS tube M18, the source of M17 and a fourth current source I BIAS4 The output end of which is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source I BIAS5 An output terminal of (a); i BIAS5 The input end of the voltage transformer is connected with the voltage input end; the drain electrode of the nineteenth MOS tube M19 is connected with the voltage input end, and the source electrodes are respectively connected with the voltage output end V INT And a sixth resistor R6, the other end of which is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end V INT A logic operation circuit is formed.
Preferably, the mode discrimination circuit is based on the input voltage V in the BUCK-BOOST controller IN And output voltage V OUT Enter different modes of operation; when V is OUT ＜V IN －V OS1 When the mode judging circuit outputs a low level, the BUCK-BOOST controller is in the BUCK mode; when V is IN －V OS1 ≤V OUT ≤V IN +V OS2 When the signal output by the mode distinguishing circuit is square wave signal, the duty ratio of the square wave signal is V OUT Increasing with increasing BUCK-BOOST controller in switching mode; when V is IN +V OS2 ≤V OUT When the mode judging circuit outputs a high level, the BUCK-BOOST controller is in the BUCK-BOOST mode; wherein V is OS1 And V OS2 All represent offset voltages.
Further, V in the mode discriminating circuit OUT ＜V IN －V OS1 When the output voltage of the logic operation circuit is 0, i.e. V INT ＝0。
Further, the mode discriminating circuit V IN －V OS1 ≤V OUT ≤V IN +V OS2 At the time with V OUT Increase, flow through M 13 、M 15 、M 19 The current of the logic operation circuit gradually increases, and the output voltage V of the logic operation circuit INT Gradually increasing.
Further, the method comprises the steps of,v in mode discrimination circuit IN +V OS2 ≤V OUT When the output voltage of the logic operation circuit is V INT ＝(I BIAS5 +I BIAS4 ) R6, wherein I BIAS5 Indicating the current level of the fifth current source, I BIAS4 The current level of the fourth current source is represented, and R6 represents the resistance value of the sixth resistor.
The invention designs a mode judging circuit applied to a BUCK-BOOST controller, which outputs a mode judging signal according to the relation between input voltage and output voltage in the BUCK-BOOST controller, and the duty ratio of the signal represents three states and can be used for a multi-mode BUCK-BOOST controller chip, so that smooth switching between modes can be realized, and the stability of a loop and the constancy of the output voltage are maintained.
Drawings
FIG. 1 is a schematic diagram of a conventional BUCK-BOOST converter topology;
FIG. 2 is a schematic diagram of a mode decision circuit for a BUCK-BOOST controller according to the present invention;
FIG. 3 is a voltage-to-current circuit diagram of the present invention;
FIG. 4 is a diagram of a logic operation circuit according to the present invention;
FIG. 5 is a graph of the output voltage of the mode decision circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The topology of the BUCK-BOOST converter is shown in figure 1, and the circuit is as follows: input voltage source VIN, MOS transistor M20, first diode D1, inductor L, MOS, transistor M21, second diode D2, capacitor C, and resistor RL; the anode of the input voltage source VIN is connected with the drain electrode of the MOS tube M20, and the cathode is grounded; the grid electrode of the MOS tube M20 is connected with the first voltage input end VG1, and the source electrode of the MOS tube M is respectively connected with the cathode of the first diode D1 and the inductor L; the positive electrode of the first diode D1 is grounded; the other end of the inductor L is respectively connected with the anode of the second diode D2 and the drain electrode of the MOS tube M21; the grid electrode of the MOS tube M21 is connected with the second voltage input end VG2, and the source electrode is grounded; the cathode of the second diode D2 is respectively connected with the capacitor C, the resistor RL and the voltage output end VOUT; the other ends of the capacitor C and the resistor RL are grounded to form a BUCK-BOOST converter topology.
When the BUCK-BOOST converter is adopted, when the on duty ratio of the first voltage input end VG1 and the second voltage input end VG2 is D, the output voltage of the converter is:
wherein V is OUT Represents the output voltage of the BUCK-BOOST converter, D represents the on-duty ratio of the first voltage input VG1 and the second voltage input VG2, V IN Representing the voltage of the input voltage source VIN.
The duty ratio D is adjusted according to the output voltage formula of the converter, so that an output voltage greater than (less than or equal to) the input voltage can be obtained. Therefore, the constant output voltage can be maintained in a wide input voltage range, and the constant output voltage can be widely applied to occasions such as automobile electronics, industrial power supply and the like.
When the input voltage is far higher than the output voltage, VG2 can be turned off through logic control, the BUCK-BOOST converter is simplified into a BUCK controller, and VG1 is only in switching action during operation, so that loss is caused, and conversion efficiency is improved. When the input voltage is close to the output voltage or the input voltage is lower than the output voltage, the system operates in a BUCK-BOOST mode.
A mode discrimination circuit for a BUCK-BOOST controller, as shown in fig. 2, the circuit comprising: the voltage-to-current circuit, the logic operation circuit, the sawtooth wave generation circuit and the comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive electrode input end of the comparator, and the sawtooth wave generating circuit is connected with the negative electrode input end of the comparator to form the mode distinguishing circuit.
A voltage to current circuit, as shown in fig. 3, the circuit comprising: two resistors, four MOS tubes and two current sources; first current source I BIAS1 One end of the first MOS tube M1 is connected with the voltage input end VDD, and the other end of the first MOS tube M1 is connected with the drain electrode of the fourth MOS tube M4; the grid electrode of the first MOS tube M1 is respectively connected with the grid electrode and the drain electrode of the second MOS tube M2, and the source electrode of the first MOS tube M1 is connected with the first resistor R1; second current source I BIAS2 One end of the second MOS tube M2 is connected with the voltage input end VDD; the source electrode of the second MOS tube M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with the voltage input end V IN The grid electrode is connected with a voltage input end VDD, and the source electrode is connected with the source electrode of the first MOS tube M1; drain electrode of fourth MOS tube M4 and current output end I OUT The source electrode is connected with the source electrode of the second MOS tube M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit.
Due to the loop control effect of M1 and M2, the output current of the circuit when r1=r2=r is:
wherein I is OUT Representing the output current of the voltage-to-current circuit, V IN The input voltage of the voltage-to-current circuit is represented, and R represents the resistance values of the first resistor R1 and the second resistor R2.
A logic circuit, as shown in fig. 4, comprising: 14 MOS tubes, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS tube M6; the source electrode of the sixth MOS tube M6 is connected with the drain electrode of the seventh MOS tube M7, and the grid electrode is respectively connected with the grid electrode of the eighth MOS tube M8, the grid electrode of the tenth MOS tube M10, the grid electrode of the eleventh MOS tube M11, the grid electrode of the fourteenth MOS tube M14 and the second capacitor C C And the drain electrode of the eighteenth MOS tube M18 is connected; the source electrode of the seventh MOS tube M7 is connected with the current output end I OUT The method comprises the steps of carrying out a first treatment on the surface of the One end of the third resistor R3 is connected with the voltage input end, and the other end is connected with the third resistorThe drain electrode of the eight MOS tube M8 is connected; the source electrode of the eighth MOS tube M8 is respectively connected with the grid electrode of the thirteenth MOS tube M13 and the drain electrode of the ninth MOS tube M9; the source electrode of the ninth MOS transistor M9 is connected with the current input end I IN The grid electrode is connected with the grid electrode of the seventh MOS tube M7 and then connected with the source electrode of the tenth MOS tube M10; the drain electrode of the tenth MOS tube M10 is connected with the voltage input end, and the grid electrode of the tenth MOS tube M11 is connected with the grid electrode; the source electrode of the eleventh MOS tube M11 is connected with the drain electrode of the twelfth MOS tube M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode is connected with the drain electrode of the seventh MOS tube M7; the source electrode of the fifteenth MOS tube M15 and the drain electrode of the sixteenth MOS tube M16 are respectively connected with the voltage input end, and the grid electrodes of the M15 and the M16 are respectively connected with the grid electrode of the nineteenth MOS tube M19 and the source electrode of the M15 after being connected with each other; the drain electrode of the fourteenth MOS tube M14 is respectively connected with the source electrode of the M15 and the second capacitor C C Is connected with one end of the second capacitor C C The source electrode is connected with the drain electrode of the thirteenth MOS tube M13; the grid electrode of the thirteenth MOS tube M13 is connected with the source electrode of the ninth MOS tube M9, the source electrode is connected with the fifth resistor R5, and the resistor R5 is grounded; sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source I BIAS4 The input end of the seventeenth MOS tube M17, the drain electrode of the seventeenth MOS tube M17 and the grid electrode of the seventeenth MOS tube M17 are connected; the grid of M17 is connected with the grid of an eighteenth MOS tube M18, the source of M17 and a fourth current source I BIAS4 The output end of which is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source I BIAS5 An output terminal of (a); i BIAS5 The input end of the voltage transformer is connected with the voltage input end; the drain electrode of the nineteenth MOS tube M19 is connected with the voltage input end, and the source electrodes are respectively connected with the voltage output end V INT And a sixth resistor R6, the other end of which is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end V INT A logic operation circuit is formed.
The mode discriminating circuit is used for discriminating the input voltage V in the BUCK-BOOST controller IN And output voltage V OU Enter different modes of operation; when V is OUT ＜V IN －V OS1 When the mode judging circuit outputs a low level, the BUCK-BOOST controller is in the BUCK mode; when V is IN －V OS1 ≤V OUT ≤V IN +V OS2 When the signal output by the mode distinguishing circuit is square wave signal, the duty ratio of the square wave signal is V OUT Increasing with increasing BUCK-BOOST controller in switching mode; when V is IN +V OS2 ≤V OUT When the mode judging circuit outputs a high level, the BUCK-BOOST controller is in the BUCK-BOOST mode; wherein V is OS1 、V OS2 Representing the offset voltage.
When V is OUT ＜V IN －V OS1 V at the time of D Less than V C Through M 13 Is 0, flows through M 15 And M 19 The current is 0, V INT ＝0。
When V is IN －V OS1 ≤V OUT ≤V IN +V OS2 At the same time, with the output voltage V OUT Increase, flow through M 13 、M 15 、M 19 The current of the logic operation circuit gradually increases, the output V of the logic operation circuit INT Gradually increasing.
When V is IN +V OS2 ≤V OUT In the process, the output voltage reaches the maximum value by the loop control action formed by M13, M15, M16, M17, M18 and M14, and V INT ＝(I BIAS5 +I BIAS4 ) R6, wherein I BIAS5 Indicating the current level of the fifth current source, I BIAS4 The current level of the fourth current source is represented, and R6 represents the resistance value of the sixth resistor.
Will V INT The signal is compared with the sawtooth wave signal to obtain a mode discrimination signal V MODE The duty cycle is:
when the input voltage is constant, VMODE outputs corresponding to different output voltages are shown in fig. 5.
The invention relates to a mode judging circuit applied to a BUCK-BOOST converter, which outputs a signal representing three states according to the relation of input and output voltages in the BUCK-BOOST converter, in particular, when V OUT ＜V IN －V OS1 At the time, the mode discrimination circuit outputsGo low indicating operation in BUCK mode; when V is IN －V OS1 ≤V OUT ≤V IN +V OS2 The mode discrimination circuit outputs a square wave signal with a duty ratio corresponding to V OUT An increase in (2) indicating operation in the switching mode; when V is IN +V OS2 ≤V OUT When the mode decision circuit outputs a high level, it indicates that the mode is operating in BUCK-BOOST mode. The mode judging circuit can be used for a multimode BUCK-BOOST controller chip, and can realize smooth switching between modes and maintain the stability of a loop and the constancy of output voltage.
While the foregoing is directed to embodiments, aspects and advantages of the present invention, other and further details of the invention may be had by the foregoing description, it will be understood that the foregoing embodiments are merely exemplary of the invention, and that any changes, substitutions, alterations, etc. which may be made herein without departing from the spirit and principles of the invention.

Claims (6)

1. A mode discrimination circuit for a BUCK-BOOST controller, comprising: the voltage-to-current circuit, the logic operation circuit, the sawtooth wave generation circuit and the comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive electrode input end of the comparator, and the sawtooth wave generating circuit is connected with the negative electrode input end of the comparator to form a mode distinguishing circuit;
the voltage-to-current circuit comprises two resistors, four MOS tubes and two current sources; first current source I BIAS1 One end of the first MOS tube M1 is connected with the voltage input end VDD, and the other end of the first MOS tube M1 is connected with the drain electrode of the fourth MOS tube M4; the grid electrode of the first MOS tube M1 is respectively connected with the grid electrode and the drain electrode of the second MOS tube M2, and the source electrode of the first MOS tube M1 is connected with the first resistor R1; second current source I BIAS2 One end of the second MOS tube M2 is connected with the voltage input end VDD; the source electrode of the second MOS tube M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with the voltage input end V IN Gate electrode connectionThe source electrode is connected with the source electrode of the first MOS tube M1; drain electrode of fourth MOS tube M4 and current output end I OUT The source electrode is connected with the source electrode of the second MOS tube M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit;
the logic operation circuit comprises 14 MOS tubes, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS tube M6; the source electrode of the sixth MOS tube M6 is connected with the drain electrode of the seventh MOS tube M7, and the grid electrode is respectively connected with the grid electrode of the eighth MOS tube M8, the grid electrode of the tenth MOS tube M10, the grid electrode of the eleventh MOS tube M11, the grid electrode of the fourteenth MOS tube M14 and the second capacitor C C And the drain electrode of the eighteenth MOS tube M18 is connected; the source electrode of the seventh MOS tube M7 is connected with the current output end I OUT The method comprises the steps of carrying out a first treatment on the surface of the One end of the third resistor R3 is connected with the voltage input end, and the other end of the third resistor R3 is connected with the drain electrode of the eighth MOS tube M8; the source electrode of the eighth MOS tube M8 is respectively connected with the grid electrode of the thirteenth MOS tube M13 and the drain electrode of the ninth MOS tube M9; the source electrode of the ninth MOS transistor M9 is connected with the current input end I IN The grid electrode is connected with the grid electrode of the seventh MOS tube M7 and then connected with the source electrode of the tenth MOS tube M10; the drain electrode of the tenth MOS tube M10 is connected with the voltage input end, and the grid electrode of the tenth MOS tube M11 is connected with the grid electrode; the source electrode of the eleventh MOS tube M11 is connected with the drain electrode of the twelfth MOS tube M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode is connected with the drain electrode of the seventh MOS tube M7; the source electrode of the fifteenth MOS tube M15 and the drain electrode of the sixteenth MOS tube M16 are respectively connected with the voltage input end, and the grid electrodes of the M15 and the M16 are respectively connected with the grid electrode of the nineteenth MOS tube M19 and the source electrode of the M15 after being connected with each other; the drain electrode of the fourteenth MOS tube M14 is respectively connected with the source electrode of the M15 and the second capacitor C C Is connected with one end of the second capacitor C C The source electrode is connected with the drain electrode of the thirteenth MOS tube M13; the grid electrode of the thirteenth MOS tube M13 is connected with the source electrode of the ninth MOS tube M9, the source electrode is connected with the fifth resistor R5, and the resistor R5 is grounded; sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source I BIAS4 The input end of the seventeenth MOS tube M17, the drain electrode of the seventeenth MOS tube M17 and the grid electrode of the seventeenth MOS tube M17 are connected; the grid of M17 is connected with the grid of an eighteenth MOS tube M18, the source of M17 and a fourth current source I BIAS4 The output end of which is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source I BIAS5 An output terminal of (a); i BIAS5 The input end of the voltage transformer is connected with the voltage input end; the drain electrode of the nineteenth MOS tube M19 is connected with the voltage input end, and the source electrodes are respectively connected with the voltage output end V INT And a sixth resistor R6, the other end of which is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end V INT A logic operation circuit is formed.
2. The mode decision circuit for a BUCK-BOOST controller according to claim 1, wherein the first resistor R1 and the second resistor R2 in the voltage-to-current circuit have equal resistance values.
3. The mode discrimination circuit for a BUCK-BOOST controller according to claim 1, wherein the mode discrimination circuit is responsive to an input voltage V in the BUCK-BOOST controller IN And output voltage V OUT Enter different modes of operation; when V is OUT ＜V IN －V OS1 When the mode judging circuit outputs a low level, the BUCK-BOOST controller is in the BUCK mode; when V is IN －V OS1 ≤V OUT ≤V IN +V OS2 When the mode judging circuit outputs a square wave signal, the BUCK-BOOST controller is in a switching mode; when V is IN +V OS2 ≤V OUT When the mode judging circuit outputs a high level, the BUCK-BOOST controller is in the BUCK-BOOST mode; wherein V is OUT Representing the output voltage, V IN Representing input voltage, V OS1 And V OS2 All represent offset voltages.
4. A mode discrimination circuit for a BUCK-BOOST controller according to claim 3, wherein V in the mode discrimination circuit OUT ＜V IN －V OS1 When the output voltage of the logic operation circuit is 0, i.e. V INT ＝0。
5. According to claim 3The mode distinguishing circuit for the BUCK-BOOST controller is characterized in that the mode distinguishing circuit V IN －V OS1 ≤V OUT ≤V IN +V OS2 At the time with V OUT Increase, flow through M 13 、M 15 、M 19 The current of the logic operation circuit gradually increases, and the output voltage V of the logic operation circuit INT Gradually increasing.
6. A mode discrimination circuit for a BUCK-BOOST controller according to claim 3, wherein V in the mode discrimination circuit IN +V OS2 ≤V OUT When the output voltage of the logic operation circuit is V INT ＝(I BIAS5 +I BIAS4 ) R6, wherein I BIAS5 Indicating the current level of the fifth current source, I BIAS4 The current level of the fourth current source is represented, and R6 represents the resistance value of the sixth resistor.
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