CN114244116A - Mode discrimination circuit for BUCK-BOOST controller - Google Patents

Mode discrimination circuit for BUCK-BOOST controller Download PDF

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CN114244116A
CN114244116A CN202111570446.4A CN202111570446A CN114244116A CN 114244116 A CN114244116 A CN 114244116A CN 202111570446 A CN202111570446 A CN 202111570446A CN 114244116 A CN114244116 A CN 114244116A
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mos transistor
circuit
voltage
buck
source
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CN114244116B (en
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廖鹏飞
雷旭
杨丰
李鹏
黄晓宗
王国强
霍改青
曾欣
刘婷
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CETC 24 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the field of power management circuits, and particularly relates to a mode discrimination circuit for a BUCK-BOOST controller, which comprises: the circuit comprises a voltage-to-current circuit, a logic operation circuit, a sawtooth wave generating circuit and a comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive input end of the comparator, and the sawtooth wave generating circuit is connected with the negative input end of the comparator to form a mode judging circuit; the invention designs a mode discrimination circuit applied to a BUCK-BOOST controller, which outputs a signal according to the relation between input voltage and output voltage in the BUCK-BOOST controller, and the signal can control a BUCK-BOOST controller chip to work in three different working states so as to realize smooth switching between modes and maintain the stability of a loop and the constancy of output voltage.

Description

Mode discrimination circuit for BUCK-BOOST controller
Technical Field
The invention belongs to the field of power management circuits, and particularly relates to a mode discrimination circuit for a BUCK-BOOST controller.
Background
A switching power supply is a power supply that maintains a stable output voltage, and is generally composed of a Pulse Width Modulation (PWM) control IC and a MOSFET. With the development and innovation of power electronic technology, the technology of the switching power supply is continuously innovated. At present, a switching power supply can be divided into a BUCK (BUCK) converter, a BOOST (BOOST) converter and a BOOST-BOOST (BUCK-BOOST) converter according to a relation between an input voltage and an output voltage, wherein the BUCK converter can only realize a BUCK function, and the BOOST converter can only realize a BOOST function; as shown in fig. 1, when an input voltage is much higher than an output voltage, VG2 can be turned off through logic control, the BUCK-BOOST converter is simplified into a BUCK controller, and only VG1 is in switching operation during operation, so that the loss of the circuit is reduced, and the conversion efficiency is improved; when the input voltage is close to the output voltage or the input voltage is lower than the output voltage, the circuit works in a BUCK-BOOST mode; therefore, the mode discrimination circuit is a key circuit in the multi-mode BUCK-BOOST controller; in the conventional mode discrimination circuit, the input voltage and the output voltage are directly compared by the comparator, and a signal is output, which represents two states of '0' and '1', and only two modes can be controlled, and for controlling other modes, a mode discrimination circuit capable of controlling multiple modes is urgently needed.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a mode discrimination circuit for a BUCK-BOOST controller, which comprises: the circuit comprises a voltage-to-current circuit, a logic operation circuit, a sawtooth wave generating circuit and a comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive input end of the comparator, and the sawtooth wave generating circuit is connected with the negative input end of the comparator to form a mode judging circuit.
Preferably, the voltage-to-current circuit comprises two resistors, four MOS transistors and two current sources; a first current source IBIAS1One end of the first MOS transistor is connected with a voltage input end VDD, and the other end of the first MOS transistor is respectively connected with the drain electrode of the first MOS transistor M1 and the grid electrode of the fourth MOS transistor M4; the grid electrode of the first MOS transistor M1 is respectively connected with the grid electrode and the drain electrode of the second MOS transistor M2, and the source electrode of the first MOS transistor M1 is connected with the first resistor R1; a second current source IBIAS2One end of the second MOS tube M2 is connected with a voltage input end VDD, and the other end of the second MOS tube M2 is connected with the drain electrode of the second MOS tube M2; the source electrode of the second MOS transistor M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with a voltage input end VINThe grid electrode is connected with a voltage input end VDD, and the source electrode is connected with the source electrode of the first MOS transistor M1; the drain of the fourth MOS transistor M4 and the current output terminal IOUTThe source electrode is connected with the source electrode of the second MOS transistor M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit.
Furthermore, the first resistor R1 and the second resistor R2 in the voltage-to-current circuit have the same resistance.
Preferably, the logic operation circuit comprises 14 MOS tubes, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS transistor M6; the source of the sixth MOS transistor M6 is connected to the drain of the seventh MOS transistor M7, and the gate is connected to the gate of the eighth MOS transistor M8, the gate of the tenth MOS transistor M10, the gate of the eleventh MOS transistor M11, the gate of the fourteenth MOS transistor M14, and the second capacitor C, respectivelyCAnd the drain electrode of the eighteenth MOS tube M18; the source electrode of the seventh MOS transistor M7 is connected with the current output end IOUT(ii) a One end of the third resistor R3 is connected with the voltage input end, and the other end is connected with the drain electrode of the eighth MOS transistor M8; the source electrode of the eighth MOS transistor M8 is connected to the gate electrode of the thirteenth MOS transistor M13 and the drain electrode of the ninth MOS transistor M9, respectively; the source electrode of the ninth MOS transistor M9 is connected with the current input end IINThe grid electrode of the seventh MOS tube M7 is connected with the grid electrode of the seventh MOS tube M10; drain of tenth MOS transistor M10The pole of the eleventh MOS transistor is connected with the voltage input end, and the grid of the eleventh MOS transistor is connected with the grid of the M11; the source electrode of the eleventh MOS transistor M11 is connected with the drain electrode of the twelfth MOS transistor M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode of the twelfth MOS tube M12 is connected with the drain electrode of the seventh MOS tube M7; the source of the fifteenth MOS transistor M15 and the drain of the sixteenth MOS transistor M16 are respectively connected to the voltage input terminal, and the gates of M15 and M16 are connected to each other and then respectively connected to the gate of the nineteenth MOS transistor M19 and the source of M15; the drain of the fourteenth MOS transistor M14 is respectively connected with the source of M15 and the second capacitor CCIs connected with the gate of the second capacitor CCThe source electrode of the other end of the third MOS transistor is connected with the drain electrode of a thirteenth MOS transistor M13; the gate of the thirteenth MOS transistor M13 is connected to the source of the ninth MOS transistor M9, the source is connected to the fifth resistor R5, and the resistor R5 is grounded; the sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source IBIAS4The input end of the seventeenth MOS transistor M17, the drain electrode of the seventeenth MOS transistor M17 and the gate electrode of the M17 are connected; the gate of M17 is connected to the gate of M18, the source of M17 and the fourth current source IBIAS4The output end of the transformer is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source IBIAS5An output terminal of (a); i isBIAS5The input end of the voltage-stabilizing circuit is connected with a voltage input end; the drain electrode of the nineteenth MOS transistor M19 is connected with the voltage input end, and the source electrodes are respectively connected with the voltage output end VINTA sixth resistor R6, the other end of the sixth resistor is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end VINTA logical operation circuit is constructed.
Preferably, the mode discrimination circuit is based on the input voltage V in the BUCK-BOOST controllerINAnd an output voltage VOUTThe relation of (2) enters different working modes; when V isOUT＜VIN－VOS1When the mode judging circuit outputs a low level, the BUCK-BOOST controller is in a BUCK mode; when V isIN－VOS1≤VOUT≤VIN+VOS2The signal output by the mode discrimination circuit is a square wave signal, and the duty ratio of the square wave signal is VOUTIs increased, the BUCK-BOOST controller is in switching mode; when V isIN+VOS2≤VOUTWhen the mode discrimination circuit outputs a high level, the BUCK-BOOST controller is at BUCK-BOOST mode; wherein, VOS1And VOS2Both represent offset voltages.
Further, V in the mode discrimination circuitOUT＜VIN－VOS1The output voltage of the logic operation circuit is 0, i.e. VINT＝0。
Further, a mode discrimination circuit VIN－VOS1≤VOUT≤VIN+VOS2When following VOUTIncrease, flow through M13、M15、M19The current of the logic operation circuit is gradually increased, and the output voltage V of the logic operation circuit is gradually increasedINTGradually increasing.
Further, V in the mode discrimination circuitIN+VOS2≤VOUTThe output voltage of the logic operation circuit is VINT＝(IBIAS5+IBIAS4) R6, wherein IBIAS5Represents the current magnitude of the fifth current source, IBIAS4Indicating the magnitude of the current of the fourth current source and R6 indicating the resistance of the sixth resistor.
The invention designs a mode discrimination circuit applied to a BUCK-BOOST controller, which outputs a mode discrimination signal according to the relation between input voltage and output voltage in the BUCK-BOOST controller, wherein the duty ratio of the signal represents three states, and the circuit can be used for a multi-mode BUCK-BOOST controller chip, can realize smooth switching between the modes and maintain the stability of a loop and the constancy of the output voltage.
Drawings
FIG. 1 is a schematic diagram of a conventional BUCK-BOOST converter topology;
FIG. 2 is a schematic diagram of a mode discrimination circuit for the BUCK-BOOST controller according to the present invention;
FIG. 3 is a circuit diagram of the voltage to current converter of the present invention;
FIG. 4 is a circuit diagram of the logic operation of the present invention;
FIG. 5 is a diagram of the output voltage of the mode decision circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A BUCK-BOOST converter topology, as shown in fig. 1, the circuit is: an input voltage source VIN, a MOS tube M20, a first diode D1, an inductor L, MOS, a tube M21, a second diode D2, a capacitor C and a resistor RL; the positive electrode of an input voltage source VIN is connected with the drain electrode of the MOS transistor M20, and the negative electrode is grounded; the gate of the MOS transistor M20 is connected to the first voltage input terminal VG1, and the source is connected to the cathode of the first diode D1 and the inductor L, respectively; the anode of the first diode D1 is grounded; the other end of the inductor L is respectively connected with the anode of the second diode D2 and the drain of the MOS transistor M21; the grid electrode of the MOS transistor M21 is connected with a second voltage input end VG2, and the source electrode is grounded; the cathode of the second diode D2 is respectively connected with the capacitor C, the resistor RL and the voltage output end VOUT; the other ends of the capacitor C and the resistor RL are grounded, and a BUCK-BOOST converter topological structure is formed.
When the BUCK-BOOST converter is adopted, when the on duty ratio of the first voltage input terminal VG1 and the second voltage input terminal VG2 is D, the output voltage of the converter is:
Figure BDA0003423195710000041
wherein, VOUTRepresenting the output voltage of the BUCK-BOOST converter, D representing the on-duty cycle of the first voltage input VG1 and the second voltage input VG2, VINRepresenting the voltage of the input voltage source VIN.
The duty ratio D is adjusted according to the output voltage formula of the converter, and the output voltage which is larger than (smaller than or equal to) the input voltage can be obtained. Therefore, the constant output voltage can be maintained in a wide input voltage range, and the constant output voltage can be widely applied to occasions such as automobile electronics, industrial power supply and the like.
When the input voltage is far higher than the output voltage, VG2 can be turned off through logic control, at the time, the BUCK-BOOST converter is simplified into a BUCK controller, and only VG1 is in switching action during working, so that loss is caused, and conversion efficiency is improved. When the input voltage is close to the output voltage or the input voltage is lower than the output voltage, the circuit works in the BUCK-BOOST mode.
A mode discrimination circuit for use in a BUCK-BOOST controller, as shown in fig. 2, the circuit comprising: the circuit comprises a voltage-to-current circuit, a logic operation circuit, a sawtooth wave generating circuit and a comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive input end of the comparator, and the sawtooth wave generating circuit is connected with the negative input end of the comparator to form a mode judging circuit.
A voltage-to-current circuit, as shown in fig. 3, comprising: the circuit comprises two resistors, four MOS (metal oxide semiconductor) tubes and two current sources; a first current source IBIAS1One end of the first MOS transistor is connected with a voltage input end VDD, and the other end of the first MOS transistor is respectively connected with the drain electrode of the first MOS transistor M1 and the grid electrode of the fourth MOS transistor M4; the grid electrode of the first MOS transistor M1 is respectively connected with the grid electrode and the drain electrode of the second MOS transistor M2, and the source electrode of the first MOS transistor M1 is connected with the first resistor R1; a second current source IBIAS2One end of the second MOS tube M2 is connected with a voltage input end VDD, and the other end of the second MOS tube M2 is connected with the drain electrode of the second MOS tube M2; the source electrode of the second MOS transistor M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with a voltage input end VINThe grid electrode is connected with a voltage input end VDD, and the source electrode is connected with the source electrode of the first MOS transistor M1; the drain of the fourth MOS transistor M4 and the current output terminal IOUTThe source electrode is connected with the source electrode of the second MOS transistor M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit.
Due to the control effect of the loop formed by M1 and M2, the output current of the circuit when R1 equals R2 equals R is:
Figure BDA0003423195710000051
wherein, IOUTIndicating the output current, V, of a voltage-to-current circuitINRepresenting the input voltage of the voltage-to-current circuit, R representing the first resistorR1 and a second resistor R2.
A logic operation circuit, as shown in fig. 4, the circuit comprising: 14 MOS tubes, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS transistor M6; the source of the sixth MOS transistor M6 is connected to the drain of the seventh MOS transistor M7, and the gate is connected to the gate of the eighth MOS transistor M8, the gate of the tenth MOS transistor M10, the gate of the eleventh MOS transistor M11, the gate of the fourteenth MOS transistor M14, and the second capacitor C, respectivelyCAnd the drain electrode of the eighteenth MOS tube M18; the source electrode of the seventh MOS transistor M7 is connected with the current output end IOUT(ii) a One end of the third resistor R3 is connected with the voltage input end, and the other end is connected with the drain electrode of the eighth MOS transistor M8; the source electrode of the eighth MOS transistor M8 is connected to the gate electrode of the thirteenth MOS transistor M13 and the drain electrode of the ninth MOS transistor M9, respectively; the source electrode of the ninth MOS transistor M9 is connected with the current input end IINThe grid electrode of the seventh MOS tube M7 is connected with the grid electrode of the seventh MOS tube M10; the drain electrode of the tenth MOS tube M10 is connected with the voltage input end, and the gate electrode of the tenth MOS tube M10 is connected with the gate electrode of the eleventh MOS tube M11; the source electrode of the eleventh MOS transistor M11 is connected with the drain electrode of the twelfth MOS transistor M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode of the twelfth MOS tube M12 is connected with the drain electrode of the seventh MOS tube M7; the source of the fifteenth MOS transistor M15 and the drain of the sixteenth MOS transistor M16 are respectively connected to the voltage input terminal, and the gates of M15 and M16 are connected to each other and then respectively connected to the gate of the nineteenth MOS transistor M19 and the source of M15; the drain of the fourteenth MOS transistor M14 is respectively connected with the source of M15 and the second capacitor CCIs connected with the gate of the second capacitor CCThe source electrode of the other end of the third MOS transistor is connected with the drain electrode of a thirteenth MOS transistor M13; the gate of the thirteenth MOS transistor M13 is connected to the source of the ninth MOS transistor M9, the source is connected to the fifth resistor R5, and the resistor R5 is grounded; the sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source IBIAS4The input end of the seventeenth MOS transistor M17, the drain electrode of the seventeenth MOS transistor M17 and the gate electrode of the M17 are connected; the gate of M17 is connected to the gate of M18, the source of M17 and the fourth current source IBIAS4The output end of the transformer is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source IBIAS5An output terminal of (a); i isBIAS5The input end of the voltage-stabilizing circuit is connected with a voltage input end; tenth itemThe drain electrode of the nine MOS tube M19 is connected with the voltage input end, and the source electrode is respectively connected with the voltage output end VINTA sixth resistor R6, the other end of the sixth resistor is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end VINTA logical operation circuit is constructed.
The mode discrimination circuit is used for discriminating the mode according to the input voltage V in the BUCK-BOOST controllerINAnd an output voltage VOUThe relation of (2) enters different working modes; when V isOUT＜VIN－VOS1When the mode judging circuit outputs a low level, the BUCK-BOOST controller is in a BUCK mode; when V isIN－VOS1≤VOUT≤VIN+VOS2The signal output by the mode discrimination circuit is a square wave signal, and the duty ratio of the square wave signal is VOUTIs increased, the BUCK-BOOST controller is in switching mode; when V isIN+VOS2≤VOUTWhen the mode judging circuit outputs a high level, the BUCK-BOOST controller is in a BUCK-BOOST mode; wherein, VOS1、VOS2Representing the offset voltage.
When V isOUT＜VIN－VOS1When, VDLess than VCThrough M13Current of (1) is 0, flows through M15And M19Current of 0, VINT＝0。
When V isIN－VOS1≤VOUT≤VIN+VOS2While following the output voltage VOUTIncrease, flow through M13、M15、M19Is gradually increased, the output V of the logic operation circuitINTGradually increasing.
When V isIN+VOS2≤VOUTWhen the voltage reaches the maximum value, the output voltage reaches the maximum value under the control action of a loop consisting of M13, M15, M16, M17, M18 and M14, and at the moment, V is controlled to be zeroINT＝(IBIAS5+IBIAS4) R6, wherein IBIAS5Represents the current magnitude of the fifth current source, IBIAS4Indicating the magnitude of the current of the fourth current source and R6 indicating the resistance of the sixth resistor.
Will VINTComparing the signal with a sawtooth wave signal to obtain a patternDiscrimination signal VMODEThe duty cycle is:
Figure BDA0003423195710000071
when the input voltage is constant, the VMODE output for different output voltages is shown in fig. 5.
The invention relates to a mode discrimination circuit applied to a BUCK-BOOST converter, which outputs a signal representing three states according to the relation of input and output voltages in the BUCK-BOOST converter, in particular, when V isOUT＜VIN－VOS1When the mode judging circuit outputs a low level, the mode judging circuit works in a BUCK mode; when V isIN－VOS1≤VOUT≤VIN+VOS2The output of the mode discrimination circuit is a square wave signal, and the duty ratio of the square wave signal follows VOUTIs increased, indicating operation in the switching mode; when V isIN+VOS2≤VOUTWhen the mode judging circuit outputs a high level, the mode judging circuit is indicated to work in the BUCK-BOOST mode. The mode discrimination circuit can be used for a multi-mode BUCK-BOOST controller chip, can realize smooth switching between modes, and maintains the stability of a loop and the constancy of output voltage.
The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention, should be understood that the above-mentioned embodiments are only preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A mode discrimination circuit for a BUCK-BOOST controller, comprising: the circuit comprises a voltage-to-current circuit, a logic operation circuit, a sawtooth wave generating circuit and a comparator; the output end of the voltage-to-current circuit is connected with the input end of the logic operation circuit, the output end of the logic operation circuit is connected with the positive input end of the comparator, and the sawtooth wave generating circuit is connected with the negative input end of the comparator to form a mode judging circuit.
2. The mode discrimination circuit for the BUCK-BOOST controller as claimed in claim 1, wherein the voltage-to-current circuit comprises two resistors, four MOS transistors and two current sources; a first current source IBIAS1One end of the first MOS transistor is connected with a voltage input end VDD, and the other end of the first MOS transistor is respectively connected with the drain electrode of the first MOS transistor M1 and the grid electrode of the fourth MOS transistor M4; the grid electrode of the first MOS transistor M1 is respectively connected with the grid electrode and the drain electrode of the second MOS transistor M2, and the source electrode of the first MOS transistor M1 is connected with the first resistor R1; a second current source IBIAS2One end of the second MOS tube M2 is connected with a voltage input end VDD, and the other end of the second MOS tube M2 is connected with the drain electrode of the second MOS tube M2; the source electrode of the second MOS transistor M2 is connected with a second resistor R2; the drain electrode of the third MOS tube is connected with a voltage input end VINThe grid electrode is connected with a voltage input end VDD, and the source electrode is connected with the source electrode of the first MOS transistor M1; the drain of the fourth MOS transistor M4 and the current output terminal IOUTThe source electrode is connected with the source electrode of the second MOS transistor M2; the other ends of the first resistor R1 and the second resistor R2 are grounded to form a voltage-to-current circuit.
3. The mode decision circuit of claim 2, wherein the first resistor R1 and the second resistor R2 in the voltage-to-current circuit have the same resistance.
4. The mode discrimination circuit for the BUCK-BOOST controller as claimed in claim 1, wherein the logic operation circuit comprises 14 MOS transistors, 4 resistors, 3 current sources and 2 capacitors; one end of the fourth resistor R4 is connected with the voltage input end, and the other end of the fourth resistor R4 is connected with the drain electrode of the sixth MOS transistor M6; the source of the sixth MOS transistor M6 is connected to the drain of the seventh MOS transistor M7, and the gate is connected to the gate of the eighth MOS transistor M8, the gate of the tenth MOS transistor M10, the gate of the eleventh MOS transistor M11, the gate of the fourteenth MOS transistor M14, and the second capacitor C, respectivelyCAnd the drain electrode of the eighteenth MOS tube M18; the source electrode of the seventh MOS transistor M7 is connected with the current output end IOUT(ii) a One end of the third resistor R3 is connected with the voltage input end, and the other end is connected with the voltage input endThe end of the second MOS tube is connected with the drain electrode of the eighth MOS tube M8; the source electrode of the eighth MOS transistor M8 is connected to the gate electrode of the thirteenth MOS transistor M13 and the drain electrode of the ninth MOS transistor M9, respectively; the source electrode of the ninth MOS transistor M9 is connected with the current input end IINThe grid electrode of the seventh MOS tube M7 is connected with the grid electrode of the seventh MOS tube M10; the drain electrode of the tenth MOS tube M10 is connected with the voltage input end, and the gate electrode of the tenth MOS tube M10 is connected with the gate electrode of the eleventh MOS tube M11; the source electrode of the eleventh MOS transistor M11 is connected with the drain electrode of the twelfth MOS transistor M12; the source electrode of the twelfth MOS tube M12 is connected with the fifth resistor R5, and the grid electrode of the twelfth MOS tube M12 is connected with the drain electrode of the seventh MOS tube M7; the source of the fifteenth MOS transistor M15 and the drain of the sixteenth MOS transistor M16 are respectively connected to the voltage input terminal, and the gates of M15 and M16 are connected to each other and then respectively connected to the gate of the nineteenth MOS transistor M19 and the source of M15; the drain of the fourteenth MOS transistor M14 is respectively connected with the source of M15 and the second capacitor CCIs connected with the gate of the second capacitor CCThe source electrode of the other end of the third MOS transistor is connected with the drain electrode of a thirteenth MOS transistor M13; the gate of the thirteenth MOS transistor M13 is connected to the source of the ninth MOS transistor M9, the source is connected to the fifth resistor R5, and the resistor R5 is grounded; the sources of the sixteenth MOS transistor M16 are respectively connected with a fourth current source IBIAS4The input end of the seventeenth MOS transistor M17, the drain electrode of the seventeenth MOS transistor M17 and the gate electrode of the M17 are connected; the gate of M17 is connected to the gate of M18, the source of M17 and the fourth current source IBIAS4The output end of the transformer is grounded; the source electrode of the eighteenth MOS tube M18 is grounded, and the drain electrode is connected with a fifth current source IBIAS5An output terminal of (a); i isBIAS5The input end of the voltage-stabilizing circuit is connected with a voltage input end; the drain electrode of the nineteenth MOS transistor M19 is connected with the voltage input end, and the source electrodes are respectively connected with the voltage output end VINTA sixth resistor R6, the other end of the sixth resistor is grounded; one end of the first capacitor C1 is grounded, and the other end is connected with the voltage output end VINTA logical operation circuit is constructed.
5. The mode decision circuit for BUCK-BOOST controller as claimed in claim 1, wherein the mode decision circuit is based on the input voltage V in the BUCK-BOOST controllerINAnd an output voltage VOUTThe relation of (2) enters different working modes; when V isOUT＜VIN－VOS1When the temperature of the water is higher than the set temperature,the mode discrimination circuit outputs a low level, and the BUCK-BOOST controller is in a BUCK mode; when V isIN－VOS1≤VOUT≤VIN+VOS2When the switching circuit is in the switching mode, the mode judging circuit outputs a square wave signal, and the BUCK-BOOST controller is in the switching mode; when V isIN+VOS2≤VOUTWhen the mode judging circuit outputs a high level, the BUCK-BOOST controller is in a BUCK-BOOST mode; wherein, VOUTRepresenting the output voltage, VINRepresenting the input voltage, VOS1And VOS2Both represent offset voltages.
6. The BUCK-BOOST controller as recited in claim 5, wherein V is in the mode discrimination circuitOUT＜VIN－VOS1The output voltage of the logic operation circuit is 0, i.e. VINT＝0。
7. The BUCK-BOOST controller as claimed in claim 5, wherein the mode discrimination circuit V is configured to discriminate between the BUCK and the BOOST controllerIN－VOS1≤VOUT≤VIN+VOS2When following VOUTIncrease, flow through M13、M15、M19The current of the logic operation circuit is gradually increased, and the output voltage V of the logic operation circuit is gradually increasedINTGradually increasing.
8. The BUCK-BOOST controller as recited in claim 5, wherein V is in the mode discrimination circuitIN+VOS2≤VOUTThe output voltage of the logic operation circuit is VINT＝(IBIAS5+I BIAS4) R6, wherein IBIAS5Represents the current magnitude of the fifth current source, IBIAS4Indicating the magnitude of the current of the fourth current source and R6 indicating the resistance of the sixth resistor.
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