CN114244103B

CN114244103B - Charge pump control circuit and method

Info

Publication number: CN114244103B
Application number: CN202111579286.XA
Authority: CN
Inventors: 刘志国; 徐春华
Original assignee: Beijing Dashun Technology Co ltd
Current assignee: Beijing Dashun Technology Co ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2023-03-24
Anticipated expiration: 2041-12-22
Also published as: CN114244103A

Abstract

Embodiments of the present disclosure relate to charge pump control circuits and methods. The control circuit includes: a comparison output circuit configured to compare and logically operate an output voltage of the charge pump with a threshold voltage to generate a DCM signal and a DCMTON signal, the comparison output circuit coupled with the charge pump; and a driving clock signal generation circuit configured to synchronize and logically operate the DCM signal and the DCMTON signal with a system clock signal to generate a driving clock signal, and control a current output of the charge pump by the driving clock signal, the driving clock signal generation circuit being coupled with the comparison output circuit and the charge pump, respectively. The present disclosure reduces the switching losses of the charge pump in case of light loads and the transition between DCM and CCM operation modes is natural.

Description

Charge pump control circuit and method

Technical Field

The disclosure relates to the technical field of charge pumps, in particular to a charge pump control circuit and a charge pump control method.

Background

For the field of voltage converters providing buck or boost functions in charge pump architectures, the power switching tubes in the charge pumps cause switching losses when in operation. For such voltage converters, how to reduce energy loss and improve conversion efficiency when energy is transmitted from an input end to an output end to supply power to a corresponding system is always the most central problem. The switching loss is related to the switching frequency of the switching tube, and when the charge pump works in a situation that the output load is light, the switching loss is dominant in the whole energy loss. If the power switch tube of the charge pump is continuously switched on and off, energy loss is increased, the efficiency of the whole system is reduced, and the service time of a battery used as the power supply input of the system is influenced.

Disclosure of Invention

A charge pump control circuit and method are provided, which can effectively reduce the switching loss of a charge pump under the condition of light load.

According to a first aspect of the present disclosure, there is provided a charge pump control circuit comprising: a comparison output circuit configured to compare and logically operate an output voltage of the charge pump with a threshold voltage to generate a DCM signal and a DCMTON signal, the comparison output circuit coupled with the charge pump; and a driving clock signal generating circuit configured to synchronize and logically operate the DCM signal and the DCMTON signal with a system clock signal to generate a driving clock signal for controlling a current output of the charge pump, the driving clock signal generating circuit being coupled with the comparison output circuit and the charge pump, respectively.

According to a second aspect of the present disclosure, there is provided a charge pump control method comprising: comparing the output voltage of the charge pump with a threshold voltage and carrying out logical operation to generate a DCM signal and a DCMTON signal; synchronizing and logically operating the DCM signal and the DCMTON signal with a system clock signal to generate a driving clock signal; and controlling the current output of the charge pump by driving the clock signal.

The beneficial effects of this disclosure include: the charge pump control circuit and the method for realizing a DCM (Discontinuous connection Mode) working Mode are provided, in the DCM Mode, only when the system output needs energy, and when the output voltage drops to a set threshold value, the current output of the charge pump is started to provide the energy, and at other times, the charge pump does not output the current, thereby achieving the purposes of saving the switching loss and improving the efficiency. And as the load becomes heavier further, the charge pump can be naturally switched to a CCM (Continuous communication Mode) working Mode from a DCM working Mode, so that the output voltage is kept stable, and the system is not influenced.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements.

Fig. 1 shows a block diagram of an example charge pump control circuit 100, according to an embodiment of the present disclosure.

Fig. 2 shows a timing diagram of related signals in an example charge pump control circuit according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of an exemplary DCM comparison output circuit 300, according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of an exemplary DCMTON comparison output circuit 400, according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of an exemplary drive clock signal generation circuit 500, in accordance with an embodiment of the present disclosure.

Fig. 6 shows a timing diagram of related signals in an exemplary drive clock signal generation circuit according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of an exemplary over-current protection circuit 700, in accordance with an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of an example charge pump 800 in accordance with an embodiment of the present disclosure.

Fig. 9 shows a flow chart of an example charge pump control method according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same samples. Other explicit and implicit definitions are also possible below.

As described above, the power switching tube in the charge pump causes switching loss when operating. The switching loss is related to the switching frequency of the switching tube, and when the charge pump works in an occasion with a light output load, if the power switching tube of the charge pump is continuously switched on and off, the energy loss is increased, the overall efficiency of the system is reduced, and the service life of a battery used as the input of a system power supply is influenced.

To address, at least in part, one or more of the above issues and other potential issues, an exemplary embodiment of the present disclosure proposes a solution for charge pump control. In this scheme, a DCM (Discontinuous connection Mode) operation Mode is realized by a control circuit and method of the charge pump. DCM mode of operation is discontinuous conduction mode of operation. In the working mode, the output voltage is compared with the corresponding threshold value to judge the system load, and then the current output of the charge pump is controlled to be started or stopped, namely the charge pump is not continuously conducted, so that the switching loss can be reduced.

The DCM operation Mode of the charge pump corresponds to a CCM (Continuous Conduction Mode) operation Mode, i.e., a Continuous Conduction Mode. When the output voltage drops below a certain threshold, the load of the system is large, and the continuous output of the charge pump is needed. At which point the charge pump is controlled to exit DCM and enter CCM mode. In this mode of operation, the charge pump receives a continuous fixed switching pulse to continue outputting current. The scheme can realize the conversion between the DCM mode and the CCM mode, and the conversion is natural.

The charge pump DCM mode of operation is controlled by the DCM signal and the DCMTON signal. Referring to fig. 2, the dcm signal includes a high level signal and a low level signal for a certain clock period. The high level DCM signal controls the charge pump in the DCM operation mode, and the low level DCM signal controls the charge pump in the CCM operation mode. During the DCM operation mode, the DCMTON signal controls the start and stop of the charge pump. When the DCMTON signal is in a high level, the switch tube in the charge pump is continuously switched to output current, and when the DCMTON signal is in a low level, the switch tube in the charge pump stops switching to stop outputting current.

During the period that the charge pump is in the DCM operation mode, the output voltage is compared with a certain threshold value to judge whether the system load is suddenly increased to require the charge pump to exit the DCM operation mode. In the event that the charge pump is required to exit the DCM mode of operation and enter the CCM mode of operation, the present disclosure generates a low level DCM signal to control the charge pump to continue outputting current.

The present disclosure solves the problem of switching loss in the case of a light load by comparing the output voltage of the charge pump with a corresponding threshold value to make a load judgment and generating a corresponding pulse control signal to control the current output of the charge pump, and can naturally transition to a CCM operation mode in the case of a load becoming large.

Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings. For ease of understanding, specific data mentioned in the following description are exemplary and are not intended to limit the scope of the present disclosure.

Fig. 1 shows an example charge pump control circuit 100 schematic in accordance with an embodiment of the present disclosure. As shown in fig. 1, the charge pump control circuit 100 includes a comparison output circuit 106 and a drive clock signal generation circuit 104. The comparison output circuit 106 is coupled to the output of the charge pump 102 to obtain the output voltage of the charge pump 102. The comparison output circuit 106 compares the obtained output voltage with a configurable threshold voltage and performs correlation logic operations to generate the DCM signal and the DCMTON signal as shown in fig. 6.

The driving clock signal generation circuit 104 is coupled to the comparison output circuit 106 and the control terminal of the charge pump 102, respectively. The driving clock signal generating circuit 104 first receives the DCM signal and the DCMTON signal generated by the comparison output circuit 106, and then synchronizes and performs a correlation logic operation on the DCM signal and the DCMTON signal with the system clock signal to generate the driving clock signal driver _ clock and the inversion signal driver _ clock kb as shown in fig. 6. The driving clock signal driver _ clock and the inverted signal driver _ clock are coupled and sent to the charge pump 102 to control the charge pump 102 output current.

In some embodiments, the comparison output circuit includes a DCM comparison output circuit and a DCMTON comparison output circuit.

Fig. 3 shows a schematic diagram of an exemplary DCM comparison output circuit, according to an embodiment of the present disclosure. As shown in fig. 3, DCM comparison output circuit 300 includes a first input circuit 302, a DCM comparison circuit 304, and a first output circuit 306. First input circuit 302 is coupled to DCM comparator circuit 304, and DCM comparator circuit 304 is coupled to first output circuit 306.

In some embodiments, DCM comparison circuit 304 includes a comparator 314 and first output circuit 306 includes a delay filter 316 and an inverter 320.

In some embodiments, comparator 314 is a high precision comparator.

In some embodiments, the first input circuit 302 receives the output voltage 312 of the charge pump and a threshold voltage.

In some embodiments, the threshold voltage includes at least a first threshold 322 and a second threshold 308. The first threshold 322 is determined based on the input voltage of the charge pump and the preconfigured DCM voltage; the second threshold 308 is determined based on the input voltage of the charge pump, the preconfigured DCM voltage, and the preconfigured second hysteresis voltage.

In some embodiments, first threshold value 322 is 1/2VIN-Vdcm and second threshold value 308 is 1/2VIN-Vdcm-Vhys2. Where VIN is the input voltage of the charge pump, vdcm is the configurable DCM voltage, and Vhys2 is the configurable second hysteresis voltage.

In some embodiments, the DCM voltage is 30 mV and the second hysteresis voltage is 10 mV.

In some embodiments, the first input circuit 302 includes SPST switches 310 and 324. First, 324 is closed and 310 is opened to transmit the first threshold 322 output voltage sample 312 to the comparator 314. The comparator 314 compares the output voltage sample 312 with a first threshold 322, and when the output voltage sample 312 is higher than the first threshold 322, it indicates that the system is in a light load state, and the DCM operation mode can be entered. The comparator 314 outputs the first comparison signal at a high level at this time. To remove the glitch in the first comparison signal, the delay filter 316 delay filters the first comparison signal to generate a high level DCM signal 318 to place the charge pump in DCM operation mode.

During operation of the charge pump in DCM, the output voltage 312 needs to be compared with the second threshold 308 in order to monitor that the system load suddenly becomes large and needs to exit DCM. To switch the input threshold of the comparator 314, the high level DCM signal 318 is passed to the SPST switch 310 to close, the high level DCM signal 318 is converted to a low level signal through the inverter 320 and passed to the SPST switch 324 to open to switch the threshold passed to the comparator 314 to the second threshold 308.

The comparator 314 compares the output voltage 312 with the second threshold 308, and when the output voltage 312 is less than the second threshold 308, it indicates that the system is in a heavy load state, and it is necessary to exit the DCM mode and enter the CCM operation mode. At this time, the comparator 314 outputs the second comparison signal of low level. To remove the interference signal in the second comparison signal, delay filter 316 delay filters the second comparison signal to generate a low level DCM signal 318.

Referring to FIG. 2, when the output voltage VOUT is above the threshold 1/2VIN-Vdcm and not below the threshold 1/2VIN-Vdcm-Vhys2, the DCM signal is a high level signal, such that the voltage signal CPx of the charge pump will appear as a discontinuous pulse signal in the DCM operating mode.

Referring to fig. 2, when the output voltage VOUT is lower than the threshold value 1/2VIN-Vdcm-Vhys2, DCM is a low level signal, so that the charge pump is in CCM operation mode, the voltage signal CPx of the charge pump will appear as a fixed continuous pulse signal, and the output current IOUT of the charge pump continues to increase.

Fig. 4 shows a schematic diagram of an exemplary DCMTON comparison output circuit, according to an embodiment of the disclosure. In fig. 4, the DCMTON comparison output circuit 400 includes a second input circuit 402, a DCMTON comparison circuit 404, and a second output circuit 406. The second input circuit 402 is coupled to a DCMTON comparison circuit 404, and the DCMTON comparison circuit 404 is coupled to a second output circuit 406.

In some embodiments, the DCMTON comparison circuit 404 includes a comparator 412 and the second output circuit 406 includes an and gate 414 and an inverter 416.

In some embodiments, comparator 412 is a high precision comparator and has a fast response speed.

In some embodiments, the second input circuit 402 receives the output voltage 424 of the charge pump and a threshold voltage.

In some embodiments, the threshold voltage includes at least a third threshold 420 and a fourth threshold 408.

In some embodiments, the third threshold 420 is determined based on the input voltage of the charge pump and the preconfigured droop voltage, and the fourth threshold 408 is determined based on the input voltage of the charge pump, the preconfigured droop voltage, and the preconfigured first hysteresis voltage.

In some embodiments, the third threshold value 420 is 1/2VIN-Vdrop and the fourth threshold value 408 is 1/2VIN-Vdrop + Vhys1. Where VIN is the input voltage of the charge pump, vdrop is a configurable drop voltage, and Vhys1 is a configurable first hysteresis voltage.

In some embodiments, the Vdrop voltage is 20-30 millivolts and Vhys1 is 10 millivolts.

In some embodiments, the second input circuit 402 includes SPST switches 410 and 422. First 422 is closed and 410 is opened to transmit the third threshold 420 and the output voltage 424 to the comparator 412. The comparator 412 compares the output voltage 424 with a third threshold 420. When the output voltage 424 is below the third threshold 420, it indicates that the system requires the charge pump output current to meet the load demand, and therefore the current output of the charge pump needs to be enabled. At this time, the comparator 412 outputs the third comparison signal of high level. The third comparison signal is logically anded with DCM signal 426 via and gate 414 in second output circuit 406 to generate the high level DCMTON signal.

To monitor the change in system load to stop the current output of the charge pump accordingly, the output voltage 424 needs to be compared to the fourth threshold 408. To switch the input threshold of the comparator 412, the high level DCMTON signal is transmitted to 410 to be closed, the high level DCM signal is passed through the inverter 416 to be converted to a low level signal and is transmitted to 422 to be opened, so that the threshold transmitted to the comparator 412 is converted to the fourth threshold 408.

The second input circuit 402 transmits the fourth threshold 408 and the output voltage 424 to the comparator 412. The comparator 412 compares the output voltage 424 to the fourth threshold 408. When the output voltage 424 is higher than the fourth threshold 408, it indicates that the charge pump in the DCM operation mode may stop the current output. At this time, the comparator 412 outputs the fourth comparison signal of low level. The fourth comparison signal is logically anded with DCM signal 426 via and gate 414 in output circuit 406 to generate the low level DCMTON signal.

Referring to fig. 2, during a high clock period of the DCM signal, when the output voltage VOUT is lower than the threshold 1/2VIN-Vdrop, the DCMTON signal starts to be generated at a high level to cause the charge pump to start outputting current, thereby causing VOUT to rise. When the output voltage VOUT is higher than the threshold value 1/2VIN-Vdrop + Vhys1, the DCMTON signal of low level is started to be generated so that the charge pump stops current output. The output current IOUT is stably output by keeping the output voltage VOUT within a certain interval.

Fig. 5 shows a schematic diagram of an exemplary drive clock signal generation circuit 500, in accordance with an embodiment of the present disclosure. As shown in fig. 5, the driving clock signal generating circuit 500 includes a third input circuit 502, a clock synchronizing circuit 504, and a third output circuit 506. The third input circuit 502 is coupled to a clock synchronization circuit 504. The clock synchronization circuit 504 is coupled to a third output circuit 506.

In some embodiments, the clock synchronization circuit 504 is comprised of a first D flip-flop 514 and a second D flip-flop 538 and an or gate 518, and the third output circuit 506 is comprised of an and gate 520 and an inverter 532.

In some embodiments, the third input circuit 502 includes an inverter 524. The system clock signal 508, the DCMTON signal 510, and the DCM signal 512 are input to a first D flip-flop 514. The first D flip-flop 514 generates a rising edge synchronization signal 516 for synchronizing the DCMTON signal 510 at the rising edge of the system clock signal 508.

In some embodiments, the system clock signal 508, the DCMTON signal 526, and the DCM signal 530 through the inverter 524 are input to the second D flip-flop 538. The second D flip-flop 538 generates a falling edge synchronization signal 506 for synchronizing the DCMTON signal 526 on the falling edge of the system clock signal 508. The rising edge synchronization signal 516 and the falling edge synchronization signal 506 are ored through the or gate 518 to generate a first synchronization signal 528.

In some embodiments, the first synchronization signal 528 generated by the clock synchronization circuit 504 is transmitted to the third output circuit 506. The system clock signal 536 logically andes with the first synchronization signal 528 to generate the driving clock signal 522 through the and gate 520 in the output circuit 506. The driving clock signal generates an inverted signal 534 through an inverter 532. The driving clock signal 522 and the inverted signal 534 are coupled to be transmitted to the charge pump to control the current output of the charge pump.

Fig. 6 shows a timing diagram of related signals in an exemplary drive clock signal generation circuit according to an embodiment of the present disclosure. Fig. 6 will be described in conjunction with fig. 5. Fig. 6 includes a system clock signal CLK, a DCMTON signal DCMTON, a first synchronization signal DCMTON _ syn, a driving clock signal driver _ clock, and an inversion signal driver _ clock.

As shown in fig. 6, the system clock signal CLK and the DCMTON signal are not synchronized. The synchronized first synchronization signal DCMTON _ sync is generated by synchronizing the DCMTON signal with the system clock signal CLK at the rising edge by the first D flip-flop 514 in fig. 5 and synchronizing the DCMTON signal with the system clock signal CLK at the falling edge by the second D flip-flop 538. After the first synchronization signal dcmton _ sync is anded with the system clock signal CLK, a driving clock signal driver _ clock is generated. The driving clock signal driver _ clock generates an inverted signal driver _ clock kb through an inverter. The driving clock signal driver _ clock and the reverse signal driver _ clock are coupled to control a power switch tube in the charge pump to output current.

Fig. 7 shows a schematic diagram of an exemplary over-current protection circuit 700, in accordance with an embodiment of the present disclosure. As shown in fig. 7, the over-current protection circuit includes a sampling circuit 702 and a comparison circuit 704, which can detect the current in the charge pump and rapidly turn off the power switch tube to protect the charge pump in case of excessive current.

In some embodiments, the power switch 708 is a power switch in a charge pump, and the sampling circuit 702 includes a sampling circuit that is the same type as the power switch 708 and has a ratio of 1:500 to 1:1000 to sample the current flowing through the power switch tube 708. The sampling circuit 702 further includes a current sampling op-amp 710 and a sampling resistor 716, wherein the sampled current is amplified and converted by the current sampling op-amp 710, and a first voltage 726 proportional to the current of the power switch 708 is generated across the sampling resistor 716.

In some embodiments, the comparison circuit 704 includes a first comparator 712 and a second comparator 718.

In some embodiments, the over-current thresholds input to the first comparator 712 and the second comparator 718 include a first threshold 722 and a second threshold 724.

In some embodiments, the first comparator 712 and the second comparator 718 are coupled with the sampling circuit 702. The first comparator 712 compares the first voltage 726 of the sampling circuit with a first threshold 722 and generates the first charge pump drive signal 714 when the first voltage 726 is lower than the first threshold 722. The second comparator 718 compares the first voltage 726 of the sampling circuit 702 with a second threshold 724 and generates a second charge pump drive signal 720 when the first voltage 726 is lower than the second threshold 724. The first charge pump driving signal 714 and the second charge pump driving signal 720 control the switching tube of the charge pump to be turned off quickly, so that the charge pump stops outputting, and the purpose of overcurrent protection is achieved.

Fig. 8 shows a schematic diagram of an example charge pump 800 in accordance with an embodiment of the present disclosure. Fig. 8 will be described in conjunction with fig. 6. As shown in fig. 8, in some embodiments, the charge pump includes

power switching tubes

806, 816, 828, 838, 810, 820, 832, 842, and flying capacitors 821, 824. The driving clock signal driver _ clock and the reverse signal driver _ clock kb in fig. 6 are coupled and transmitted to the

control terminals

804, 814, 826, 836, 808, 818, 830, 840 of the switching tubes to control the switching states of the switching

tubes

806, 816, 828, 838, 810, 820, 832, 842, thereby controlling the different operating modes of the charge pump. By comparing the output voltage 834 in FIG. 8 to the corresponding threshold values in FIG. 2, a system load condition can be determined.

At block 902, the output voltage of the charge pump is compared and logically operated with a threshold voltage, generating a DCM signal and a DCMTON signal.

At block 904, the DCM signal and the DCMTON signal are synchronized and logically operated with a system clock signal, generating a drive clock signal.

At block 906, the current output of the charge pump is controlled by a driving clock signal.

Other aspects of the charge pump control method are with reference to the charge pump control circuit embodiment.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A charge pump control circuit, comprising:

a comparison output circuit configured to compare and logically operate an output voltage of a charge pump with a threshold voltage to generate a DCM signal and a DCMTON signal, the comparison output circuit coupled with the charge pump; and

a driving clock signal generation circuit configured to synchronize and logically operate the DCM signal and the DCMTON signal with a system clock signal to generate a driving clock signal for controlling a current output of the charge pump, the driving clock signal generation circuit being coupled with the comparison output circuit and the charge pump, respectively;

wherein the driving clock signal generating circuit includes:

a third input circuit configured to receive the DCM signal, the DCMTON signal, and the system clock signal;

a clock synchronization circuit configured to: generating a rising edge synchronization signal for synchronizing the DCMTON signal at a rising edge of the system clock signal; generating a falling edge synchronization signal for synchronizing the DCMTON signal at a falling edge of the system clock signal; ORing the rising edge synchronization signal and the falling edge synchronization signal to generate a first synchronization signal, the clock synchronization circuit coupled with the third input circuit; and

a third output circuit configured to AND the first synchronization signal with the system clock signal to generate the driving clock signal, the third output circuit coupled with the clock synchronization circuit.

2. The circuit of claim 1, wherein the comparison output circuit comprises a DCM comparison output circuit and a DCMTON comparison output circuit.

3. The circuit of claim 2, wherein the DCM comparison output circuit comprises:

a first input circuit configured to receive the output voltage and the threshold voltage, the threshold voltage comprising at least a first threshold and a second threshold;

a DCM comparison circuit configured to compare the output voltage with the first and second thresholds, respectively, to generate a first comparison signal when the output voltage is greater than the first threshold and a second comparison signal when the output voltage is less than the second threshold, the DCM comparison circuit coupled with the first input circuit; and

a first output circuit configured to delay filter the first comparison signal to generate a high level DCM signal and delay filter the second comparison signal to generate a low level DCM signal, the first output circuit coupled with the DCM comparison circuit.

4. The circuit of claim 2, wherein the DCMTON comparison output circuit comprises:

a second input circuit configured to receive the output voltage, the threshold voltage, and the DCM signal, the threshold voltage including at least a third threshold and a fourth threshold;

a DCMTON comparison circuit configured to compare the output voltage to the third threshold and the fourth threshold, respectively, to generate a third comparison signal when the output voltage is less than the third threshold and a fourth comparison signal when the output voltage is greater than the fourth threshold, the DCMTON comparison circuit coupled with the second input circuit; and

a second output circuit configured to AND the third and fourth comparison signals with the DCM signal to generate a DCMTON signal, the second output circuit coupled with the DCMTON comparison circuit.

5. The circuit of claim 3, wherein the first threshold is determined based on an input voltage of a charge pump and a preconfigured DCM voltage; the second threshold is determined based on an input voltage of the charge pump, a preconfigured DCM voltage, and a preconfigured second hysteresis voltage.

6. The circuit of claim 4, wherein the third threshold is determined based on an input voltage of the charge pump and a preconfigured droop voltage; the fourth threshold is determined based on an input voltage of the charge pump, a preconfigured droop voltage, and a preconfigured first hysteresis voltage.

7. The circuit of claim 1, further comprising an over-current protection circuit configured to: sampling and amplifying the current in the charge pump to obtain a sampling current; converting the sampled current to a first voltage and comparing with a configurable over-current threshold, generating a charge pump drive signal, the charge pump drive signal for rapidly turning off the charge pump.

8. A charge pump control method, comprising:

comparing and logically operating the output voltage of the charge pump with a threshold voltage through a comparison output circuit to generate a DCM signal and a DCMTON signal, wherein the comparison output circuit is coupled with the charge pump;

synchronizing and logically operating the DCM signal and the DCMTON signal with a system clock signal through a driving clock signal generating circuit to generate a driving clock signal, wherein the driving clock signal generating circuit is respectively coupled with the comparison output circuit and the charge pump; and

controlling the current output of the charge pump by the driving clock signal;

wherein the threshold voltage comprises at least a first threshold and a second threshold, wherein generating the DCM signal comprises:

comparing, by the comparison output circuit, the output voltage with the first threshold and the second threshold, respectively, to generate a first comparison signal when the output voltage is greater than the first threshold and a second comparison signal when the output voltage is less than the second threshold; and

delay filtering the first comparison signal to generate the DCM signal of high level, and delay filtering the second comparison signal to generate the DCM signal of low level.

9. The method of claim 8, wherein the threshold voltage comprises at least a third threshold and a fourth threshold, wherein generating the DCMTON signal comprises:

comparing the output voltage with the third threshold and a fourth threshold, respectively, to generate a third comparison signal when the output voltage is less than the third threshold and a fourth comparison signal when the output voltage is greater than the fourth threshold; and

anding the third and fourth comparison signals with the DCM signal to generate the DCMTON signal.

10. The method of claim 8, wherein generating the driving clock signal comprises:

generating a rising edge synchronization signal for synchronizing the DCMTON signal at a rising edge of the system clock signal;

generating a falling edge synchronization signal for synchronizing the DCMTON signal at a falling edge of the system clock signal;

OR-ing the rising edge synchronization signal and the falling edge synchronization signal to generate a first synchronization signal; and

and operating the first synchronization signal with the system clock signal to generate the driving clock signal.

11. The method of claim 8, wherein the pulses of the driving clock signal are multiples of a frequency division of the system clock signal.