CN114242735A - Array substrate, manufacturing method and mobile terminal - Google Patents

Array substrate, manufacturing method and mobile terminal Download PDF

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Publication number
CN114242735A
CN114242735A CN202111530127.0A CN202111530127A CN114242735A CN 114242735 A CN114242735 A CN 114242735A CN 202111530127 A CN202111530127 A CN 202111530127A CN 114242735 A CN114242735 A CN 114242735A
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China
Prior art keywords
active
layer
active portion
array substrate
substrate
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CN202111530127.0A
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Chinese (zh)
Inventor
刘倩
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202111530127.0A priority Critical patent/CN114242735A/en
Publication of CN114242735A publication Critical patent/CN114242735A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors

Abstract

The application provides an array substrate, a manufacturing method and a mobile terminal; the array substrate comprises a substrate and an active layer arranged on the substrate, wherein the active layer comprises a first active part arranged on the substrate and a second active part arranged on the first active part, and the mass ratio of crystals in the second active part is larger than or equal to that in the first active part; the active layer is arranged to comprise the first active portion and the second active portion, and the second active portion and the first active portion are at least partially crystallized, so that unstable movement of carriers can be hindered through semiconductor crystallization, and the stability of the oxide semiconductor thin film transistor is improved.

Description

Array substrate, manufacturing method and mobile terminal
Technical Field
The application relates to the field of display technologies, in particular to an array substrate, a manufacturing method and a mobile terminal.
Background
Thin Film Transistors (TFTs) are also classified into different types according to the material of an active layer, and a TFT in which the material of the active layer is an oxide semiconductor is called an oxide semiconductor TFT. The oxide semiconductor thin film transistor has a difference between a crystalline oxide semiconductor and an amorphous oxide semiconductor depending on the state of the oxide semiconductor. Since the amorphous oxide semiconductor material has the characteristics of high film formation uniformity and high product yield, most of the active layer materials of the oxide semiconductor thin film transistor at the present stage are amorphous oxide semiconductors.
However, in the amorphous oxide semiconductor thin film transistor, due to the presence of oxygen vacancy defects, unstable movement of carriers is likely to occur under the influence of external thermal stimulation or photostimulation, and the threshold voltage of the thin film transistor is shifted positively or negatively, which is disadvantageous to the operation stability of the device.
Disclosure of Invention
The application provides an array substrate, a manufacturing method and a mobile terminal, which aim to solve the technical problem that the working stability of a device of a current amorphous oxide semiconductor thin film transistor is poor.
In order to solve the technical problem, the technical scheme provided by the application is as follows:
the application provides an array substrate, includes:
a substrate;
an active layer disposed on the substrate, the active layer including a first active portion disposed on the substrate and a second active portion disposed on the first active portion;
wherein a crystal mass fraction within the second active portion is greater than or equal to a crystal mass fraction within the first active portion.
In the array substrate of the present application, a crystal size in the second active portion is greater than or equal to a crystal size in the first active portion.
In the array substrate of the present application, the number of crystals in the second active portion is less than or equal to the number of crystals in the first active portion per unit area parallel to the substrate.
In the array substrate of the present application, the array substrate further includes a gate layer disposed on a side of the active layer close to the substrate and a source drain layer disposed on a side of the active layer away from the substrate;
the gate layer and the active layer are arranged in an insulating manner, and the source drain layer is connected with the second active portion.
In the array substrate of the present application, the array substrate further includes a gate insulating layer disposed between the gate electrode layer and the first active portion and a crystalline insulating layer disposed on the gate insulating layer;
wherein the crystalline insulating layer is provided continuously with the second active portion.
In the array substrate of the present application, the crystal size in the second active portion is greater than or equal to the crystal size in the crystalline insulating layer, and the number of crystals in the second active portion is less than or equal to the number of crystals in the crystalline insulating layer per unit area parallel to the substrate.
The application provides a manufacturing method of an array substrate, which includes:
forming an active layer on a substrate;
and crystallizing the active layer to form a first active part and a second active part positioned on the first active part, wherein the crystal mass ratio in the second active part is larger than or equal to that in the first active part.
In the method for manufacturing an array substrate of the present application, the step of crystallizing the active layer to form a first active portion and a second active portion on the first active portion includes:
depositing a seed layer on the surface of the active layer, wherein the seed layer contains impurity crystal nuclei;
and annealing the seed layer to form a first active part and a second active part positioned on the first active part.
In the method for manufacturing the array substrate, the step of depositing the seed layer on the surface of the active layer includes:
and carrying out plasma treatment on the surface of the active layer, wherein plasma gas adopted by the plasma treatment comprises one or more of oxygen, nitrogen, helium and argon.
The application also provides a mobile terminal, which comprises a terminal main body and the array substrate, wherein the array substrate and the terminal main body are combined into a whole.
Has the advantages that:
the active layer is arranged to comprise a first active portion and a second active portion, and the crystal mass proportion in the second active portion is larger than or equal to the crystal mass proportion in the first active portion, namely the second active portion and the first active portion are at least partially crystallized, so that unstable movement of carriers can be hindered through semiconductor crystallization, and the device stability of the oxide semiconductor thin film transistor is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a first structure of an array substrate according to the present application;
FIG. 2 is a schematic view of a second structure of the array substrate of the present application;
FIG. 3 is a block flow diagram of a method for fabricating an array substrate according to the present disclosure;
fig. 4 to 9 are schematic views illustrating a manufacturing process of the array substrate according to the present application.
Description of reference numerals:
the semiconductor device includes a substrate 100, an active layer 200, a seed layer 201, a first active portion 210, a second active portion 220, a gate layer 300, a gate insulating layer 400, a source-drain layer 500, a passivation layer 600, an isolation protection layer 700, and a crystalline insulating layer 800.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The semiconductor active layer materials of a commonly used Thin Film Transistor (TFT) are: amorphous silicon material (a-Si), Low Temperature polysilicon material (LTPS), indium zinc oxide (IZ 0), Indium Gallium Zinc Oxide (IGZO), etc., which are deposited by dc or ac magnetron sputtering to form a uniform film on a large-area substrate, thereby improving the yield of the product.
The active layer material of the oxide semiconductor thin film transistor at the present stage is mostly amorphous oxide semiconductor because the amorphous oxide semiconductor material has the characteristics of high film forming uniformity and high product yield. However, in the amorphous oxide semiconductor thin film transistor, due to the presence of oxygen vacancy defects, unstable movement of carriers is likely to occur under the influence of external thermal stimulation or photostimulation, and the threshold voltage of the thin film transistor is shifted positively or negatively, which is disadvantageous to the operation stability of the device. The present application proposes the following solutions based on the above technical problems.
Referring to fig. 1 to 9, the present application provides an array substrate, including:
a substrate 100;
an active layer 200 disposed on the substrate 100, the active layer 200 including a first active portion 210 disposed on the substrate 100 and a second active portion 220 disposed on the first active portion 210;
wherein a crystal mass fraction in the second active portion 220 is greater than or equal to a crystal mass fraction in the first active portion 210.
The active layer 200 is provided to include the first active portion 210 and the second active portion 220, and the crystal mass ratio in the second active portion 220 is greater than or equal to the crystal mass ratio in the first active portion 210, that is, the second active portion 220 and the first active portion 210 are at least partially crystallized, so that unstable movement of carriers can be hindered through semiconductor crystallization, and the device stability of the oxide semiconductor thin film transistor can be improved.
The technical solution of the present application will now be described with reference to specific embodiments. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
In the array substrate of the present application, the substrate 100 may be a glass substrate or a polyimide substrate.
In the present embodiment, the material of the active layer 200 may include an oxide semiconductor material, such as one or more of an indium zinc oxide (IZ 0) and an Indium Gallium Zinc Oxide (IGZO). Wherein the oxide semiconductor material may include one of a fully crystalline oxide semiconductor or a partially crystalline amorphous oxide semiconductor. In this embodiment, the oxide semiconductor materials of the second active portion 220 and the first active portion 210 may be the same or different.
Referring to fig. 1, in this embodiment, the array substrate may further include a gate layer 300 disposed on the substrate 100, a gate insulating layer 400 disposed between the gate layer 300 and the active layer 200, a source drain layer 500 disposed on the active layer 200, a passivation layer 600 disposed on the source drain layer 500, an isolation protection layer 700 disposed on the passivation layer 600, and a pixel electrode layer (not shown) disposed on the isolation protection layer 700.
In this embodiment, the source and drain layer 500 may be connected to the second active portion 220, and the source and drain layer 500 may include a source electrode and a drain electrode respectively connected to two channel regions of the second active portion 220. In this embodiment, the gate layer 300, the active layer 200 and the source/drain layer 500 form a bottom-gate thin film transistor, and in the bottom-gate thin film transistor, the crystalline second active portion 220 has excellent etching resistance, so that a channel region in the active layer 200 can be protected, and channel damage can be prevented during a process of etching the source/drain layer 500.
In this embodiment, the gate layer 300 and the source/drain layer 500 may be made of a metal material with a large work function, good shape stability, electrical conductivity, thermal conductivity, and the like, such as Mo, Al, Cu, Ti, and the like.
In this embodiment, the gate insulating layer 400 and the passivation layer 600 may be made of SiOxOr is SiNxAnd the like, so as to play roles of water and gas resistance, insulation and the like and protect other structures of the thin film transistor.
In this embodiment, the isolation and protection layer 700 may be made of a polymer material, such as teflon or the like.
In this embodiment, the pixel electrode layer may be made of a transparent conductive material, such as an indium tin oxide material.
Referring to fig. 1 and 2, in the array substrate of the present application, the first active portion 210 may include a crystal or may not include a crystal.
Referring to fig. 1, in the present embodiment, the first active portion 210 may include crystals, and a mass ratio of the crystals in the first active portion 210 is equal to a mass ratio in the second active portion 220, so that the active layer 200 has a uniform crystal structure, thereby better improving the instability of the oxide semiconductor thin film transistor.
Referring to fig. 1, in the present embodiment, the first active portion 210 may not contain crystals, and the mass ratio of the crystals in the first active portion 210 is 0% at this time, so that the first active portion 210 and the second active portion 220 of the active layer 200 form an amorphous-crystalline double-layer structure.
Referring to fig. 2, in the present embodiment, the second active portion 220 may cover the surface of the first active portion 210, that is, the second active portion 220 may be located on the surface of the first active portion 210 except the surface contacting the gate insulating layer 400, so that the second active portion 220 in a crystalline state may shield and protect the first active portion 210 in an amorphous state (especially, a channel region in the first active portion 210) to prevent channel damage.
In this embodiment, the upper crystalline second active portion 220 may hinder unstable movement of carriers, thereby improving device stability of the oxide semiconductor thin film transistor, and the crystalline second active portion 220 may also improve the etching resistance of the active layer 200, thereby preventing etching damage and protecting the back channel. The lower amorphous first active region 210 may improve film formation uniformity and carrier mobility of the active layer 200. In this embodiment, the combined action of the amorphous first active portion 210 and the crystalline second active portion 220 not only improves the device stability of the mos thin film transistor, but also ensures better film formation uniformity, etching uniformity, and carrier mobility.
In the array substrate of the present application, the crystal size in the second active portion 220 is greater than or equal to the crystal size in the first active portion 210.
In this embodiment, the crystal size in the second active portion 220 may be larger than the crystal size in the first active portion 210, that is, both the second active portion 220 and the first active portion 210 may include crystals, or the second active portion 220 includes crystals and the first active portion 210 does not include crystals.
Referring to fig. 1 and 2, in the present embodiment, when the second active portion 220 includes a crystal and the first active portion 210 does not include a crystal, all of the second active portions 220 may have a crystal structure, all of the first active portions 210 may have an amorphous structure, and the second active portions 220 and the first active portions 210 form a crystalline-amorphous double-layer structure, so that the upper crystalline second active portions 220 hinder unstable movement of carriers, improve device stability of the oxide semiconductor thin film transistor and etching resistance of the active layer 200, and prevent etching damage and protect a back channel, and the lower amorphous first active portions 210 can improve film formation uniformity and carrier mobility of the active layer 200.
When the second active portion 220 and the first active portion 210 both include crystals, the size of the crystals gradually decreases in the direction from the second active portion 220 to the first active portion 210. At this time, the crystal size in the second active portion 220 and the first active portion 210 depends on the crystal growth time, that is, the crystal in the second active portion 220 grows first, so the crystal size is large, and the crystal in the first active portion 210 grows later, so the crystal size is small.
In the present embodiment, it is preferable that the crystal size in the second active portion 220 is the same as the crystal size in the first active portion 210, so that the crystal structure in the active layer 200 has good grain uniformity and grain boundary distribution is uniform. At this time, the crystal formation in the first active portion 210 and the second active portion 220 reaches a saturation state, i.e., a state in which the crystal grain sizes of all the crystals are uniform.
In the array substrate of the present application, the number of crystals in the second active portion 220 is less than or equal to the number of crystals in the first active portion 210 per unit area parallel to the substrate 100.
In the present embodiment, the number of crystals in the first and second active portions 210 and 220 is related to the size of crystals in the first and second active portions 210 and 220. The concrete description is as follows: when the crystal size in the second active portion 220 is larger than the crystal size in the first active portion 210, the number of crystals in the second active portion 220 is smaller than the number of crystals in the first active portion 210 in a unit area parallel to the substrate 100; when the crystal size in the second active portion 220 is equal to the crystal size in the first active portion 210, the number of crystals in the second active portion 220 is equal to the number of crystals in the first active portion 210 in a unit area parallel to the substrate 100.
It should be noted that the crystal size and the number of crystals in the first active portion 210 and the second active portion 220 in this embodiment are not structural designs that exist independently, but are related to the crystallization mode of the active layer 200 in this embodiment.
Through the above arrangement, the crystal size and the crystal number in the first active portion 210 and the second active portion 220 can be adapted, and the effects of improving the device stability and the etching resistance of the active layer 200, preventing etching damage, protecting a back channel, improving the film formation uniformity and the carrier mobility of the active layer 200, and the like are achieved.
Referring to fig. 1 and 2, in the array substrate of the present application, the array substrate further includes a gate insulating layer 400 disposed between the gate electrode layer 300 and the first active portion 210, and a crystalline insulating layer 800 disposed on the gate insulating layer 400. In this embodiment, the crystalline insulating layer 800 may be disposed on the gate insulating layer 400 in a region except for a region in contact with the first active portion 210.
In this embodiment, the crystalline insulating layer 800 may be made of an organic photoresist material.
In this embodiment, the crystalline insulating layer 800 may be continuously disposed with the second active portion 220, so that the crystalline insulating layer may be formed in the same process, thereby simplifying the manufacturing process and reducing the process cost.
In this embodiment, the crystalline insulating layer 800 is disposed on the gate insulating layer 400, so that the breakdown voltage of the gate metal and the source/drain metal in the region of the array substrate other than the thin film transistor can be increased, thereby reducing the risk of electrostatic discharge (ESD) of the gate metal and the source/drain metal.
In the array substrate of the present application, the crystal size in the second active portion 220 is greater than or equal to the crystal size in the crystalline insulating layer 800, and the number of crystals in the second active portion 220 is less than or equal to the number of crystals in the crystalline insulating layer 800 in a unit area parallel to the substrate 100.
In the present embodiment, the second active portion 220 is an inorganic material of a metal oxide semiconductor, and the crystalline insulating layer 800 is made of an organic photoresist material. Since the second active portion 220 and the crystalline insulating layer 800 can be formed in the same process, i.e., the initial crystal nucleus densities of the second active portion 220 and the crystalline insulating layer 800 are substantially similar, the difference between the crystal sizes and the numbers of the second active portion 220 and the crystalline insulating layer 800 depends on the material differences of the second active portion 220 and the crystalline insulating layer 800. Compared to the crystalline insulating layer 800 made of an organic material, the growth rate of crystal nuclei in the second active portion 220 made of an inorganic material is faster, the crystal lattice size is larger, and the number of crystals per unit area parallel to the substrate 100 is correspondingly smaller than that of the crystalline insulating layer 800.
In this embodiment, the active layer 200 is configured to include the first active region 210 and the second active region 220, and the crystal mass ratio in the second active region 220 is greater than or equal to the crystal mass ratio in the first active region 210, that is, the second active region 220 and the first active region 210 are at least partially crystallized, so that not only the film formation uniformity and the etching uniformity of the active layer 200 can be ensured, but also the unstable motion of carriers can be hindered by the crystallization of semiconductors, thereby improving the device stability of the oxide semiconductor thin film transistor.
Referring to fig. 3 to 9, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
s100, forming an active layer 200 on the substrate 100;
s200, crystallizing the active layer 200 to form a first active portion 210 and a second active portion 220 on the first active portion 210, and making a crystal mass ratio in the second active portion 220 greater than or equal to a crystal mass ratio in the first active portion 210.
In this embodiment, the active layer 200 is crystallized, and in this process, the second active portion 220 with a larger crystal mass and the first active portion 210 with a smaller crystal mass are formed in the active layer 200 by controlling the grain size and the crystallization speed, so that the film formation uniformity and the carrier mobility of the active layer 200 are improved by the first active portion 210, the etching resistance is improved by the second active portion 220, the back channel is protected to prevent the etching damage and reduce the unstable motion of the carrier, and the device stability of the thin film transistor is further improved.
In this embodiment, the "crystal mass ratio" may be understood as: the ratio of the crystal mass within the first/second active portions 210, 220 to the total mass of the first/second active portions 210, 220.
In the method for manufacturing an array substrate of the present application, referring to fig. 4 and 5, the step S100 may include:
s110, forming a gate material layer on the substrate 100, developing and etching to form a patterned gate layer 300;
s120, forming a gate insulating layer 400 on the gate layer 300;
s130, forming an active material layer on the gate insulating layer 400, and developing and etching to form the patterned active layer 200.
In the method for manufacturing an array substrate of the present application, referring to fig. 6 and 7, the step S200 may include:
s210, depositing a seed layer 201 on the surface of the active layer 200, wherein the seed layer 201 comprises impurity crystal nuclei.
In this embodiment, the seed layer 201 deposited on the surface of the active layer 200 may be formed by dc plasma sputtering or ac plasma sputtering to form a crystal nucleus.
In this embodiment, the plasma sputtering can be performed by a gas that does not cause an increase in defects in the oxide semiconductor material, such as oxygen, nitrogen, helium, or argon. In this embodiment, the plasma treatment may preferably use oxygen to improve the defect uniformity of the oxide semiconductor material.
In the present embodiment, the crystalline insulating layer 800 may be formed on the surface of the gate insulating layer 400 in the same process, i.e., the seed layer 201 may be deposited on the surface of the active layer 200 and the surface of the gate insulating layer 400 in the same process, so as to simplify the manufacturing process and reduce the time cost and the economic cost.
S220, annealing the seed layer 201 to form a first active portion 210 and a second active portion 220 on the first active portion 210.
In this embodiment, the seed layer 201 on the gate insulating layer 400 may be simultaneously annealed in the same process to form the crystalline insulating layer 800.
In this embodiment, the annealing process on the seed layer 201 may be performed by processing the seed layer 201 at a high temperature or by using a laser, and forming a crystallization layer in the active layer 200 and on the gate insulating layer 400 after the seed layer 201 is cooled.
This embodiment is through above mode preparation seed layer 201 and to through high temperature or laser mode seed layer 201 carries out annealing treatment, and not only the preparation that makes seed layer 201 is more high-efficient and crystal nucleus distribution is even, thereby the growth rate control crystal size and the quantity of crystal that can also accurate control crystal nucleus improve crystalline grain homogeneity and grain boundary distribution uniformity.
In the method for manufacturing an array substrate of the present application, referring to fig. 8 and 9, the method for manufacturing an array substrate may further include:
s300, forming a source drain layer 500 on the active layer 200 after the crystallization treatment, and etching a patterned source electrode and a patterned drain electrode.
S400, forming a passivation layer 600 on the source drain layer 500, forming an isolation protection layer 700 on the passivation layer 600, patterning the isolation protection layer 700, and forming a pixel electrode layer opposite to the source drain layer 500 on the patterned isolation protection layer 700.
The embodiment of the application further provides a mobile terminal, the mobile terminal comprises a terminal main body and the array substrate, and the terminal main body and the array substrate are combined into a whole. In this embodiment, the mobile terminal may be an intelligent display device such as a mobile phone, a computer, a watch, and the like.
The array substrate, the manufacturing method thereof and the mobile terminal provided by the embodiment of the present application are introduced in detail, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An array substrate, comprising:
a substrate;
an active layer disposed on the substrate, the active layer including a first active portion disposed on the substrate and a second active portion disposed on the first active portion;
wherein a crystal mass fraction within the second active portion is greater than or equal to a crystal mass fraction within the first active portion.
2. The array substrate of claim 1, wherein the crystal size in the second active portion is greater than or equal to the crystal size in the first active portion.
3. The array substrate of claim 2, wherein the number of crystals in the second active portion is less than or equal to the number of crystals in the first active portion per unit area parallel to the substrate.
4. The array substrate of claim 1, further comprising a gate layer disposed on a side of the active layer close to the substrate and a source drain layer disposed on a side of the active layer away from the substrate;
the gate layer and the active layer are arranged in an insulating manner, and the source drain layer is connected with the second active portion.
5. The array substrate of claim 4, further comprising a gate insulating layer disposed between a gate layer and the first active portion and a crystalline insulating layer disposed on the gate insulating layer;
wherein the crystalline insulating layer is provided continuously with the second active portion.
6. The array substrate of claim 1, wherein a crystal size in the second active portion is greater than or equal to a crystal size in the crystalline insulating layer, and wherein a number of crystals in the second active portion is less than or equal to a number of crystals in the crystalline insulating layer per unit area parallel to the substrate.
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming an active layer on a substrate;
and crystallizing the active layer to form a first active part and a second active part positioned on the first active part, wherein the crystal mass ratio in the second active part is larger than or equal to that in the first active part.
8. The method for manufacturing the array substrate according to claim 7, wherein the step of crystallizing the active layer to form a first active portion and a second active portion on the first active portion comprises:
depositing a seed layer on the surface of the active layer, wherein the seed layer contains impurity crystal nuclei;
and annealing the seed layer to form a first active part and a second active part positioned on the first active part.
9. The method for manufacturing the array substrate of claim 7, wherein the step of depositing the seed layer on the surface of the active layer comprises:
and carrying out plasma treatment on the surface of the active layer, wherein plasma gas adopted by the plasma treatment comprises one or more of oxygen, nitrogen, helium and argon.
10. A mobile terminal comprising a terminal body and the array substrate of claims 1 to 6, wherein the array substrate and the terminal body are combined into a single body.
CN202111530127.0A 2021-12-14 2021-12-14 Array substrate, manufacturing method and mobile terminal Pending CN114242735A (en)

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