WO2003096110A1 - Method for providing transparent substrate having protection layer on crystalized polysilicon layer, method for forming polysilicon active layer thereof and method for manufacturing polysilicon tft using the same - Google Patents

Method for providing transparent substrate having protection layer on crystalized polysilicon layer, method for forming polysilicon active layer thereof and method for manufacturing polysilicon tft using the same Download PDF

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Publication number
WO2003096110A1
WO2003096110A1 PCT/KR2003/000935 KR0300935W WO03096110A1 WO 2003096110 A1 WO2003096110 A1 WO 2003096110A1 KR 0300935 W KR0300935 W KR 0300935W WO 03096110 A1 WO03096110 A1 WO 03096110A1
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layer
poly
forming
protection
protection layer
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PCT/KR2003/000935
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French (fr)
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Taehoon Jeong
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Taehoon Jeong
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Publication of WO2003096110A1 publication Critical patent/WO2003096110A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04B—GENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B2/00—Walls, e.g. partitions, for buildings; Wall construction with regard to insulation; Connections specially adapted to walls
    • E04B2/74—Removable non-load-bearing partitions; Partitions with a free upper edge
    • E04B2/7407—Removable non-load-bearing partitions; Partitions with a free upper edge assembled using frames with infill panels or coverings only; made-up of panels and a support structure incorporating posts
    • E04B2/7416—Removable non-load-bearing partitions; Partitions with a free upper edge assembled using frames with infill panels or coverings only; made-up of panels and a support structure incorporating posts with free upper edge, e.g. for use as office space dividers
    • E04B2/7422—Removable non-load-bearing partitions; Partitions with a free upper edge assembled using frames with infill panels or coverings only; made-up of panels and a support structure incorporating posts with free upper edge, e.g. for use as office space dividers with separate framed panels without intermediary support posts
    • E04B2/7425—Details of connection of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04B—GENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B2/00—Walls, e.g. partitions, for buildings; Wall construction with regard to insulation; Connections specially adapted to walls
    • E04B2/74—Removable non-load-bearing partitions; Partitions with a free upper edge
    • E04B2002/7487—Partitions with slotted profiles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam

Definitions

  • This invention regards to a method to provide the transparent
  • LCD Liquid Crystal Display
  • TFTs Thin Film Transistors
  • a-Si amorphous Si
  • substrates need to be crystallized.
  • ELA laser annealing
  • SPC is the method to use high temperature (600 ° C) to crystallize a-Si.
  • high temperature 600 ° C
  • poly-Si has lack of crystallinity due to the defects inside each poly-Si grains.
  • the high temperature ( ⁇ 1000 ° C) process is often used for thermal oxide as gate insulator. Therefore, expensive quartz substrates, to withstand the high temperature, have to be used.
  • MILC is the method to use a furnace annealing and a small amount of metals on top of a-Si to catalyze the crystallization.
  • the metals act as lower the enthalpy for the crystallization of a-Si. Therefore, a low temperature such as
  • ELA is a method to be used most widely.
  • the range of UV and pulsed laser beams are used.
  • Khaibullin employed Laser to anneal the extrinsic Si layer for Large Scale Integration (LSI) process.
  • LSI Large Scale Integration
  • this laser annealing method starts to be used for fabrication of mobile LTPS TFT-LCD products.
  • This is most efficient method to crystallization of Si films because ELA does not damage the transparent substrate.
  • excimer laser itself can lead to a direct melting of Si films, the temperature of the substrates stay at room temperature during the laser annealing process because the pulse duration of excimer laser is extremely short ( ⁇ 20 ⁇ 30nano seconds). With this method, due to the clean and high quality of liquid-phase crystallized Si, the mobility of poly-Si TFT is exceeding
  • Si films are temporarily melted and solidified and becomes poly-Si films.
  • the degree of melting and quality of poly-Si change. For example, if the energy density of the laser is higher, the deeper the melting of a-Si. As we increase the energy density, the more the amount of a-Si.
  • the grain size of poly-Si is proportional to the energy density of
  • grains to be laterally grown starting from unmelted a-Si as "seeds" of the growth are laterally grown starting from unmelted a-Si as "seeds" of the growth.
  • the poly-Si TFT requires not only high-performance but uniformity and reproducibility.
  • the definition of the layers may vary but most likely the less number of masks and a p-gate structure are used.
  • the Si layer becomes "open” because gate insulator need to be deposited on patterned Si layer.
  • the substrates remain in the clean room for fairy long time for the next process step. Furthermore, if the substrates are needed to
  • the TFT characteristics may be damaged or
  • This invention which is contrived to solve the above problems, provides the method to have the clean interface between poly-Si and gate insulator to
  • one aspect of the invention is to provide transparent substrates with a protection layer on top of
  • crystallized poly-Si films is composed of a step of a-Si thin films deposition on
  • this invention provide the method; a step of etching the protection layer partially or entirely to be equal or less than the thickness of the gate insulator and a step of patterning active Si
  • TFT using poly-Si active layer provides the method; a step of forming gate
  • insulator as an either entire or remaining protection layer during the etching step or an additional gate insulator deposition on top of remaining protection
  • Fig.1 is the illustration of the method to provide the transparent substrate according to a reference of desirable execution of the invention.
  • Fig.2 is the illustration of forming the poly-Si active layer according to a reference of desirable execution of the invention.
  • Fig.3 is the illustration of the fabrication of poly-Si TFT according to a reference of desirable execution of the invention.
  • the insulating layer, the a-Si layer, and the metal layer can be formed using both LPCVD and PECVD. It is natural to even include the Sputtering method depending on the layers.
  • Fig. 1 is the illustration of the method to provide the transparent
  • a buffer layer is formed on a transparent substrate.
  • Transparent substrates are not specially limited, for example, glass substrates, plastic substrates, and flexible substrates. Particularly the technical aspect can use any semiconductor substrates, which is noticed, instead of transparent substrates.
  • the buffer layer plays a role to prevent any
  • Buffer layer can be insulating layer, for example, SiNx, SiOx, and any kind of well-known insulating layers are possible. These layers can be deposited using PECVD method. The thickness of the
  • buffer layer could be, for example, 1000 to 10000 A but most likely is 2000 to
  • Si layer 30 is formed on the transparent substratel O.
  • Si layer 30 is formed on the buffered layer mentioned above by SiH4 source gas
  • the buffered layer and the a-Si layer 30 should be formed by a serial process. It is more desirable that the serial processes can be PECVD
  • the thickness of a-Si layer 30 can be from 300 A to 1000 A , for
  • the a-Si layer 30 is crystallized partially or completely.
  • the crystallization can be executed by, for example, SPC method, MIC method or
  • the vertical partial of complete region of the a-Si layer 30 is crystallized. It is desirable that the crystallization equipment is designed as a cluster type so that
  • the vacuum state should be maintained from the a-Si formation process to the crystallization process.
  • the equipment is composed of the cluster type, one can perform the buffered layer 20 and the a-Si layer 30 successively, and then crystallize the a-Si layer by the excimer laser maintaining the vacuum state.
  • the forming method of poly-Si layer 40 mentioned above can be, especially, an as-deposition method similar to the method of an a-Si deposition. Table 1. shows that the typical deposition conditions of poly-Si and a-Si, comparatively.
  • a protection layer 50 is formed on the crystallized poly-Si layer 40 mentioned above, It is essential to keep the interface between the poly-Si 40 and the protection layer 50 clean because the protection layer 50 is formed directly on the surface of poly-Si layer 40 as an active layer. For this reason, it is desirable that the protection layer 50 should be formed on the poly-Si layer 40 under vacuum environments by PECVD system in the cluster-type equipment composed of PECVD system as well as laser annealing system as mentioned
  • the protection layer 50 can be all kind of insulating materials well-known
  • organic materials such as PC41 1 B, PC403, PC455R1 ,
  • PC452, TR-SJ31 , PMHS-914 etc. can be applied to a protection layer.
  • layer 50 may be the same material for the buffered layer 20 or not.
  • thickness of the protection layer 50 can be determined from 50 A to a few ⁇ m.
  • the thickness of protection layer 50 can be changed variously considering the kind and method of the latter part of process or the main purpose of the
  • protection layer For example, if full-etching of the protection layer is possible,
  • the thickness of the protection layer can be varied from 100 A to 5 ⁇ m.
  • the cleaning process for the interface between the poly-Si layer 40 and the protection layer (gate insulating layer) can be reduced remarkably, that is, the cleaning process for the interface between the active layer and the gate insulating layer using HF solution etc. is essential to the device characteristics for good qualities, but the excellent interface properties can be achieved by the process explained above without such cleaning process.
  • the transparent substrate on which the poly-Si and the protection layer are sequentially made by the process suggested above cannot be degraded in spite of the long-term stay during the process and can possess stable properties irrelevant to the stay-time to the latter part of the process. It is effective for the stability of process.
  • the protection layer 50 on the poly-Si layer 40 is etched partially or completely, that is, the protection layer 50 originally formed to protect the crystallized poly-Si layer 40 can be used as a gate insulating layer partially or
  • the thickness of the gate insulating layer ranges from 50 ⁇ A to 2000A and about 100 ⁇ A is suitable.), one may etch the whole
  • protection layer 50 can be remained after the partial or complete etching of the protection layer 50 in order that the thickness of remaining protection layer must be thinner than the thickness of gate insulating layer
  • the remaining layer is used for the gate insulating layer).
  • protection layer remaining layered structure is patterned to active part by simultaneous etching so that the upper layer of the final structure may be the protection layer 50 or poly-Si layer 40.
  • photo resist as a protection layer 50 can be used for the patterning of active layer, that is, photo lithography process using the very photo resist as protection layer 50 for the photo-sensing material can be applied directly to the patterning of active layer.
  • the whole process can be simplified effectively using the process suggested above, that is, the gate insulating layer forming step can be followed directly by that process.
  • protection layer 50 on the poly-Si active layer survived after the protection layer etch step can be used as a gate insulating layer, or the remaining protection layer 50 and
  • a gate insulating layer formed additionally after the protection layer etch step can be used together as a gate insulating layer, or a gate insulating layer
  • the protection layer etch step can be used individually as a gate insulating layer, in order to make the gate insulating layer whose
  • the general thickness of the gate-insulating layer varies from 50 ⁇ A to 2000A.
  • the newly formed gate-insulating layer 60 may be formed by the same material as that of the protection layer 50, or not.
  • the protection layer 50 may be formed by the same material as that of the protection layer 50, or not.
  • protection layer may be formed by Si0 2 and gate insulating layer 60 equally by
  • the protection layer may be formed by Si0 2 and gate insulating layer 60 by SiNx. It is still obvious that various combinations besides the cases mentioned above are possible.
  • the gate electrode 70 is sputtered and patterned by photolithography after the gate-insulating layer 60.
  • the fixed regions of the active layer are designated for the source/drain regions by doping n+ or p+ ions using the upper gate electrode 70 as a mask.
  • the thickness of the gate electrode 70 ranges, for example, from 1500A to 4000A and about 3000A is desirable.
  • the inter-insulating layer 80) is formed on the gate electrode 70 and patterned to contact holes 90.
  • the metal layer 100 is deposited and patterned in order to make electrical connection between the source/drain regions of the active layer and the data lines through the contacts 90.
  • the thickness of the inter-insulating layer 80 ranges, for example, from 2000A to 8000A.
  • N-type or P-type poly-Si TFTs can be fabricated by
  • the space or the photo resist can be formed at the both sides or one
  • This invention can be modified variously on condition that the
  • the present invention has an effect in making a crystallized poly-Si / gate insulator interface clean and have a high quality when the processing time is delayed between crystallization process and a next step or the crystallized sample has to be transferred out of clean room area.

Abstract

Disclosed is a method of providing a transparent substrate having a poly-Si layer on which a protection layer is deposited to maintain the interface between poly-Si and gate insulator clean. This invention discloses also the method of forming a poly-Si active layer and poly-Si thin film transistor using the poly-Si active layer. For this purpose, the present invention discloses a method of providing a transparent substrate having a poly-Si layer on which a protection layer is deposited, comprising the steps of; forming an a-Si thin film on a transparent substrate, crystallizing a part of or a whole area of a-Si thin film, forming a protection layer on the crystallized poly-Si layer.

Description

Method for Providing Transparent Substrate Having Protection
Layer on Crystalized Polysilicon layer, Method for Forming
Polysilicon Active Layer Thereof and Method for Manufacturing
Polysilicon TFT using the same
BACKGROUND OF THE INVENTION
(a) Field of the Invention
This invention regards to a method to provide the transparent
substrates with a protection layer on top of crystallized poly-Si films, especially,
a method to provide the transparent substrates with a protection layer on top of
crystallized poly-Si films in order to keep the clean interface between the poly-
Si and the gate insulator.
(b) Description of the Related Art
Recently, Thin Film Transistors has been used for switching device for
Liquid Crystal Display (LCD). In order to make poly-Si for the semiconductor
layer in the channel of Thin Film Transistors (TFTs), amorphous Si (a-Si) on the
substrates need to be crystallized.
For the crystallization of Si films, there exist a few method; such as, solid
phase crystallization (SPC), metal induced crystallization (MILC), and excimer
laser annealing (ELA).
SPC is the method to use high temperature (600 °C) to crystallize a-Si. With this method, poly-Si has lack of crystallinity due to the defects inside each poly-Si grains. To compensate this drawback, the high temperature (~1000°C) process is often used for thermal oxide as gate insulator. Therefore, expensive quartz substrates, to withstand the high temperature, have to be used.
MILC is the method to use a furnace annealing and a small amount of metals on top of a-Si to catalyze the crystallization. The metals act as lower the enthalpy for the crystallization of a-Si. Therefore, a low temperature such as
500 °C is possible but the surface of the Si layer is not high-quality. Furthermore,
the electrical characteristics become tawdry and there exist a lot of in-grain defects inside poly-Si grains.
ELA is a method to be used most widely. For the annealing, the range of UV and pulsed laser beams are used. In 1976, for the first time, Khaibullin employed Laser to anneal the extrinsic Si layer for Large Scale Integration (LSI) process. Recently, this laser annealing method starts to be used for fabrication of mobile LTPS TFT-LCD products. This is most efficient method to crystallization of Si films because ELA does not damage the transparent substrate. Although excimer laser itself can lead to a direct melting of Si films, the temperature of the substrates stay at room temperature during the laser annealing process because the pulse duration of excimer laser is extremely short (~20~30nano seconds). With this method, due to the clean and high quality of liquid-phase crystallized Si, the mobility of poly-Si TFT is exceeding
100 cπ /Vsec.
Methods of ELA for crystallization of a-Si are as follows.
Laser is irradiated on a-Si films. Si films are temporarily melted and solidified and becomes poly-Si films. Depending on the energy density of the excimer laser, the degree of melting and quality of poly-Si change. For example, if the energy density of the laser is higher, the deeper the melting of a-Si. As we increase the energy density, the more the amount of a-Si. After
the energy density reaches a certain threshold, a-Si films melt completely. To a
certain degree, the grain size of poly-Si is proportional to the energy density of
the laser. (In other words, the more a-Si melts, the larger the grain size of poly-
Si). This means that if the energy density is below the threshold, only upper side of a-Si melts partially. This gives a small-sized poly-Si grains. If the
energy density is reaching to the threshold energy density of complete melting,
only few a-Si remains unmelted whereas most of a-Si melts completely. This "near-complete-melting" condition gives unique environs to allow the poly-Si
grains to be laterally grown starting from unmelted a-Si as "seeds" of the growth.
Finally, this produces a large-grain poly-Si.
Incidentally, as the implementation of poly-Si TFT expands to Flat Panel Display such as TFT-LCD and Active Matrix Organic Light Emitting Diode
(AMOLED), the poly-Si TFT requires not only high-performance but uniformity and reproducibility.
One of the most important causes for the degradation of poly-TFT's uniformity and reproducibility is the fact that it is almost impossible to keep the
clean interfaces of each layer, which affect the TFT characteristics. Depending
on the TFT structures, the definition of the layers may vary but most likely the less number of masks and a p-gate structure are used. For the case of the top- gate structured poly-Si TFTs, after crystallization, the Si layer becomes "open" because gate insulator need to be deposited on patterned Si layer. For this
reason, the most important interface, between poly-Si and gate insulator, is impossible to have a clean interface.
In order to overcome this problem, many cleaning methods have been
developed. Especially HF based cleaning method is the one used most widely. However, the condition of HF cleaning is very sensitive to TFT performance and
sometimes not enough to clean the interface. Most importantly, after
crystallization process, the substrates remain in the clean room for fairy long time for the next process step. Furthermore, if the substrates are needed to
carry out to outside of clean room, the TFT characteristics may be damaged or
degraded.
SUMMARY OF THE INVENTION
This invention, which is contrived to solve the above problems, provides the method to have the clean interface between poly-Si and gate insulator to
sustain the TFT performances even if the TFT substrates are stagnated or
transferred outside.
In order to accomplish the purpose of the invention, one aspect of the invention is to provide transparent substrates with a protection layer on top of
crystallized poly-Si films, is composed of a step of a-Si thin films deposition on
transparent substrates, a step of crystallize the partial of entire a-Si thin films,
and a step of having protection layer on poly-Si
With regard to a method to provide transparent substrates with a protection layer on top of crystallized poly-Si films, this invention provide the method; a step of etching the protection layer partially or entirely to be equal or less than the thickness of the gate insulator and a step of patterning active Si
layer after etching the protection layer partially or entirely.
The another aspect of the invention, for the fabrication method of poly-Si
TFT using poly-Si active layer, provides the method; a step of forming gate
insulator as an either entire or remaining protection layer during the etching step or an additional gate insulator deposition on top of remaining protection
layer or, if there is not remaining protection layer, entirely new gate insulator deposition, a step of forming gate layer on top of gate insulator, a step of
forming source and drain using part of the active layer after ion-doping process using the gate layer as a mask for doping, a step of forming inter-layer dielectric
on the gate layer and making contact hole on the inter-layer dielectric, a step of
forming metal layer after contact process.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute
a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention:
Fig.1 is the illustration of the method to provide the transparent substrate according to a reference of desirable execution of the invention.
Fig.2 is the illustration of forming the poly-Si active layer according to a reference of desirable execution of the invention.
Fig.3 is the illustration of the fabrication of poly-Si TFT according to a reference of desirable execution of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying
drawings. However, the following references are provided for those of who has
conventional knowledge for the purpose of better understanding of the
inventions. So the invention can be transformed to various forms and does not limit the following references. Same mark refers to the same components.
Also, the insulating layer, the a-Si layer, and the metal layer can be formed using both LPCVD and PECVD. It is natural to even include the Sputtering method depending on the layers.
(A Method to Provide the Transpant Substrate with A Protection Layer on Top of Crystallized Poly-Si Films)
Fig. 1 is the illustration of the method to provide the transparent
substrate according to a reference of desirable execution of the invention.
Firstly, a buffer layer is formed on a transparent substrate. Transparent substrates are not specially limited, for example, glass substrates, plastic substrates, and flexible substrates. Particularly the technical aspect can use any semiconductor substrates, which is noticed, instead of transparent substrates.
At the same time, the buffer layer plays a role to prevent any
contamination from the substrates to poly-Si layer when poly-Si is formed during the crystallization process. Buffer layer can be insulating layer, for example, SiNx, SiOx, and any kind of well-known insulating layers are possible. These layers can be deposited using PECVD method. The thickness of the
buffer layer could be, for example, 1000 to 10000 A but most likely is 2000 to
5000 A.
Then, the a-Si layer 30 is formed on the transparent substratel O. Si layer 30 is formed on the buffered layer mentioned above by SiH4 source gas
diluted with Ar gas as a source gas using the PECVD process. It is desirable
that the buffered layer and the a-Si layer 30 should be formed by a serial process. It is more desirable that the serial processes can be PECVD
processes. The thickness of a-Si layer 30 can be from 300 A to 1000 A , for
example and 500 A is most suitable.
Then, the a-Si layer 30 is crystallized partially or completely. The crystallization can be executed by, for example, SPC method, MIC method or
ELA method. From now on, the laser annealing method is explained as an exemplary case. In this case, the statement of 'crystallized partially or
completely' must be comprehended to mean both that the a-Si layer 30 on the partial or complete region of the transparent substrate is crystallized and that
the vertical partial of complete region of the a-Si layer 30 is crystallized. It is desirable that the crystallization equipment is designed as a cluster type so that
the vacuum state should be maintained from the a-Si formation process to the crystallization process. When the equipment is composed of the cluster type, one can perform the buffered layer 20 and the a-Si layer 30 successively, and then crystallize the a-Si layer by the excimer laser maintaining the vacuum state. On the other hand, the forming method of poly-Si layer 40 mentioned above can be, especially, an as-deposition method similar to the method of an a-Si deposition. Table 1. shows that the typical deposition conditions of poly-Si and a-Si, comparatively.
[Table 1 ]
Figure imgf000009_0001
Then, a protection layer 50 is formed on the crystallized poly-Si layer 40 mentioned above, It is essential to keep the interface between the poly-Si 40 and the protection layer 50 clean because the protection layer 50 is formed directly on the surface of poly-Si layer 40 as an active layer. For this reason, it is desirable that the protection layer 50 should be formed on the poly-Si layer 40 under vacuum environments by PECVD system in the cluster-type equipment composed of PECVD system as well as laser annealing system as mentioned
above, after laser annealing has been completed using that cluster-type
equipment. Therefore, a-Si deposition step, partial or complete crystallization
step, and protection layer forming step are executed continuously through the
process explained above. In this statement, 'continuously' stands for the situation that the transparent substrate 10 do not emerge into the atmosphere
but stay under vacuum during the whole processes mentioned above.
The protection layer 50 can be all kind of insulating materials well-known
to the industry such as Si02 and SiNx and be deposited by PECVD method. Furthermore, photo resist or organic layer etc. formed by a coater, can be a protection layer. The organic materials such as PC41 1 B, PC403, PC455R1 ,
PC452, TR-SJ31 , PMHS-914 etc. can be applied to a protection layer.
On the other hand, it is obvious that the material used for the protection
layer 50 may be the same material for the buffered layer 20 or not. The
thickness of the protection layer 50 can be determined from 50 A to a few μm.
The thickness of protection layer 50 can be changed variously considering the kind and method of the latter part of process or the main purpose of the
protection layer. For example, if full-etching of the protection layer is possible,
the thickness of the protection layer can be varied from 100 A to 5 μm.
Meanwhile, when the protection layer 50 has been formed under the condition that the substrate do not emerge into the atmosphere after the crystallization and then partial or whole body of the very protection layer 50 is adopted as a gate insulating layer, the cleaning process for the interface between the poly-Si layer 40 and the protection layer (gate insulating layer) can be reduced remarkably, that is, the cleaning process for the interface between the active layer and the gate insulating layer using HF solution etc. is essential to the device characteristics for good qualities, but the excellent interface properties can be achieved by the process explained above without such cleaning process.
The transparent substrate on which the poly-Si and the protection layer are sequentially made by the process suggested above, cannot be degraded in spite of the long-term stay during the process and can possess stable properties irrelevant to the stay-time to the latter part of the process. It is effective for the stability of process.
In practice, one can provide outside or sell these substrates by the package. It is an example of the providing method of the transparent substrate. An active layer must be formed using the poly-Si layer and the protection layer so that such transparent substrate can be applied to the devices such as LCD of OLED etc. From hence, it is explained precisely the method to make the poly-Si active layer using the substrate on which the poly-Si and the protection layer are made.
(The method to make the poly-Si active layer) In the following section, it is explained in detail the method to make the poly-Si active layer using the substrate on which the poly-Si layer 40 and the protection layer 50 are made with reference to the figure 2.
At first, the protection layer 50 on the poly-Si layer 40 is etched partially or completely, that is, the protection layer 50 originally formed to protect the crystallized poly-Si layer 40 can be used as a gate insulating layer partially or
completely just as explained above. For instance, if one intends to make a
100θA-thick gate insulating layer when the 200θA-thick protection layer has
already been formed (The thickness of the gate insulating layer ranges from 50θA to 2000A and about 100θA is suitable.), one may etch the whole
protection layer and a certain portion of the poly-Si layer 40 as an active layer. Another case to make the 100θA-thick gate insulating layer is that one may
etch the protection layer partially in order to remain 50θA-thick protection layer
and then etch simultaneously the remaining protection layer 50 as well as the poly-Si layer 40 when one etch a certain portion of the poly-Si layer 40 as an
active layer.
The case explained above is only an example. Therefore, it is natural
that the protection layer 50 can be remained after the partial or complete etching of the protection layer 50 in order that the thickness of remaining protection layer must be thinner than the thickness of gate insulating layer
(Figure 2 shows the situation that the protection layer 50 is partially etched then
the remaining layer is used for the gate insulating layer). After etching the
protection layer, remaining layered structure is patterned to active part by simultaneous etching so that the upper layer of the final structure may be the protection layer 50 or poly-Si layer 40.
On the other hand, photo resist as a protection layer 50 can be used for the patterning of active layer, that is, photo lithography process using the very photo resist as protection layer 50 for the photo-sensing material can be applied directly to the patterning of active layer. The whole process can be simplified effectively using the process suggested above, that is, the gate insulating layer forming step can be followed directly by that process.
(Fabrication method for the poly-Si thin film transistor)
From now on, it is explained in detail the method to fabricate the poly-Si
TFT using the transparent substrate 10 on which the poly-Si active layer are
made with reference to the figure 3.
Once the poly-Si active layer has been formed, the whole protection
layer 50 on the poly-Si active layer survived after the protection layer etch step can be used as a gate insulating layer, or the remaining protection layer 50 and
a gate insulating layer formed additionally after the protection layer etch step can be used together as a gate insulating layer, or a gate insulating layer
formed additionally after the protection layer etch step can be used individually as a gate insulating layer, in order to make the gate insulating layer whose
thickness has been determined. For example, the general thickness of the gate-insulating layer varies from 50θA to 2000A.
In this case, the newly formed gate-insulating layer 60 may be formed by the same material as that of the protection layer 50, or not. For example, the
protection layer may be formed by Si02 and gate insulating layer 60 equally by
Si02. Alternatively, the protection layer may be formed by Si02 and gate insulating layer 60 by SiNx. It is still obvious that various combinations besides the cases mentioned above are possible.
Then, the gate electrode 70 is sputtered and patterned by photolithography after the gate-insulating layer 60. After this process, the fixed regions of the active layer are designated for the source/drain regions by doping n+ or p+ ions using the upper gate electrode 70 as a mask. The thickness of the gate electrode 70 ranges, for example, from 1500A to 4000A and about 3000A is desirable. Then, the inter-insulating layer 80)is formed on the gate electrode 70 and patterned to contact holes 90. After this process, the metal layer 100 is deposited and patterned in order to make electrical connection between the source/drain regions of the active layer and the data lines through the contacts 90. The thickness of the inter-insulating layer 80 ranges, for example, from 2000A to 8000A.
It is obvious that the N-type or P-type poly-Si TFTs can be fabricated by
the sequential processes illustrated by figure 3 and the LDD (Lightly doped
drain) structure, which is known to all, can be applied to those TFTs. Following
serial process can form the LDD structure. At first, the ion doping with low
density is performed using the gate electrode 70 mentioned above as a doping
mask, then the space or the photo resist can be formed at the both sides or one
side of the gate electrode 70 by so called 'spacer process' etc. Finally, the LDD
structure can be achieved by making source/drain regions just as explained
above through the ion doping process with high density using the space or the
photo resist mentioned above as a doping mask.
This invention can be modified variously on condition that the
modifications may not deviate from the idea and range. Therefore, the above
explanations for the practical example are merely provided for example itself
and not provided in order to confine this invention defined by the appended request-limitations and the equivalence of those.
INDUSTRIAL AVAILABILITY
As is described above, the present invention has an effect in making a crystallized poly-Si / gate insulator interface clean and have a high quality when the processing time is delayed between crystallization process and a next step or the crystallized sample has to be transferred out of clean room area.

Claims

WHAT IS CLAIMED IS:
1. A method of manufacturing and providing a poly-Si-formed transparent glass with protection layer, comprising the steps of: depositing an a-Si thin film on a transparent substrate; crystallizing the a-Si layer to form a poly-Si layer; and forming a protection film on top of the poly-Si layer.
1. The method of claim 1 , wherein an a-Si is crystallized using Solid State Crystallization, Excimer Laser Annealing, Metal Induced Crystallization or
As-deposition method.
2. The method of claim 1 , containing a consecutive process comprising the steps of; forming the a-Si thin film on a transparent glass; crystallizing the a-Si layer to form the poly-Si layer; and Forming a protection film on top of the poly-Si layer.
3. The method of claim 1 , forming an insulating layer between the transparent substrate and the a-Si thin film.
4. The method of claim 1 , containing a consecutive process comprising the steps of; forming an insulating layer on a transparent substrate; forming an a-Si thin film on an insulating layer; crystallizing an a-Si layer to form a poly-Si layer; and Forming a protection film on top of a poly-Si layer.
5. The method of claim 1 , wherein the transparent substrate is a glass, quartz, plastic or flexible substrate.
6. The method of claim 1 , wherein the protection layer is Si Oxide film,
Si Nitride film or organic film.
7. The method of claim 1 , wherein the protection layer is a photo- resistor (PR) material.
8. A method of manufacturing an active layer of thin film transistor using the method of claim 1 or claim 7, comprising the steps of; etching a part of or a full region of the protection layer; and forming an active layer using a remaining film after etching.
9. A method of forming an active layer using a transparent substrate having a poly-Si layer and photo-resistor protection layer following the method of claim 8, comprising steps of; defining an active area by UV exposure of a part of the protection layer; and
patterning the active layer using the remaining protection layer as a
mask.
10. A method of manufacturing a thin film transistor using a transparent substrate having an active layer of poly-Si following the method of the claim 9, comprising the steps of;
using the remaining protection layer after etching step as a gate insulator or forming an additional gate insulator on the remaining protection layer to have
a enough gate insulator thickness or forming a full gate insulator on the poly-Si
active layer if there remained no protection layer; forming a gate electrode on the gate insulator; defining an area of source/drain in the active layer by ion-doping the
poly-Si layer using the gate electrode as a mask; forming a inter-insulating layer on the gate electrode followed by patterning a contact; and
forming a metal layer on the inter-insulating layer and contact.
11. The method of claim 11 , wherein an additional ion-doping step is comprised to make a low-doping area between the active region and the source/drain region.
13. The method of claim 11 , wherein the gate insulator and protection layer are the same material such as Si Nitride thin film or Si Oxide thin film.
PCT/KR2003/000935 2002-05-13 2003-05-12 Method for providing transparent substrate having protection layer on crystalized polysilicon layer, method for forming polysilicon active layer thereof and method for manufacturing polysilicon tft using the same WO2003096110A1 (en)

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JPS61156106A (en) * 1984-12-28 1986-07-15 Sanyo Electric Co Ltd Substrate for liquid crystal display
JPH11298003A (en) * 1998-04-07 1999-10-29 Toshiba Corp Manufacture of active matrix substrate for liquid crystal display device and manufacture thereof
JP2001291870A (en) * 2000-04-06 2001-10-19 Sony Corp Thin film transistor and method for manufacturing the same

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JPS61156106A (en) * 1984-12-28 1986-07-15 Sanyo Electric Co Ltd Substrate for liquid crystal display
JPH11298003A (en) * 1998-04-07 1999-10-29 Toshiba Corp Manufacture of active matrix substrate for liquid crystal display device and manufacture thereof
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