CN114242666A - Semiconductor device with a plurality of semiconductor chips - Google Patents
Semiconductor device with a plurality of semiconductor chips Download PDFInfo
- Publication number
- CN114242666A CN114242666A CN202111031125.7A CN202111031125A CN114242666A CN 114242666 A CN114242666 A CN 114242666A CN 202111031125 A CN202111031125 A CN 202111031125A CN 114242666 A CN114242666 A CN 114242666A
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- Prior art keywords
- heat sink
- semiconductor device
- recess
- insulating layer
- recessed
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000011347 resin Substances 0.000 claims abstract description 41
- 229920005989 resin Polymers 0.000 claims abstract description 41
- 238000007789 sealing Methods 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 17
- 238000005516 engineering process Methods 0.000 abstract 1
- 206010040844 Skin exfoliation Diseases 0.000 description 21
- 230000000694 effects Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000002250 progressing effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000009751 slip forming Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The purpose is to provide a technology capable of suppressing the progress of peeling of the interface between a package resin and a heat sink to the interface between an insulating layer provided on the upper surface of the heat sink and the heat sink, for a semiconductor device having the heat sink. A semiconductor device (100) comprises: a heat sink (5); an insulating layer (4) disposed on the upper surface of the heat sink (5); a lead frame (1) fixed to the upper surface of the insulating layer (4); a semiconductor element (2) mounted on the upper surface of the lead frame (1); and an encapsulating resin (6) encapsulating the heat sink (5) and the semiconductor element (2) in a state in which the bottom surface (10) of the heat sink (5) is exposed. A bottom surface step portion (7) recessed in a step shape is formed on the peripheral edge portion of the bottom surface (10) of the heat sink (5), a recess portion (11) recessed upward and not exposed from the sealing resin (6) is formed on the bottom surface step portion (7), and a recess portion (12) recessed downward is formed on the upper surface of the heat sink (5).
Description
Technical Field
The present invention relates to a semiconductor device having a heat sink.
Background
There is a semiconductor device having a heat sink, a semiconductor element, and an encapsulating resin encapsulating the heat sink and the semiconductor element in a state where a bottom surface of the heat sink is exposed. In such a semiconductor device, a step portion is provided on the bottom surface of the heat sink.
For example, patent document 1 discloses a technique of preventing a heat sink from falling off from a package resin by forming a resin hook by curing the package resin that has detoured to a step portion. The resin hook is a structure in which the cured resin is hooked on the unevenness of the member like a hook to prevent the member from falling off. In general, a heat sink is formed using a material having good heat dissipation properties, such as Al or Cu.
Patent document 1: japanese patent laid-open publication No. 2003-7933
However, in the conventional semiconductor device, when thermal stress or the like is applied to a corner portion of the stepped portion provided on the bottom surface of the heat sink, stress tends to concentrate, and the stress tends to become a starting point of peeling of the interface between the sealing resin and the heat sink. When peeling progresses along the side surface of the heat sink toward the interface between the insulating layer provided on the upper surface of the heat sink and the heat sink, there is a problem that the insulating property of the semiconductor device deteriorates.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a technique for suppressing the progress of the peeling of the interface between the encapsulating resin and the heat sink toward the interface between the insulating layer provided on the upper surface of the heat sink and the heat sink in a semiconductor device having the heat sink.
The semiconductor device according to the present invention includes: a heat sink; an insulating layer disposed on an upper surface of the heat sink; a lead frame fixed to an upper surface of the insulating layer; a semiconductor element mounted on an upper surface of the lead frame; and a sealing resin for sealing the heat sink and the semiconductor element in a state where a bottom surface of the heat sink is exposed, wherein a bottom surface stepped portion recessed in a step shape is formed in a peripheral portion of the bottom surface of the heat sink, a 1 st recessed portion recessed upward and not exposed from the sealing resin is formed in the bottom surface stepped portion, and a 2 nd recessed portion recessed downward is formed in an upper surface of the heat sink.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, the package resin filled in the 1 st recess can suppress excessive warping of the heat sink at high temperatures, and therefore, the peeling of the interface between the package resin and the heat sink can be suppressed from progressing from the corner of the bottom surface stepped portion. Even when the peeling of the interface between the sealing resin and the heat sink progresses, the peeling of the interface between the sealing resin and the heat sink can be suppressed from progressing to the interface between the insulating layer and the heat sink by the 2 nd recessed portion.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device according to embodiment 1.
Fig. 2 is a bottom view of a heat sink included in the semiconductor device according to embodiment 1.
Fig. 3 is a bottom view of a heat sink included in the semiconductor device according to embodiment 2.
Fig. 4 is a bottom view of a heat sink included in the semiconductor device according to modification 1 of embodiment 2.
Fig. 5 is a bottom view of a heat sink included in the semiconductor device according to modification 2 of embodiment 2.
Fig. 6 is an enlarged cross-sectional view of the semiconductor device according to embodiment 3.
Fig. 7 is a cross-sectional view showing warpage of the semiconductor device in a case where no recess is formed in the bottom surface step portion.
Detailed Description
< embodiment 1 >
Hereinafter, embodiment 1 will be described with reference to the drawings. Fig. 1 is a cross-sectional view of a semiconductor device 100 according to embodiment 1. Fig. 2 is a bottom view of heat sink 5 included in semiconductor device 100.
As shown in fig. 1, the semiconductor device 100 has a heat spreader 5, an insulating layer 4, an encapsulating resin 6, a plurality of lead frames 1, and a plurality of semiconductor elements 2.
The heat sink 5 is formed using a material having good heat dissipation properties, such as Al or Cu. The insulating layer 4 is provided on the entire upper surface of the heat spreader 5. The lead frame 1 is fixed to the upper surface of the insulating layer 4. The semiconductor element 2 is fixed to the upper surface of the lead frame 1 using a bonding material 3 such as solder. In addition, the semiconductor element 2 is connected to the lead frame 1 or another semiconductor element 2 using the metal wire 14.
The sealing resin 6 seals the heat sink 5 and the semiconductor element 2 in a state where the bottom surface 10 of the heat sink 5 is exposed. The insulating layer 4 and the sealing resin 6 are made of a resin having good insulating properties such as an epoxy resin or a phenol resin and an additive.
Next, the structure of the heat sink 5 will be explained. As shown in fig. 1 and 2, a bottom surface stepped portion 7 recessed in a stepped shape is continuously formed along a peripheral edge portion of a bottom surface 10 of the heat sink 5. A groove-like recess 11, which is a 1 st recess recessed upward, is continuously formed along the outer peripheral portion of the bottom surface stepped portion 7.
The recess 11 is filled with the sealing resin 6, and the recess 11 is not exposed from the sealing resin 6. By forming the recess 11 on the outer periphery of the bottom stepped portion 7, that is, on the periphery of the corner of the bottom stepped portion 7, the sealing resin 6 filled in the recess 11 can suppress excessive warping of the heat sink 5 at high temperatures. This can suppress the progress of the peeling at the interface between the sealing resin 6 and the heat sink 5.
The recess 11 is formed by press working. When the concave portion 11 is formed by press working, the outer peripheral portion of the bottom surface step portion 7 is press-worked, whereby the portion around the portion of the side surface 9 where the press-working is performed is plastically deformed and is deformed so as to expand. When the side surface 9 is smooth, the peeling generated at the corner of the bottom surface stepped portion 7 tends to progress along the smooth side surface 9, but in embodiment 1, the shape of the side surface 9 is distorted, and thus it becomes difficult to progress.
On the upper surface of the heat sink 5, a groove-like recess 12 as a 2 nd recess recessed downward is continuously formed along the outer peripheral portion of the upper surface. The portion of the insulating layer 4 facing the recess 12 is formed in a convex shape protruding downward so as to correspond to the recess 12. By forming the recess 12 on the upper surface of the heat sink 5, when the peeling of the interface between the sealing resin 6 and the heat sink 5 progresses, the progress toward the insulating layer 4 can be suppressed. That is, the progress of the peeling of the interface between the sealing resin 6 and the heat sink 5 toward the insulating layer 4 can be suppressed before the peeling of the interface between the sealing resin 6 and the heat sink 5 progresses along the side surface 9 of the heat sink 5 and further continues to the peeling of the interface between the insulating layer 4 and the heat sink 5.
The recess 12 may not be continuous, but may be formed discontinuously in plural. Further, the concave portion 12 is not formed in the central portion of the upper surface of the heat sink 5, but is formed in the outer peripheral portion, and has a great effect of suppressing the progress of the peeling.
Next, the operation and effect of the semiconductor device 100 will be described in comparison with the case where the recess 11 is not formed in the bottom surface step portion 7. Fig. 7 is a cross-sectional view showing warpage of the semiconductor device 101 in a case where the recess 11 is not formed in the bottom surface step portion 7.
Generally, the heat sink 5 has a coefficient of linear thermal expansion larger than that of the encapsulating resin 6, and at a high temperature, the entire semiconductor device 101 is warped so that the bottom surface 10 of the heat sink 5 is convex as shown in fig. 7.
In contrast, the semiconductor device 100 according to embodiment 1 includes: a heat sink 5; an insulating layer 4 provided on an upper surface of the heat sink 5; a lead frame 1 fixed to an upper surface of the insulating layer 4; a semiconductor element 2 mounted on an upper surface of the lead frame 1; and a sealing resin 6 for sealing the heat sink 5 and the semiconductor element 2 in a state where the bottom surface 10 of the heat sink 5 is exposed, wherein a bottom surface stepped portion 7 recessed in a step shape is formed on a peripheral edge portion of the bottom surface 10 of the heat sink 5, a recessed portion 11 recessed upward and not exposed from the sealing resin 6 is formed on the bottom surface stepped portion 7, and a recessed portion 12 recessed downward is formed on an upper surface of the heat sink 5.
Therefore, at high temperatures, the sealing resin 6 filled in the concave portion 11 can suppress excessive warpage of the heat sink 5, and therefore, the peeling of the interface between the sealing resin 6 and the heat sink 5 can be suppressed from progressing from the corner of the bottom surface stepped portion 7. Even when the peeling of the interface between the sealing resin 6 and the heat sink 5 progresses, the peeling of the interface between the sealing resin 6 and the heat sink 5 can be suppressed from progressing to the interface between the insulating layer 4 and the heat sink 5 by the concave portion 12. This enables long-term use of the semiconductor device 100.
Further, since the recess 12 is formed in the outer peripheral portion of the upper surface of the heat sink 5, the effect of suppressing the progress of the peeling increases.
Further, since the recess 11 is formed along the outer peripheral portion of the bottom surface stepped portion 7, the occurrence of peeling of the entire outer peripheral portion of the bottom surface stepped portion 7 can be suppressed.
< embodiment 2 >
Next, the semiconductor device 100 according to embodiment 2 will be described. Fig. 3 is a bottom view of heat sink 5 included in semiconductor device 100 according to embodiment 2. Fig. 4 is a bottom view of heat sink 5 included in semiconductor device 100 according to modification 1 of embodiment 2. Fig. 5 is a bottom view of heat sink 5 included in semiconductor device 100 according to modification 2 of embodiment 2. In embodiment 2, the same components as those described in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.
As shown in fig. 3, in embodiment 2, the concave portions 11 are discontinuously formed. Specifically, the groove-like recess 11 is formed only at the 4 corners of the bottom surface step portion 7.
As shown in fig. 4, the recessed portion 11 may be formed in a circular shape in a bottom view, and a plurality of recessed portions may be formed at intervals along the outer peripheral portion of the bottom surface stepped portion 7.
As shown in fig. 5, the circular recesses 11 may be provided only at 4 corners of the bottom surface stepped portion 7.
As described above, in embodiment 2, since the concave portions 11 are formed discontinuously, an effect of suppressing the development of peeling can be obtained, and the processing efficiency when forming the concave portions 11 can be improved as compared with the case of embodiment 1.
< embodiment 3 >
Next, the semiconductor device 100 according to embodiment 3 will be described. Fig. 6 is an enlarged cross-sectional view of the semiconductor device 100 according to embodiment 3. In embodiment 3, the same components as those described in embodiments 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
As shown in fig. 6, in embodiment 3, the recess 11 is not formed in the bottom surface step portion 7, and instead, the recess 13 is formed in the side surface 9 of the heat sink 5. The concave portion 13 is formed along the circumferential direction of the side surface 9 so as to be recessed toward the inner circumferential side of the side surface 9, and is not exposed from the sealing resin 6.
As described above, in embodiment 3, since the recess 13 is formed in the side surface 9 of the heat sink 5, it is possible to suppress the development of the separation from the corner of the bottom surface step portion 7 along the side surface 9. This can suppress the progress of peeling toward the interface between the insulating layer 4 and the heat sink 5.
In embodiment 3, the recess 12 may be provided on the upper surface of the heat sink 5. This can suppress the progress of peeling toward the interface between the insulating layer 4 and the heat sink 5, as compared with the case where the recess 12 is not provided.
Further, the respective embodiments may be freely combined, or may be appropriately modified or omitted.
Description of the reference numerals
1 lead frame, 2 semiconductor element, 4 insulating layer, 5 heat spreader, 6 encapsulating resin, 7 bottom surface step, 11 recess, 12 recess, 13 recess, 100 semiconductor device.
Claims (5)
1. A semiconductor device, comprising:
a heat sink;
an insulating layer disposed on an upper surface of the heat sink;
a lead frame fixed to an upper surface of the insulating layer;
a semiconductor element mounted on an upper surface of the lead frame; and
an encapsulating resin encapsulating the heat spreader and the semiconductor element in a state where a bottom surface of the heat spreader is exposed,
a bottom surface step portion recessed in a step shape is formed on a peripheral edge portion of a bottom surface of the heat sink,
a 1 st recess which is recessed upward and is not exposed from the sealing resin is formed on the bottom surface step part,
a 2 nd recess recessed downward is formed in an upper surface of the heat sink.
2. The semiconductor device according to claim 1,
the 2 nd recess is formed in an outer peripheral portion of an upper surface of the heat sink.
3. The semiconductor device according to claim 1 or 2,
the 1 st recess is formed along an outer peripheral portion of the bottom surface step portion.
4. The semiconductor device according to claim 3,
the 1 st recess is discontinuously formed.
5. A semiconductor device, comprising:
a heat sink;
an insulating layer disposed on an upper surface of the heat sink;
a lead frame fixed to an upper surface of the insulating layer;
a semiconductor element mounted on an upper surface of the lead frame; and
an encapsulating resin encapsulating the heat spreader and the semiconductor element in a state where a bottom surface of the heat spreader is exposed,
a bottom surface step portion recessed in a step shape is formed on a peripheral edge portion of a bottom surface of the heat sink,
a concave portion is formed on a side surface of the heat sink so as to be recessed toward an inner peripheral side and not to be exposed from the sealing resin.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020151004A JP7407679B2 (en) | 2020-09-09 | 2020-09-09 | semiconductor equipment |
| JP2020-151004 | 2020-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114242666A true CN114242666A (en) | 2022-03-25 |
Family
ID=80266859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111031125.7A Pending CN114242666A (en) | 2020-09-09 | 2021-09-03 | Semiconductor device with a plurality of semiconductor chips |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP7407679B2 (en) |
| CN (1) | CN114242666A (en) |
| DE (1) | DE102021120264A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008311366A (en) * | 2007-06-13 | 2008-12-25 | Denso Corp | Resin-sealed semiconductor device |
| JP2011258814A (en) * | 2010-06-10 | 2011-12-22 | Toyota Motor Corp | Semiconductor device cooler |
| CN102347291A (en) * | 2010-07-30 | 2012-02-08 | 安森美半导体贸易公司 | Semiconductor device and method of manufacturing same |
| US20140332951A1 (en) * | 2012-02-09 | 2014-11-13 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN107634036A (en) * | 2016-07-19 | 2018-01-26 | 三菱电机株式会社 | Semiconductor device |
| CN110392924A (en) * | 2017-02-21 | 2019-10-29 | 三菱电机株式会社 | Semiconductor device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041902A (en) | 1989-12-14 | 1991-08-20 | Motorola, Inc. | Molded electronic package with compression structures |
| JP2540478B2 (en) * | 1993-11-04 | 1996-10-02 | 株式会社後藤製作所 | Heat sink for semiconductor device and manufacturing method thereof |
| EP0758488A1 (en) | 1995-03-06 | 1997-02-19 | National Semiconductor Corporation | Heat sink for integrated circuit packages |
| US6159764A (en) | 1997-07-02 | 2000-12-12 | Micron Technology, Inc. | Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages |
| JP2001035985A (en) | 1999-07-19 | 2001-02-09 | Denso Corp | Semiconductor device sealed with resin |
| TW200812023A (en) | 2006-08-22 | 2008-03-01 | Advanced Semiconductor Eng | Heat slug for package structure |
| JP5153684B2 (en) | 2009-02-27 | 2013-02-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| WO2013125474A1 (en) | 2012-02-24 | 2013-08-29 | 三菱電機株式会社 | Semiconductor device and method for manufaturing same |
| DE112012006656B4 (en) | 2012-07-05 | 2021-08-05 | Mitsubishi Electric Corporation | Semiconductor device |
-
2020
- 2020-09-09 JP JP2020151004A patent/JP7407679B2/en active Active
-
2021
- 2021-08-04 DE DE102021120264.7A patent/DE102021120264A1/en active Granted
- 2021-09-03 CN CN202111031125.7A patent/CN114242666A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008311366A (en) * | 2007-06-13 | 2008-12-25 | Denso Corp | Resin-sealed semiconductor device |
| JP2011258814A (en) * | 2010-06-10 | 2011-12-22 | Toyota Motor Corp | Semiconductor device cooler |
| CN102347291A (en) * | 2010-07-30 | 2012-02-08 | 安森美半导体贸易公司 | Semiconductor device and method of manufacturing same |
| US20140332951A1 (en) * | 2012-02-09 | 2014-11-13 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN107634036A (en) * | 2016-07-19 | 2018-01-26 | 三菱电机株式会社 | Semiconductor device |
| CN110392924A (en) * | 2017-02-21 | 2019-10-29 | 三菱电机株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7407679B2 (en) | 2024-01-04 |
| DE102021120264A1 (en) | 2022-03-10 |
| JP2022045413A (en) | 2022-03-22 |
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