CN114242134A

CN114242134A - SRAM memory, write-in sub-circuit, read-out sub-circuit and control method thereof

Info

Publication number: CN114242134A
Application number: CN202111556564.XA
Authority: CN
Inventors: 唐永生; 黄立; 申石林; 刘阿强
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-03-25

Abstract

The application provides an SRAM memory, a writing sub-circuit, a reading sub-circuit and a control method thereof, relates to the technical field of semiconductors, and can save the internal space of electronic equipment and reduce the power consumption of the electronic equipment to the greatest extent. The SRAM memory includes: a write sub-circuit, a memory sub-circuit, and a read sub-circuit; the write sub-circuit is configured to output the input signal from the first output signal terminal and output the inverted input signal from the second output signal terminal. The storage sub-circuit is configured to store the first output signal and the second output signal. The readout sub-circuit is configured to pull up potentials of the third output signal terminal and the fourth output signal terminal to the first power supply voltage signal, and output signals of different potentials from the third output signal terminal and the fourth output signal terminal.

Description

SRAM memory, write-in sub-circuit, read-out sub-circuit and control method thereof

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to an SRAM memory, and a write sub-circuit, a read sub-circuit, and a control method thereof.

Background

Static Random Access Memory (SRAM) is a memory device with static access function, which can store the data stored therein without a refresh circuit, has the advantages of high speed, low power consumption, compatibility with standard processes, and the like, and is widely applied to various electronic devices such as computers, personal communications, consumer electronics (smart cards, digital cameras, multimedia players), and the like. With the development of various electronic devices toward light weight, thinness and low power consumption, various circuit structures located inside the electronic devices also need to be developed toward small area and low power consumption, so as to be better adapted to various future electronic devices.

Disclosure of Invention

The embodiment of the invention provides an SRAM, a read-write circuit of the SRAM, a write-in sub-circuit of the SRAM, a read-out sub-circuit of the SRAM, a control method of the SRAM, a processing circuit chip and electronic equipment.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, the present invention provides a write sub-circuit of an SRAM memory, including: the device comprises an input signal end, a selection signal end, a first enable signal end, a first output signal end and a second output signal end; and is configured to output an input signal provided by the input signal terminal from the first output signal terminal and output the inverted input signal from the second output signal terminal under the control of the selection signal terminal and the first enable signal terminal.

In some embodiments, the write subcircuit of the SRAM memory further comprises: the first diode and the second diode are configured to stabilize the transmission of the input signal to the first output signal terminal and the second output signal terminal under the control of the first supply voltage signal terminal.

In some embodiments, the write subcircuit of the SRAM memory further comprises: a reset signal terminal; and is further configured to reset the first output signal terminal and the second output signal terminal under control of the reset signal terminal and the first power supply voltage signal terminal.

In some embodiments, the write subcircuit of the SRAM memory further comprises: the transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter.

A gate of the first transistor is coupled to the first enable signal terminal, a first pole of the first transistor is coupled to the input signal terminal, and a second pole of the first transistor is coupled to the first pole of the third transistor;

the gate of the second transistor is coupled to the first enable signal terminal, the first pole is coupled to the output terminal of the inverter, and the second pole is coupled to the first pole of the fourth transistor.

The grid electrode of the third transistor is coupled with the selection signal terminal, and the second pole is coupled with the first output signal terminal.

The gate of the fourth transistor is coupled to the selection signal terminal, and the second pole is coupled to the second output signal terminal.

The input end of the phase inverter is coupled with the input signal end.

In some embodiments, in a case where the write sub-circuit includes a first power supply voltage signal terminal, a first diode, and a second diode, an input terminal of the first diode is coupled to the second terminal of the first transistor, and an output terminal thereof is coupled to the first power supply voltage signal terminal; an input end of the second diode is coupled to the second electrode of the second transistor, and an output end of the second diode is coupled to the first power voltage signal end.

In some embodiments, the write subcircuit includes a fifth transistor and a sixth transistor.

A gate of the fifth transistor is coupled to the reset signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the first output signal terminal.

A gate of the sixth transistor is coupled to the reset signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the second output signal terminal.

In another aspect, the present invention provides a readout sub-circuit of an SRAM memory, comprising: a first power supply voltage signal end, a second enable signal end, a second gate drive signal end, a third output signal end and a fourth output signal end; is configured to pull up potentials of the third and fourth output signal terminals to a first power supply voltage signal provided from the first power supply voltage signal terminal under control of the first and second power supply voltage signal terminals, and to output signals of different potentials from the third and fourth output signal terminals under control of the second, third, second and second power supply voltage signal terminals.

In some embodiments, the read-out subcircuit of the SRAM memory further comprises: a data latch unit configured to latch signals output from the third and fourth output signal terminals.

In some embodiments, the read-out subcircuit of the SRAM memory further comprises: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor.

A gate of the thirteenth transistor is coupled to the second gate driving signal terminal, a first pole of the thirteenth transistor is coupled to a second pole of the seventeenth transistor, and a second pole of the thirteenth transistor is coupled to the fourth output signal terminal.

A gate of the fourteenth transistor is coupled to the third gate driving signal terminal, a first pole of the fourteenth transistor is coupled to a second pole of the seventeenth transistor, and a second pole of the fourteenth transistor is coupled to the third output signal terminal.

A gate of the fifteenth transistor is coupled to the second enable signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the fourth output signal terminal.

A gate of the sixteenth transistor is coupled to the second enable signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the third output signal terminal.

A gate of the seventeenth transistor is coupled to the second enable signal terminal, and a first pole of the seventeenth transistor is coupled to the second power voltage signal terminal.

In yet another aspect, an SRAM memory is provided, comprising: a write sub-circuit, a memory sub-circuit, and a read sub-circuit.

The write-in sub-circuit is provided with a first node and a second node, is coupled with an input signal terminal, a selection signal terminal, a first enable signal terminal, a first output signal terminal and a second output signal terminal, and is configured to output an input signal provided by the input signal terminal from the first output signal terminal and output an inverted input signal from the second output signal terminal under the control of the selection signal terminal and the first enable signal terminal; the input signal is transmitted to the first output signal end through the first node, and the inverted input signal is transmitted to the second output signal end through the second node.

The storage sub-circuit is coupled to the first output signal terminal, the second output signal terminal, the first power voltage signal terminal, the second power voltage signal terminal, and the first gate driving signal terminal, and configured to store a first output signal provided by the first output signal terminal and a second output signal provided by the second output signal terminal under the control of the first power voltage signal terminal, the second power voltage signal terminal, and the first gate driving signal terminal.

A readout sub-circuit coupled to the first power supply voltage signal terminal, the second power supply voltage signal terminal, a second enable signal terminal, a second gate drive signal terminal, a third output signal terminal, and a fourth output signal terminal, configured to pull up potentials of the third output signal terminal and the fourth output signal terminal to a first power supply voltage signal provided by the first power supply voltage signal terminal under control of the first power supply voltage signal terminal and the second enable signal terminal, and to output signals of different potentials from the third output signal terminal and the fourth output signal terminal under control of the second gate drive signal terminal, the third gate drive signal terminal, the second enable signal terminal, and the second power supply voltage signal terminal, wherein a second gate drive signal provided by the second gate drive signal terminal is generated from the first output signal stored by the storage sub-circuit, the third gate driving signal provided by the third gate driving signal terminal is generated by the second output signal stored by the storage sub-circuit.

In some embodiments, the second gate driving signal terminal is coupled to the first node, and the third gate driving signal terminal is coupled to the second node.

In some embodiments, the write subcircuit includes: the transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter.

The gate of the first transistor is coupled to the first enable signal terminal, the first pole is coupled to the input signal terminal, and the second pole is coupled to the first node.

The gate of the second transistor is coupled to the first enable signal terminal, the first pole is coupled to the output terminal of the inverter, and the second pole is coupled to the second node.

The gate of the third transistor is coupled to the selection signal terminal, the first pole is coupled to the first node, and the second pole is coupled to the first output signal terminal.

The gate of the fourth transistor is coupled to the selection signal terminal, the first pole is coupled to the second node, and the second pole is coupled to the second output signal terminal.

The input end of the phase inverter is coupled with the input signal end.

On this basis, in some embodiments, the storage sub-circuit comprises: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor.

The gate of the seventh transistor is coupled to the first control node, the first pole is coupled to the second power voltage signal terminal, and the second pole is coupled to the second control node.

A gate of the eighth transistor is coupled to the first control node, a first pole of the eighth transistor is coupled to the first power voltage signal terminal, and a second pole of the eighth transistor is coupled to the second control node.

A gate of the ninth transistor is coupled to the second control node, a first pole of the ninth transistor is coupled to the second power voltage signal terminal, and a second pole of the ninth transistor is coupled to the first control node.

A gate of the tenth transistor is coupled to the second control node, a first pole of the tenth transistor is coupled to the first power voltage signal terminal, and a second pole of the tenth transistor is coupled to the first control node.

A gate of the eleventh transistor is coupled to the first gate driving signal terminal, a first pole is coupled to the second output signal terminal, and a second pole is coupled to the second control node.

A gate of the twelfth transistor is coupled to the first gate driving signal terminal, a first pole of the twelfth transistor is coupled to the first output signal terminal, and a second pole of the twelfth transistor is coupled to the first control node.

On this basis, in some embodiments, the readout subcircuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor.

In other embodiments, the write subcircuit includes: the transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter.

The input end of the phase inverter is coupled with the input signal end.

The memory sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor.

The readout sub-circuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor.

The gate of the eighteenth transistor is coupled to the selection signal terminal, the first pole is coupled to the first output signal terminal, and the second pole is coupled to the second gate driving signal terminal.

The gate of the nineteenth transistor is coupled to the selection signal terminal, the first pole is coupled to the second output signal terminal, and the second pole is coupled to the third gate driving signal terminal.

In yet another aspect, the present invention provides a read/write circuit for an SRAM memory, comprising a write sub-circuit and a read sub-circuit.

The write subcircuit includes: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first diode, a second diode, a phase inverter, an input signal end, a first enable signal end, a selection signal end, a first power supply voltage signal end, a reset signal end, a first output signal end and a second output signal end.

The input end of the first diode is coupled with the first node, and the output end of the first diode is coupled with the first power supply voltage signal end; the input end of the second diode is coupled with the second node, and the output end of the second diode is coupled with the first power voltage signal end.

The input end of the phase inverter is coupled with the input signal end.

The reading sub-circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second enable signal end, a second grid driving signal end, a third grid driving signal end, a first power voltage signal end, a second power voltage signal end, a third output signal end and a fourth output signal end.

The second gate driving signal terminal is coupled to the first node, and the third gate driving signal terminal is coupled to the second node.

In yet another aspect, the present invention also provides a processing circuit chip, including the SRAM memory and at least one processing circuit as described above; the SRAM memory is used for storing data required by the at least one processing circuit during operation.

In still another aspect, the present invention further provides an electronic device, including the processing circuit chip as described above and a power supply, where the power supply is configured to provide power to the processing circuit chip.

In another aspect, the present invention further provides a method for controlling an SRAM memory, including:

the write-in sub-circuit outputs an input signal provided by an input signal end from a first output signal end and outputs the inverted input signal from a second output signal end under the control of a selection signal end and a first enable signal end.

The storage sub-circuit stores a first output signal provided by the first output signal terminal and a second output signal provided by the second output signal terminal under the control of a first power supply voltage signal terminal, a second power supply voltage signal terminal and a first gate drive signal terminal.

The reading sub-circuit pulls up the electric potentials of a third output signal terminal and a fourth output signal terminal to a first power supply voltage signal provided by the first power supply voltage signal terminal under the control of the first power supply voltage signal terminal and a second enable signal terminal, and outputs signals with different electric potentials from the third output signal terminal and the fourth output signal terminal under the control of a second gate driving signal terminal, a third gate driving signal terminal, a second enable signal terminal and a second power supply voltage signal terminal, wherein the second gate driving signal provided by the second gate driving signal terminal is generated by the first output signal stored by the storage sub-circuit, and the third gate driving signal provided by the third gate driving signal terminal is generated by the second output signal stored by the storage sub-circuit.

In some embodiments, the write sub-circuit has a first node through which the input signal is transmitted to a first output signal terminal and a second node through which the inverted input signal is transmitted to a second output signal terminal.

The readout sub-circuit outputs signals of different potentials from the third output signal terminal and the fourth output signal terminal under the control of the first node, the second gate drive signal terminal, the third gate drive signal terminal, the second enable signal terminal, and the second power supply voltage signal terminal.

The embodiment of the invention provides a writing sub-circuit of an SRAM (static random access memory), a reading sub-circuit of the SRAM, a reading and writing circuit of the SRAM, a control method of the SRAM, a processing circuit chip and electronic equipment. The SRAM memory, the read-write circuit, the write-in sub-circuit, the read-out sub-circuit and the like have simple structures, small areas and low power consumption, can save the internal space of the electronic equipment to the greatest extent, reduce the power consumption of the electronic equipment, reduce the production cost of the SRAM memory and further facilitate the reduction of the production cost of the processing circuit chip and the electronic equipment.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1a is a schematic structural diagram of an SRAM memory according to an embodiment of the present invention;

FIG. 1b is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 1c is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 1d is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 1e is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 1f is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 1g is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 2a is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 2b is a schematic structural diagram of a data latch unit according to an embodiment of the present invention;

fig. 2c is a schematic structural diagram of a first RS flip-flop and a second flip-flop according to an embodiment of the present invention;

FIG. 3a is a schematic diagram of a write sub-circuit according to an embodiment of the present invention;

FIG. 3b is a schematic diagram of another write sub-circuit according to an embodiment of the present invention;

FIG. 3c is a schematic diagram of a write sub-circuit according to another embodiment of the present invention;

FIG. 3d is a schematic diagram of a write sub-circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a memory sub-circuit according to an embodiment of the present invention;

FIG. 5a is a schematic diagram of a readout sub-circuit according to an embodiment of the present invention;

FIG. 5b is a schematic diagram of a circuit structure of an SRAM memory according to an embodiment of the present invention;

FIG. 6a is a schematic circuit diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 6b is a schematic circuit diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 6c is a schematic circuit diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 6d is a schematic circuit diagram of another SRAM memory according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a readout sub-circuit according to another embodiment of the present invention;

FIG. 8a is a flowchart illustrating a control method for an SRAM memory according to an embodiment of the present invention;

FIG. 8b is a flow chart illustrating another SRAM memory control method according to an embodiment of the present invention;

FIG. 9a is a timing diagram of a related art SRAM memory in a data writing phase;

FIG. 9b is a timing diagram of the SRAM memory in the related art during a data reading phase;

FIG. 10 is a timing diagram of an SRAM memory according to an embodiment of the present invention;

FIG. 11a is a schematic structural diagram of another SRAM memory according to an embodiment of the present invention;

fig. 11b is a schematic structural diagram of a logic controller according to an embodiment of the present invention.

Reference numerals: 1-SRAM memory; 10-a read-write circuit; 11-a write sub-circuit; 110-a multiplexing unit; 111-inverter; 12-a storage sub-circuit; 12' -an array of memory sub-circuits; 13-a readout sub-circuit; 131-a data latch unit; 1311-first RS flip-flop; 1312-a second RS flip-flop; 1313-a first nand gate; 1314-a second nand gate; 14-a logic controller; 141-a first delay module; 142-a second delay module; 143-a third delay block; 144-a reset time generation module; 145-write time generation module; 146-a readout time generation module; 15-row decoder;

din-input signal terminal; sel-select signal terminal; we-first enable signal terminal; BL-first output signal terminal; NBL-second output signal terminal; VDD — a first power supply voltage signal terminal; vss-second supply voltage signal terminal; WL-first gate drive signal terminal; n1-first node; n2-second node; n3-third node; n4-fourth node; s1 — a first control node; s2 — a second control node; lat-second enable signal terminal; g2 — second gate drive signal terminal; g3 — third gate drive signal terminal; out-a third output signal terminal; outn-fourth output signal terminal; d0-fifth output signal terminal; d-a sixth output signal terminal; rstn-reset signal terminal; d1 — first diode; d2 — second diode; d3 — third diode; d4 — fourth diode; ADR-address signal; CLK-clock signal.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Low power consumption and light weight are the development directions pursued by many portable electronic devices, such as notebook computers, and in order to reduce the volume and power consumption of the electronic devices, higher design requirements are provided for various circuit structures supporting the electronic devices, and how to design a circuit with a simpler structure and lower power consumption is a problem that needs to be solved urgently by technical personnel in the field.

An embodiment of the present invention provides an electronic device including a processing circuit chip and a power supply for supplying power to the processing circuit chip.

The power source may be provided by, for example, a lithium battery, but is not limited thereto.

The processing circuit chip comprises, for example, an SRAM memory 1 and at least one processing circuit, and the SRAM memory 1 is used to store data required by the operation of the at least one processing circuit.

The at least one processing circuit may be, for example, a core (e.g., an ARM core), or a hardware circuit implemented based on an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. For example, the processing circuit chip may be an Application Processor (AP) in a communication device (such as a mobile phone, a tablet computer, a personal computer, and the like), or may be an accelerator in a neural network.

It should be understood that the processing circuit chip provided in the embodiments of the present application may also have other structures, such as an input/output interface, etc., which are known in the processor.

Referring to fig. 1a to 1g, the SRAM memory 1 described above includes: a write sub-circuit 11, a memory sub-circuit 12 and a read sub-circuit 13.

The write sub-circuit 11 has a first node N1 and a second node N2. The write sub-circuit 11 is coupled to the input signal terminal Din, the selection signal terminal Sel, the first enable signal terminal We, the first output signal terminal BL, and the second output signal terminal NBL. The write sub-circuit 11 is configured to output the input signal Din provided from the input signal terminal Din from the first output signal terminal BL and output the inverted input signal Din from the second output signal terminal NBL under the control of the selection signal terminal Sel and the first enable signal terminal We.

As can be seen from the above, the first output signal BL and the second output signal NBL are inverted signals, and have a phase difference of 180 °.

The input signal Din is transmitted to the first output signal terminal BL through the first node N1, and the inverted input signal Din is transmitted to the second output signal terminal NBL through the second node N2. It is understood that the first node N1 is located on a path along which the input signal Din is transmitted to the first output signal terminal BL, and the second node N2 is located on a path along which the inverted input signal Din is transmitted to the second output signal terminal NBL.

The memory sub-circuit 12 is coupled to a first output signal terminal BL, a second output signal terminal NBL, a first power voltage signal terminal VDD, a second power voltage signal terminal Vss, and a first gate driving signal terminal WL. The memory sub-circuit 12 is configured to store a first output signal BL provided from the first output signal terminal BL and a second output signal NBL provided from the second output signal terminal NBL under the control of the first power supply voltage signal terminal VDD, the second power supply voltage signal terminal Vss, and the first gate driving signal terminal WL.

The readout sub-circuit 13 is coupled to a first power supply voltage signal terminal VDD, a second power supply voltage signal terminal Vss, a second enable signal terminal Lat, a second gate driving signal terminal G2, a third gate driving signal terminal G3, a third output signal terminal Out, and a fourth output signal terminal Outn. The readout sub-circuit 13 is configured to pull up the potentials of the third output signal terminal Out and the fourth output signal terminal Outn to the first power supply voltage signal VDD provided by the first power supply voltage signal terminal VDD under the control of the first power supply voltage signal terminal VDD and the second enable signal terminal Lat, which may be understood as performing a reset operation on the third output signal terminal Out and the fourth output signal terminal Outn, that is, setting the potentials of the third output signal terminal Out and the fourth output signal terminal Outn to 1.

The readout sub-circuit 13 is also configured to output signals of different potentials from the third output signal terminal Out and the fourth output signal terminal Outn under the control of the second gate drive signal terminal G2, the third gate drive signal terminal G3, the second enable signal terminal Lat, and the second power supply voltage signal terminal Vss. For example, the third output signal Out is high when output from the third output signal terminal Out, and the fourth output signal Outn is low when output from the fourth output signal terminal Outn, or vice versa.

The second gate driving signal G2 provided by the second gate driving signal terminal G2 is generated by the first output signal BL stored in the storage sub-circuit 12, the third gate driving signal G3 provided by the third gate driving signal terminal G3 is generated by the second output signal NBL stored in the storage sub-circuit 12, that is, the second gate driving signal G2 provided by the second gate driving signal terminal G2 is the same as the first output signal BL, and the third gate driving signal G3 provided by the third gate driving signal terminal G3 is the same as the second output signal NBL. The second gate driving signal G2 can be realized by directly coupling the second gate driving signal terminal G2 with the first output signal terminal BL, or by indirectly coupling, for example, by transmitting the first output signal BL to the second gate driving signal terminal G2 through other elements, such as a field effect transistor, which is used in this application; the same principle of the third gate driving signal G3 and the second output signal NBL is completely the same as the same principle of the second gate driving signal G2 and the first output signal BL, and thus the description thereof is omitted.

Illustratively, the SRAM memory 1 in the embodiment of the present invention includes a write sub-circuit 11, a storage sub-circuit 12, and a read sub-circuit 13.

Illustratively, the SRAM memory 1 in the embodiment of the present invention includes one write sub-circuit 11, a plurality of storage sub-circuits 12, and one read sub-circuit 13. Illustratively, the number of memory sub-circuits 12 is 16.

As another example, the SRAM memory 1 in the embodiment of the present invention includes a plurality of write sub-circuits 11, a plurality of memory sub-circuits 12, and a plurality of read sub-circuits 13. The plurality of write sub-circuits 11 and the plurality of read sub-circuits 13 correspond to each other one by one, and the plurality of write sub-circuits 11 may or may not correspond to the plurality of storage sub-circuits 12 one by one, which is not limited in the present invention.

When the SRAM memory 1 includes a plurality of storage sub-circuits 12, the plurality of storage sub-circuits 12 are distributed in the form of an array.

The embodiment of the invention provides an SRAM memory 1, wherein the SRAM memory 1 comprises: a write sub-circuit 11, a memory sub-circuit 12 and a read sub-circuit 13. The write sub-circuit 11 and the read sub-circuit 13 are coupled to fewer signal terminals, so that the SRAM memory 1 can implement data writing, storing, and reading. Therefore, the SRAM memory 1 in the embodiment of the present invention has a simple structure, a small area, and low power consumption, and can save the internal space of the electronic device and reduce the power consumption of the electronic device to the greatest extent, reduce the production cost of the SRAM memory 1, and further contribute to reducing the production costs of the processing circuit chip and the electronic device.

In some embodiments, referring to fig. 1b and 1e, the write sub-circuit 11 includes a first diode and a second diode, and the write sub-circuit 11 is further coupled to the first power supply voltage signal terminal VDD, and the first diode and the second diode are configured to stabilize the transmission of the input signal to the first output signal terminal BL and the second output signal terminal NBL under the control of the first power supply voltage signal terminal VDD.

Illustratively, the output terminals of the first diode and the second diode are coupled to the first power supply voltage signal terminal VDD, thereby forming a clamp circuit. In the process of transmitting the input signal Din to the first output signal terminal BL and transmitting the inverted input signal Din to the second output signal terminal NBL, the first diode and the second diode are both kept in the off state, so that the input signal Din and the inverted input signal Din are prevented from generating interference with each other, and the write-in sub-circuit 11 is more stable in the working process.

In some embodiments, as shown with reference to fig. 1c and 1f, the write sub-circuit 11 is further coupled to a reset signal terminal Rstn. The write sub-circuit 11 is configured to reset the first output signal terminal BL and the second output signal terminal NBL under the control of the reset signal terminal Rstn and the first power supply voltage signal terminal VDD.

For example, during the process of resetting the first output signal terminal BL and the second output signal terminal NBL, the potentials of the first output signal terminal BL and the second output signal terminal NBL may be pulled up to the magnitude of the first power voltage signal VDD. In the working process of the write-in sub-circuit 11, the write-in sub-circuit 11 firstly resets and then transmits the input signal Din, so that the situation that the signal output of the first output signal end BL and the signal output of the second output signal end NBL is influenced by the residual signal after the previous signal output is avoided, and the accuracy and precision of the output signal of the write-in sub-circuit 11 are improved.

In some embodiments, referring to fig. 1a, 1b and 1c, the second gate driving signal terminal G2 is coupled to the first node N1, and the third gate driving signal terminal G3 is coupled to the second node N2.

When the second gate driving signal terminal G2 is coupled to the first node N1 and the third gate driving signal terminal G3 is coupled to the second node N2, the readout sub-circuit 13 may multiplex a part of the circuits in the write sub-circuit 11, so that the circuit structure in the SRAM memory 1 may be simplified, the areas of the write sub-circuit 11 and the readout sub-circuit 13 may be reduced, the production cost may be reduced, and the market competitiveness of the SRAM memory 1 may be improved.

In other embodiments, referring to fig. 1d, 1e, 1f and 1G, the second gate driving signal terminal G2 is coupled to the first output signal terminal BL, and the third gate driving signal terminal G3 is coupled to the second output signal terminal NBL. In this circuit configuration, the write sub-circuit 11 and the read sub-circuit 13 are relatively independent, so that mutual interference between the sub-circuits can be reduced, and the stability of the operation of the SRAM memory 1 can be improved.

In some embodiments, referring to fig. 2a, the sensing sub-circuit 13 further includes a data latch unit 131, and the data latch unit 131 is configured to latch signals output by the third output signal terminal Out and the fourth output signal terminal Outn.

For example, referring to fig. 2a, the data latch unit 131 is coupled to the third output signal terminal Out and the fourth output signal terminal Outn, respectively, and under the control of the third output signal Out output from the third output signal terminal Out and the fourth output signal Outn output from the fourth output signal terminal Outn, the data latch unit 131 may temporarily store the third output signal Out and the fourth output signal Outn and output data from the fifth output signal terminal D0 and/or the sixth output signal terminal D.

Based on the above, it can be understood by those skilled in the art that the fifth output signal terminal D0 and the sixth output signal terminal D are the final signal output terminals of the readout sub-circuit 13.

For example, in some embodiments, the final output signal of the readout sub-circuit 13 is output from the fifth output signal terminal D0; in this configuration, the fifth output signal terminal D0 is coupled to an external circuit.

As another example, in other embodiments, the final output signal of the readout sub-circuit 13 is output from the sixth output signal terminal D; under this configuration, the sixth output signal terminal D is coupled to an external circuit, and the external circuit includes an inverter.

It will be appreciated by those skilled in the art that the output signal of the readout sub-circuit 13 is used as an input signal for an external circuit, which can operate on the input signal to obtain a corresponding operation result.

In some embodiments, referring to fig. 2b, the data latch unit 131 includes at least one flip-flop, and a Set terminal Set and a reset terminal Rst of the flip-flop are coupled to the third output signal terminal Out and the fourth output signal terminal Outn in a one-to-one correspondence, respectively. For example, the third output signal terminal Out is coupled to the Set terminal Set of the flip-flop, and the fourth output signal terminal Outn is coupled to the reset terminal Rst of the flip-flop.

Illustratively, the flip-flop described above is an RS flip-flop.

Further illustratively, referring to fig. 2b, the data latch unit 131 includes a first RS flip-flop 1311 and a second RS flip-flop 1312. The set terminal of the first RS flip-flop 1311 is coupled to the third output signal terminal Out, and the reset terminal is coupled to the fourth output signal terminal Outn. The set terminal of the second RS flip-flop 1312 is coupled to the first output terminal Q of the first RS flip-flop 1311, and the reset terminal of the second RS flip-flop 1312 is coupled to the second output terminal Qn of the first RS flip-flop 1311; one output terminal of the second RS flip-flop 1312 serves as a fifth output signal terminal D0, and the other output terminal thereof serves as a sixth output signal terminal D.

In the embodiment of the present invention, only the data latch unit 131 includes 2 RS flip-flops for illustration, and it can be understood by those skilled in the art that the data latch unit 131 may include only one RS flip-flop, where the Set terminal Set and the reset terminal Rst of the RS flip-flop are respectively coupled to the third output signal terminal Out and the fourth output signal terminal Outn, and the two output terminals are respectively used as the fifth output signal terminal D0 and the sixth output signal terminal D.

Referring to fig. 2c, the first RS flip-flop 1311 includes, for example, a first nand gate 1313 and a second nand gate 1314. The Set terminal Set of the first nand gate 1313 is coupled to the output terminal Qn of the second nand gate 1314, the reset terminal Rst of the second nand gate 1314 is coupled to the output terminal Q of the first nand gate 1313, the reset terminal Rst of the first nand gate 1313 is configured to be coupled to the fourth output signal terminal Outn, and the Set terminal Set of the second nand gate 1314 is configured to be coupled to the third output signal terminal Out.

The second RS flip-flop 1312 has the same structure as the first RS flip-flop 1311, except that one of the two output terminals of the two nand gates in the second RS flip-flop 1312 serves as the fifth output signal terminal D0, and the other serves as the sixth output signal terminal D.

In some embodiments, referring to fig. 3a to 3d, the write sub-circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and an inverter 111.

The gate of the first transistor M1 is coupled to the first enable signal terminal We, the first pole is coupled to the input signal terminal Din, and the second pole is coupled to the first node N1.

The gate of the second transistor M2 is coupled to the first enable signal We, the first pole is coupled to the output of the inverter 111, and the second pole is coupled to the second node N2.

The gate of the third transistor M3 is coupled to the selection signal terminal Sel, the first pole is coupled to the first node N1, and the second pole is coupled to the first output signal terminal BL.

The gate of the fourth transistor M4 is coupled to the selection signal terminal Sel, the first pole is coupled to the second node N2, and the second pole is coupled to the second output signal terminal NBL.

The input terminal of the inverter 111 is coupled to the input signal terminal Din.

For example, the first enable signal We and the select signal Sel are active high, and the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all N-type transistors. In the data writing phase, when the first enable signal We and the select signal Sel are at a high level, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all turned on, and the input signal Din passes through the first transistor M1 and the third transistor M3 and is output from the first output signal end BL; the input signal Din is inverted by the inverter 111 and flows into the second transistor M2 and the fourth transistor M4, and the inverted input signal Din is output from the second output signal terminal NBL. For example, when the input signal Din is at a high level, the first output signal BL output from the first output signal terminal BL is at a high level, for example, 1; the second output signal NBL output from the second output signal terminal NBL is low, for example, 0.

The write-in sub-circuit 11 has a simple structure, requires fewer control signals, can output signals, is convenient for building a circuit and reduces the production cost of the circuit to the greatest extent.

In some embodiments, referring to fig. 3b and 3D, the write sub-circuit 11 includes a first diode D1 and a second diode D2, and the write sub-circuit 11 is further coupled to the first power supply voltage signal terminal VDD. The input end of the first diode D1 is coupled to the first node N1, and the output end is coupled to the first power voltage signal end VDD; the second diode D2 has an input coupled to the second node N2 and an output coupled to the first power voltage signal terminal VDD.

The first diode D1 and the second diode D2 constitute a potential clamp circuit, and since the first power voltage VDD provided by the first power voltage signal terminal VDD is much greater than the level of the input signal Din, the first diode D1 and the second diode D2 are both unlikely to be turned on in the reverse direction, so that the mutual interference generated between the voltage of the first node N1 and the voltage of the second node N2 can be reduced, and the stability of the write sub-circuit 11 is finally improved.

In some embodiments, as shown with reference to fig. 3c and 3d, the write sub-circuit 11 further includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is coupled to the reset signal terminal Rstn, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the first output signal terminal BL.

The gate of the sixth transistor M6 is coupled to the reset signal terminal Rstn, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the second output signal terminal NBL.

For example, the low level of the reset signal Rstn provided by the reset signal terminal Rstn is an active signal, and the fifth transistor M5 and the sixth transistor M6 may be P-type transistors, such as PMOS transistors.

When the reset signal Rstn is at a low level, the fifth transistor M5 and the sixth transistor M6 are turned on, the first power supply voltage signal terminal VDD provides the first power supply voltage signal VDD, and the first power supply voltage signal VDD is transmitted to the first output signal terminal BL and the second output signal terminal NBL, so that the potentials of the first output signal terminal BL and the second output signal terminal NBL are pulled up, and the first output signal terminal BL and the second output signal terminal NBL are reset.

The reset phase of the write-in sub-circuit 11 is located before the data write-in phase, and resetting the first output signal terminal BL and the second output signal terminal NBL can ensure the accuracy of the first output signal output by the first output signal terminal BL and the second output signal output by the second output signal terminal NBL during the data write-in phase, thereby improving the performance of the write-in sub-circuit 11.

In some embodiments, as shown with reference to FIG. 4, the memory sub-circuit 12 includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.

The gate of the seventh transistor M7 is coupled to the first control node S1, the first pole is coupled to the second power voltage signal terminal Vss, and the second pole is coupled to the second control node S2.

The gate of the eighth transistor M8 is coupled to the first control node S1, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the second control node S2.

The gate of the ninth transistor M9 is coupled to the second control node S2, the first pole is coupled to the second power voltage signal terminal Vss, and the second pole is coupled to the first control node S1.

The gate of the tenth transistor M10 is coupled to the second control node S2, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the first control node S1.

The gate of the eleventh transistor M11 is coupled to the first gate driving signal terminal WL, the first pole is coupled to the second output signal terminal NBL, and the second pole is coupled to the second control node S2.

The twelfth transistor M12 has a gate coupled to the first gate driving signal terminal WL, a first pole coupled to the first output signal terminal BL, and a second pole coupled to the first control node S1.

Illustratively, the first gate driving signal WL provided by the first gate driving signal terminal WL is active high. On this basis, the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the twelfth transistor M12 are exemplified as N-type transistors; the eighth transistor M8 and the tenth transistor M10 are both P-type transistors, such as PMOS transistors.

The twelfth transistor M12 is turned on to transmit the first output signal BL to the first control node S1 when the first gate driving signal WL is at a high level, and the eleventh transistor M11 is turned on to transmit the second output signal NBL to the second control node S2, and meanwhile, when the first output signal BL is at a high level and the second output signal NBL is at a low level, the first control node S1 is at a high level and the second control node S2 is at a low level. When the first control node S1 is at a high level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, and the seventh transistor M7 is turned on to transmit the second power voltage signal Vss provided by the second power voltage signal terminal Vss to the second control node S2, where the signals are all at a low level, i.e., Vss level (e.g., 0), on the line formed by the seventh transistor M7, the second control node S2, the eleventh transistor M11, and the second output signal terminal NBL; when the second control node S2 is at a low level, the ninth transistor M9 is turned off, the tenth transistor M10 is turned on to transmit the first power voltage signal VDD to the first control node S1, and signals are all at a high level, i.e., VDD level (e.g., 1), on a line formed by the tenth transistor M10, the first control node S1, the twelfth transistor M12, and the first output signal terminal BL. The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 thus constitute two cross-coupled inverters, the first output signal BL is stored at the first control node S1, the second output signal NBL is stored at the second control node S2, the potential of the first control node S1 is 1 when the first output signal BL is 1, and the potential of the second control node S2 is 0 when the second output signal NBL is 0, and vice versa; the storage sub-circuit 12 thus realizes storage of the signal output by the write sub-circuit 11.

In other embodiments, memory sub-circuits 12 are distributed in an array, such as in a plurality of rows and columns. The memory sub-circuits 12 located in the same row share the same first power supply voltage signal line VDD, second power supply voltage signal line Vss and first gate driving signal line WL; the memory sub-circuits 12 in the same column share the same first output signal line BL and second output signal line NBL.

The memory sub-circuit 12 can realize the storage of data by only 6 transistors at least, and has a simple structure. The plurality of memory sub-circuits 12 distributed in the array can store more signals, so the number of memory sub-circuits 12 needs to be set according to the requirements of the processing circuit chip and the electronic device.

In some embodiments, as shown with reference to fig. 5a and 5b, the readout sub-circuit 13 includes: a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17.

The gate of the thirteenth transistor M13 is coupled to the second gate driving signal terminal G2, the first pole is coupled to the second pole of the seventeenth transistor M17, and the second pole is coupled to the fourth output signal terminal Outn.

The gate of the fourteenth transistor M14 is coupled to the third gate driving signal terminal G3, the first pole is coupled to the second pole of the seventeenth transistor M17, and the second pole is coupled to the third output signal terminal Out.

The gate of the fifteenth transistor M15 is coupled to the second enable signal terminal Lat, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the fourth output signal terminal Outn.

The gate of the sixteenth transistor M16 is coupled to the second enable signal terminal Lat, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the third output signal terminal Out.

The gate of the seventeenth transistor M17 is coupled to the second enable signal terminal Lat, and the first pole is coupled to the second power voltage signal terminal Vss.

For example, the thirteenth transistor M13, the fourteenth transistor M14, and the seventeenth transistor M17 are N-type transistors; the fifteenth transistor M15 and the sixteenth transistor M16 are P-type transistors, such as PMOS transistors. When the second enable signal Lat is at a low level, the seventeenth transistor M17 is turned off, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on to transmit the first power voltage signal VDD provided by the first power voltage signal terminal VDD to the third output signal terminal Out and the fourth output signal terminal Outn, the third output signal terminal Out and the fourth output signal terminal Outn are reset by pulling high potentials, and at this time, the third output signal terminal Out and the fourth output signal terminal Outn both keep at a high level. When the second gate driving signal G2 provided by the second gate driving signal terminal G2 is at a high level, the thirteenth transistor M13 is turned on, and when the second enable signal Lat is at a high level, the seventeenth transistor M17 is turned on to transmit the second power voltage signal Vss to the thirteenth transistor M13, the thirteenth transistor M13 transmits the second power voltage signal Vss to the fourth output signal terminal Outn, and the fourth output signal Outn output by the fourth output signal terminal Outn is at a low level; when the third gate driving signal G3 is at a low level, the fourteenth transistor M14 is turned off, and the third output signal Out output by the third output signal terminal Out still maintains the high level at the time of reset. As a result, when the readout sub-circuit 13 operates, the levels of the third output signal Out and the fourth output signal Outn are different, one of them is high, and the other is necessarily low.

Referring to fig. 5b, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the first diode D1 and the second diode D2 in the write sub-circuit 11 constitute a multiplexing unit 110, the multiplexing unit 110 is configured to be multiplexed as a part of the read sub-circuit 13 when the read sub-circuit 13 is in operation, and the read sub-circuit 13 is configured to read data from the memory sub-circuit 12.

Referring to FIG. 5b, the second gate driving signal terminal G2 is coupled to the first node N1 of the write sub-circuit 11, and the third gate driving signal terminal G3 is coupled to the second node N2 of the write sub-circuit 11; the memory sub-circuit 12 and the write sub-circuit 11 are coupled via a first output signal terminal BL and a second output signal terminal NBL. When the readout sub-circuit 13 needs to read out data in the memory sub-circuit 12, the reset signal Rstn in the multiplexing unit 110 is at a high level, the fifth transistor M5 and the sixth transistor M6 are turned on, the first output signal terminal BL and the second output signal terminal NBL are reset first, the first gate driving signal WL is an inactive signal, and the eleventh transistor M11 and the twelfth transistor M12 are turned off, so that resetting the first output signal terminal BL and the second output signal terminal NBL does not affect the data stored in the memory sub-circuit 12. After the reset, the fifth transistor M5 and the sixth transistor M6 are turned off.

When the storage sub-circuit 12 stores a high level, the first control node S1 is at a high level, the second control node S2 is at a low level, when the first gate driving signal WL is at a high level, the eleventh transistor M11 is turned on, the second output signal terminal NBL outputs the second output signal NBL at a low level, the twelfth transistor M12 is turned on, the first output signal terminal BL outputs the first output signal BL at a high level, the select signal Sel is also at a high level, the third transistor M3 and the fourth transistor M4 are turned on, and the potential of the first node N1 is controlled to be at a high level, and the potential of the second node N2 is controlled to be at a low level; when the first node N1 is at a high level, the second gate driving signal G2 is also at a high level, the thirteenth transistor M13 is turned on, meanwhile, the second enable signal Lat is at a high level, and the seventeenth transistor M17 is turned on, so that the fourth output signal Outn output by the fourth output signal terminal Outn is at a low level; when the second node N2 is at a low level, the fourteenth transistor M14 is in an off state, and the third output signal terminal Out maintains a high level in a reset stage (a reset stage of the readout sub-circuit 13), where the level is VDD, that is, the third output signal Out output by the third output signal terminal Out is at a high level, so that the level of the third output signal Out is higher than the level of the fourth output signal Outn.

When the storage sub-circuit 12 stores a low level, the first control node S1 is at a low level, the second control node S2 is at a high level, when the first gate driving signal WL is at a high level, the eleventh transistor M11 is turned on, the second output signal terminal NBL outputs the second output signal NBL at a high level, the twelfth transistor M12 is turned on, the first output signal terminal BL outputs the first output signal BL at a low level, the select signal Sel is also at a high level, the third transistor M3 and the fourth transistor M4 are turned on, and the potential of the first node N1 is controlled to be at a low level, and the potential of the second node N2 is controlled to be at a high level; when the first node N1 is at a low level, the second gate driving signal G2 is also at a low level, and the thirteenth transistor M13 is in an off state, so that the fourth output signal Outn remains at a high level, i.e., VDD; when the second node N2 is at a high level, the fourteenth transistor M14 is turned on, and meanwhile, the second enable signal Lat is at a high level, and the seventeenth transistor M17 is turned on, so as to control the third output signal terminal Out to output the third output signal Out at a low level, wherein the low level is Vss; so that the level of the third output signal Out is lower than the level of the fourth output signal Outn. Therefore, the third output signal Out output by the third output signal terminal Out is the signal stored by the storage sub-circuit 12, and when the storage sub-circuit 12 stores a high level, the third output signal Out is a high level, for example, 1; when the storage sub-circuit 12 stores a low level, the third output signal Out is a low level, for example, 0.

It should be noted that, referring to the structure in fig. 5b, the structure of the write sub-circuit 11 can also be as shown in fig. 3a, 3b and 3 c.

The read sub-circuit 13 has a simple structure, and the multiplexing unit 110 can be shared with the write sub-circuit 11, thereby simplifying the structure of the read sub-circuit 13 to the maximum extent.

In other embodiments, and as shown with reference to fig. 6a and 6b, the readout sub-circuit 13 includes: a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19.

The gate of the eighteenth transistor M18 is coupled to the selection signal terminal Sel, the first pole is coupled to the first output signal terminal BL, and the second pole is coupled to the second gate driving signal terminal G2.

The gate of the nineteenth transistor M19 is coupled to the selection signal terminal Sel, the first pole is coupled to the second output signal terminal NBL, and the second pole is coupled to the third gate driving signal terminal G3.

The eighteenth transistor M18 and the nineteenth transistor M19 are, for example, N-type transistors.

Referring to fig. 6b, the readout sub-circuit 13 further includes a third diode D3 and a fourth diode D4, wherein an input terminal of the third diode D3 is coupled to the third node N3, and an output terminal thereof is coupled to the first power voltage signal terminal VDD; an input terminal of the fourth diode D4 is coupled to the fourth node N4, and an output terminal thereof is coupled to the first power voltage signal terminal VDD; the third node N3 is coupled to the second gate driving signal terminal G3, and the fourth node N4 is coupled to the third gate driving signal terminal G3.

Referring to fig. 6a and 6b, the read-out sub-circuit 13 is directly coupled to the first output signal terminal BL and the second output signal terminal NBL, i.e. the read-out sub-circuit 13 no longer multiplexes the multiplexing unit 110 in the write sub-circuit 11.

Referring to fig. 6b, when the read sub-circuit 13 needs to read the data stored in the storage sub-circuit 12, when the storage sub-circuit 12 stores a high level, the level of the first control node S1 is a high level, and the level of the second control node S2 is a low level; when the selection signal Sel is at a high level, the eighteenth transistor M18 and the nineteenth transistor M19 are controlled to be turned on, so that the level of the third node N3 is at a high level, the level of the fourth node N4 is at a low level, the second gate driving signal G2 is at a high level to control the thirteenth transistor M13 to be turned on, meanwhile, the second enable signal Lat is at a high level to control the seventeenth transistor M17 to be turned on, and finally, the fourth output signal Outn is at a low level; when the fourth node N4 is at a low level, the third gate driving signal G3 is at a low level to control the fourteenth transistor M14 to turn off, and the third output signal Out is at a high level (keeping the magnitude of VDD).

When the storage sub-circuit 12 stores a low level, the level of the first control node S1 is a low level, and the level of the second control node S2 is a high level; when the selection signal Sel is at a high level, the eighteenth transistor M18 and the nineteenth transistor M19 are controlled to be turned on, so that the level of the third node N3 is at a low level, the level of the fourth node N4 is at a high level, the second gate driving signal G2 is at a low level, the thirteenth transistor M13 is turned off, and the fourth output signal Outn is at a high level; when the fourth node N4 is at a high level, the third gate driving signal G3 is at a high level, the fourteenth transistor M14 is turned on, the second enable signal Lat is at a high level, the seventeenth transistor M17 is turned on, and the third output signal Out is at a low level.

Referring to fig. 6c and 6d, the readout sub-circuit 13 further includes a twentieth transistor M20 and a twentieth transistor M21, a gate of the twentieth transistor M20 is coupled to the reset signal terminal Rstn, a first pole is coupled to the first power supply voltage signal terminal VDD, and a second pole is coupled to the first output signal terminal BL; the gate of the twenty-first transistor M21 is coupled to the reset signal terminal Rstn, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the second output signal terminal NBL. The twentieth transistor M20 and the twenty-first transistor M21 are, for example, P-type transistors, such as PMOS transistors.

The readout sub-circuit 13 may reset the first output signal terminal BL and the second output signal terminal NBL before reading out data, and when the reset signal Rstn is at a high level, the twentieth transistor M20 and the twenty-first transistor M21 are turned on to reset the first output signal terminal BL and the second output signal terminal NBL, so as to ensure accuracy of data read out from the storage sub-circuit 12 by the readout sub-circuit 13.

It should be noted that the structure of the write sub-circuit 11 in fig. 6a to 6d may also be the structure of the write sub-circuit 11 as shown in fig. 3a, 3c and 3d, but the read sub-circuit 13 does not multiplex the structure in the write sub-circuit 11 at this time, i.e. the overall structure of the write sub-circuit 11 is not changed, but the multiplexing unit 110 does not need to be subdivided.

It will be understood by those skilled in the art that when the readout sub-circuit 13 is in operation, the selection signal Sel is high, and the third transistor M3 and the fourth transistor M4 in the write sub-circuit 11 are also turned on, but since the first enable signal We is not valid, no path is formed in the write sub-circuit 11. Based on this, in other embodiments, the signal connected to the eighteenth transistor M18 and the nineteenth transistor M19 may be other signals, and this signal is only used as the selection signal Sel in this application for illustration, but is not limited thereto.

In other embodiments, referring to fig. 7, the sensing sub-circuit 13 further includes a data latch unit 131. Further, the data latch unit 131 includes, for example, a first RS flip-flop 1311. The Set terminal Set of the first RS flip-flop 1311 is coupled to the third output signal terminal Out, the reset terminal Rst of the first RS flip-flop 1311 is coupled to the fourth output signal terminal Outn, the output terminal Q of the first RS flip-flop 1311 serves as the fifth output signal terminal D0, and the output terminal Qn of the first RS flip-flop 1311 serves as the sixth output signal terminal D.

Illustratively, when the third output signal Out is at a high level 1 and the fourth output signal Outn is at a low level 0, the reset terminal Rst of the first nand gate 1313 is at 0 and the set terminal of the second nand gate 1314 is at 1, so that the fifth output signal terminal D0 outputs a high level 1 and finally inputs a high level 1 to the external circuit. When the fifth output signal terminal D0 outputs a high level 1, the potential of the sixth output signal terminal D is 0, and the sixth output signal terminal D is in a floating state when the sixth output signal terminal D is not coupled to an external circuit.

The data latch unit 131 is used to implement a data latch function, and the data read from the storage sub-circuit 12 by the reading sub-circuit 13 is latched at the fifth output signal terminal D0 or the sixth output signal terminal D until the next second enable signal Lat arrives.

Illustratively, when the third output signal terminal Out outputs a high level, for example, 1, and the fourth output signal terminal Outn outputs a low level, for example, 0, then the fifth output signal terminal D0 outputs a high level, for example, 1, so that the readout sub-circuit 13 achieves the purpose of reading Out the same signal as the storage sub-circuit 12 from the storage sub-circuit 12.

In the above description, the writing sub-circuit 11, the storing sub-circuit 12 and the reading sub-circuit 13 in the SRAM memory 1 work together, but in some embodiments, the writing sub-circuit 11, the storing sub-circuit 12 and the reading sub-circuit 13 in the SRAM memory 1 may also be used alone or in combination.

For example, referring to fig. 1a and 1d, an embodiment of the present invention further provides a write sub-circuit 11 of the SRAM memory 1, where the write sub-circuit 11 includes: an input signal terminal Din, a selection signal terminal Sel, a first enable signal terminal We, a first output signal terminal BL and a second output signal terminal NBL. The write sub-circuit 11 is used to output the input signal Din provided from the input signal terminal Din from the first output signal terminal BL and output the inverted input signal Din from the second output signal terminal NBL under the control of the selection signal terminal Sel and the first enable signal terminal We. The description of the write sub-circuit 11 is described in detail in the foregoing description of the SRAM memory 1, and thus is not repeated.

Still further, referring to fig. 1c and 1f, the write sub-circuit 11 further includes a first power supply voltage signal terminal VDD and a reset signal terminal Rstn. The write sub-circuit 11 is also used to reset the first output signal terminal BL and the second output signal terminal NBL under the control of the reset signal terminal Rstn and the first power supply voltage signal terminal VDD.

For another example, referring to fig. 1a to 1c, an embodiment of the present invention further provides a readout sub-circuit 13 of the SRAM memory 1, including: a first power supply voltage signal terminal VDD, a second power supply voltage signal terminal Vss, a second enable signal terminal Lat, a second gate driving signal terminal G2, a third gate driving signal terminal G3, a third output signal terminal Out, and a fourth output signal terminal Outn. The readout sub-circuit 13 is used to pull up the potentials of the third output signal terminal Out and the fourth output signal terminal Outn to the first power supply voltage signal VDD supplied from the first power supply voltage signal terminal VDD under the control of the first power supply voltage signal terminal VDD and the second enable signal terminal Lat, and to output signals of different potentials from the third output signal terminal Out and the fourth output signal terminal Outn under the control of the second gate drive signal terminal G2, the third gate drive signal terminal G3, the second enable signal terminal Lat, and the second power supply voltage signal terminal Vss.

The structure of the write sub-circuit 11 and the read sub-circuit 13 when used separately is described above, and the structure of the read/write circuit 10 formed by using the write sub-circuit 11 and the read sub-circuit 13 in combination is described below.

In some embodiments, referring to fig. 5b, the read-write circuit 10 of the SRAM memory 1 includes a write sub-circuit 11 and a read sub-circuit 13.

The write sub-circuit 11 includes: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the first diode D1, the second diode D2, the inverter 111, the input signal terminal Din, the first enable signal terminal We, the selection signal terminal Sel, the first power supply voltage signal terminal VDD, the reset signal terminal Rstn, the first output signal terminal BL, and the second output signal terminal NBL.

The gate of the fifth transistor M5 is coupled to the reset signal terminal Rstn, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the first output signal terminal BL.

The gate of the sixth transistor M6 is coupled to the reset signal terminal BL, the first pole is coupled to the first power voltage signal terminal VDD, and the second pole is coupled to the second output signal terminal NBL.

The input end of the first diode D1 is coupled to the first node N1, and the output end is coupled to the first power voltage signal end VDD; the second diode D2 has an input coupled to the second node N2 and an output coupled to the first power voltage signal terminal VDD.

The readout sub-circuit 13 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, a second enable signal terminal Lat, a second gate drive signal terminal G2, a third gate drive signal terminal G3, a first power supply voltage signal terminal VDD, a second power supply voltage signal terminal Vss, a third output signal terminal Out, and a fourth output signal terminal Outn.

The second gate driving signal terminal G2 is coupled to the first node N1, and the third gate driving signal terminal G3 is coupled to the second node N2.

The functions and other different structures of the write sub-circuit 11 and the read sub-circuit 13 of the SRAM memory 1 are also described in detail above, and are understood by referring to the foregoing description, and therefore are not described in detail herein.

Referring to fig. 8a, an embodiment of the present invention further provides a control method of the SRAM memory 1, including:

s1, the write sub-circuit 11 outputs the input signal Din provided from the input signal terminal Din from the first output signal terminal BL and outputs the inverted input signal from the second output signal terminal NBL under the control of the selection signal terminal Sel and the first enable signal terminal We.

That is, the first output signal BL and the second output signal NBL are inverse signals, and the first output signal BL and the input signal Din are the same.

S2, the memory sub-circuit 12 stores the first output signal BL provided by the first output signal terminal BL and the second output signal NBL provided by the second output signal terminal NBL under the control of the first power supply voltage signal terminal VDD, the second power supply voltage signal terminal Vss and the first gate driving signal terminal WL.

Illustratively, the storage sub-circuit 12 has a first control node S1 and a second control node S2, the first output signal BL being stored at the first control node S1 and the second output signal NBL being stored at the second control node S2.

S3, the readout sub-circuit 13 pulls up the potentials of the third output signal terminal Out and the fourth output signal terminal Outn to the first power supply voltage signal VDD provided by the first power supply voltage signal terminal VDD under the control of the first power supply voltage signal terminal VDD and the second enable signal terminal Lat, and outputs signals of different potentials from the third output signal terminal Out and the fourth output signal terminal Outn under the control of the second gate drive signal terminal G2, the third gate drive signal terminal G3, the second enable signal terminal Lat and the second power supply voltage signal terminal Vss, wherein the second gate drive signal G2 provided by the second gate drive signal terminal G2 is generated by the first output signal BL stored in the memory sub-circuit memory 12, and the third gate drive signal G3 provided by the third gate drive signal terminal G3 is generated by the second output signal NBL of the memory sub-circuit memory 12.

The second gate driving signal G2 is generated by the first output signal BL of the memory sub-circuit 12, i.e. the first output signal BL stored by the memory sub-circuit can be transmitted to the second gate driving signal terminal G2 as the second gate driving signal G2; the third gate driving signal G3 is generated by the second output signal NBL of the memory sub-circuit 12, i.e., the second output signal NBL can be transmitted to the third gate driving signal terminal G3 as the third gate driving signal G3.

The write sub-circuit 11 functions to write data into the memory sub-circuit 12, the memory sub-circuit 12 functions to store data, and the read sub-circuit 13 reads data from the memory sub-circuit 12 after the data is stored.

In the present application, the source of the second gate driving signal G2 and the source of the third gate driving signal G3 are the memory sub-circuit 12, the memory sub-circuit 12 outputs the first output signal BL and the second output signal NBL from the first output signal terminal BL and the second output signal terminal NBL, respectively, and the first output signal BL and the second output signal NBL are transmitted and finally received by the readout sub-circuit 13 to become the second gate driving signal G2 and the third gate driving signal G3.

The control method of the SRAM memory 1 in the present application has the same beneficial effects as the aforementioned SRAM memory 1, and therefore, the detailed description thereof is omitted.

In some embodiments, referring to fig. 8b, the readout sub-circuit 13 outputs signals of different potentials from the third output signal terminal Out and the fourth output signal terminal Outn under the control of the first node N1, the second node N2, the second gate driving signal terminal G2, the third gate driving signal terminal G3, the second enable signal terminal Lat, and the second power supply voltage signal terminal Vss.

When the readout sub-circuit 13 performs data reading, the first output signal BL is transmitted to the first node N1, the second output signal NBL is transmitted to the second node N2, and the readout sub-circuit 13 is coupled to the write sub-circuit 11, the readout sub-circuit 13 needs to read out the potential of the first control node S1 and the potential of the second control node S2. At this time, the read sub-circuit 13 and the write sub-circuit 11 share a part of transistors.

In other embodiments, when the readout sub-circuit 13 performs data reading, the first output signal and the second output signal can be directly transmitted to the readout sub-circuit 13, and the readout sub-circuit 13 does not need to share transistors with the writing sub-circuit 11.

The read-out sub-circuit 13 is used to read data from the memory sub-circuit 12, so that this object can be achieved by a simple circuit design, which is simpler than a circuit in the related art that often requires several tens of transistors.

Referring to fig. 9a, in the data writing phase of the related art SRAM memory 1, the low level of the select signal CS is an active signal, the high level of the enable signal We is an active signal, and the input signal Din is written into the circuit under the control of the select signal CS, the enable signal We, and the address signal ADR.

Referring to fig. 9b, in the data read phase of the related art SRAM memory 1, the low level of the select signal CS is an active signal, the enable signal We maintains the low level, and the output terminal Dout outputs a signal under the control of the select signal CS and the enable signal We.

The related art has fewer control signals, and when a circuit of the SRAM memory is designed, more transistors are needed to cooperate to realize control with fewer signals.

The control method of the SRAM memory 1 in the present application is described below with reference to a timing chart and a circuit configuration diagram:

referring to fig. 10 in conjunction with fig. 5b, the reset phase: in the write sub-circuit 11, when a rising edge of the clock signal CLK arrives, that is, after a time t0 arrives, the reset signal Rstn jumps from a high level to a low level at a time t1, a low-level pulse is generated, and when the reset signal Rstn is an active signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and reset operations are performed on the first output signal terminal BL and the second output signal terminal NBL to pull up the levels of the first output signal terminal BL and the second output signal terminal NBL to the high level; when the reset signal Rstn jumps from low to high at time t2, the reset signal Rstn becomes an invalid signal, and the reset phase of the write sub-circuit 11 ends. The time when the clock signal CLK changes from high level to low level is t4, time t2 is less than time t4 and greater than time t1, and time t1 is greater than time t0, that is, the width of the active level of the reset signal Rstn is less than the width of the active level of the clock signal CLK.

A data writing stage: after the reset phase, the first enable signal We jumps from low level to high level at time t3 to control the first transistor M1 and the second transistor M2 to be turned on, and the select signal Sel also jumps from low level to high level at time t3 to control the third transistor M3 and the fourth transistor M4 to be turned on. The input signal Din provided from the input signal terminal Din is transmitted to the first output signal terminal BL through the first transistor M1 and the third transistor M3, and the inverted input signal Din is transmitted to the second output signal terminal NBL through the second transistor M2 and the fourth transistor M4. At this time, in the memory sub-circuit 12, the first gate driving signal WL jumps from the low level to the high level at time t3 to control the twelfth transistor M12 and the eleventh transistor M11 to be turned on, and stores the first output signal BL to the first control node S1 and the second output signal NBL to the second node N2, respectively. At time t4, the first enable signal We, the select signal Sel, and the first gate drive signal WL all jump low again from high, and time t4 coincides with the time of the falling edge of the clock signal CLK.

When the memory sub-circuit 12 is plural, the first output signal BL and the second output signal NBL are stored in which memory sub-circuit 12 is determined by an address signal ADR, which includes plural addresses, such as an address ADR1, an address ADR2, and the like; each address in the address signals ADR corresponds one-to-one to the memory sub-circuits 12.

And a data reading stage: the first gate driving signal WL jumps from the low level to the high level at time t5, the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the signal stored in the first control node S1 is output from the twelfth transistor M12 to the first output signal terminal BL, i.e., the first output signal BL; the signal stored in the second control node S2 is output from the eleventh transistor M11 to the second output signal terminal NBL, i.e., the second output signal NBL. The select signal Sel also jumps from low level to high level at time t5, the third transistor M3 and the fourth transistor M4 are turned on, the first output signal BL is transmitted to the first node N1 through the third transistor M3, and the second output signal NBL is transmitted to the second node N2 through the fourth transistor M4. Under the control of the first node N1, the thirteenth transistor M13 is turned on, the fourteenth transistor M14 is still turned off under the control of the second node N2, and at this time, the second enable signal Lat jumps from a low level to a high level at time t5, so that the seventeenth transistor M17 is controlled to be turned on, the fifteenth transistor M15 and the sixteenth transistor M16 are controlled to be turned off, and both the third output signal terminal Out and the fourth output signal terminal Outn are at a high level before the fifteenth transistor M15 and the sixteenth transistor M16 are turned off. When the thirteenth transistor M13 is turned on, the second power supply voltage signal Wss is transmitted to the fourth output signal terminal Outn, so that the third output signal terminal Out outputs a high level at this time, and the fourth output signal terminal Outn outputs a low level at this time, so that the third output signal Out at this time is the same as the first output signal BL, and the fourth output signal Outn is the same as the second output signal NBL, that is, the reading sub-circuit 13 reads the third output signal Out from the storage sub-circuit 12, which is the same as the potential of the first control node S1 in the storage sub-circuit 12, and the fourth output signal Outn, which is the same as the potential of the second control node S2, and finally achieves the purpose of data reading.

In some embodiments, the fifth output signal terminal D0 of the data latch unit 131 is coupled to an external circuit, so that the waveform diagram of the fifth output signal is as shown in fig. 10.

It should be noted that, during the data reading phase, there is also a reset process, when the second enable signal is at a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are both in an on state, and at this time, the first power voltage signal VDD can be transmitted to the third output signal terminal Out and the fourth output signal terminal Outn to reset them, so as to prepare for the output signals of the thirteenth transistor M13 and the fourteenth transistor M14.

It will be understood by those skilled in the art that although the first power supply voltage signal VDD and the second power supply voltage signal Vss are not shown in the present application, the first power supply voltage signal VDD and the second power supply voltage signal Vss are each embodied as a straight line in the timing diagram, except that the straight line of the first power supply voltage signal VDD represents a high level and the straight line of the second power supply voltage signal Vss represents a low level.

Compared with the related art in which the control signals only include an enable signal We, a select signal CS and an address signal ADR, the data writing stage and the reading stage of the circuit are controlled by the control signals, the number of the control signals is small, the number of transistors required in the circuit structure is large, the control of the circuit is not fine and stable, the number of the control signals in the present application is large, the number of the required transistors is small, the control is more precise and stable, and particularly, the control of the writing sub-circuit 11 and the reading sub-circuit 13 is more accurate, because the writing sub-circuit 11 is controlled by the first enable signal We and the reading sub-circuit 13 is controlled by the second enable signal Lat in the present application, so that the control of the writing sub-circuit 11 and the reading sub-circuit 13 is relatively independent, and the control process is relatively simple.

Referring to fig. 11a, the SRAM memory 1 in the embodiment of the present invention may further include a row decoder 15 and a logic controller 14; the row decoder 15 is configured to provide a first gate driving signal WL to the SRAM memory 1, and the logic controller 14 is configured to provide a reset signal Rstn, a first enable signal We, and a second enable signal Lat to the SRAM memory 1.

Referring to fig. 11a, the reset signal Rstn, the first enable signal We, and the second enable signal Lat in the write sub-circuit 11 and the read sub-circuit 13 are provided by the logic controller 14. The logic controller 14 supplies the reset signal Rstn, the first enable signal We, and the second enable signal Lat to the write sub-circuit 11 and the read sub-circuit 13 under the control of the clock signal CLK, the write enable signal, and the read enable signal externally supplied.

The logic controller 14 supplies the address signal ADR to the row decoder 15 under the control of the externally supplied address signal ADR, and the row decoder 15 supplies the first gate driving signal WL to the memory sub circuit array 12' under the control of the address signal ADR. The address signal ADR and the first output signal BL provided by the row decoder 15 determine which specific memory sub-circuit 12 of the memory sub-circuit array 12' is operated, and then the first enable signal We and the second enable signal Lat control whether the memory sub-circuit 12 performs data writing or data reading.

It will be understood by those skilled in the art that the signal line for transmitting the first gate driving signal WL may be referred to as a word line, and the signal lines for transmitting the first output signal BL and the second output signal NBL may be referred to as bit lines.

Referring to fig. 11b, a process in which the logic controller 14 generates the reset signal Rstn, the first enable signal We, and the second enable signal Lat according to the external clock signal CLK, the write enable signal, and the read enable signal is described.

The first step is as follows: an external clock signal CLK is input to the first delay block 141, and an output signal of the first delay block 141 and the clock signal CLK are input to the reset time generation block 144, so as to generate a reset signal Rstn, and the duration of the active level of the reset signal Rstn may be referred to fig. 10, for example, from t1 to t 2.

The second step is that: the output signal of the first delay block 141 is input to the second delay block 142, and the output signal of the second delay block 142 and an external write enable signal are input to the write time generation block 145, thereby generating the first enable signal We. The duration of the active level of the first enable signal We can refer to FIG. 10, for example, t 3-t 4.

The third step: the output signal of the second delay block 142 is input to the third delay block 143, and the output signal of the third delay block 143 and an external read enable signal are input to the readout time generation block 146, thereby generating the second enable signal Lat. The duration of the active level of the second enable signal Lat can refer to fig. 10, for example, t 5-t 6.

It will be understood by those skilled in the art that the first delay module 141, the second delay module 142, and the third delay module 143 all function as time delays; the functions of the reset time generation module 144, the write time generation module 145 and the read time generation module 146 are all signal recombination. The first delay module 141, the second delay module 142, the third delay module 143, the reset time generation module 144, the write time generation module 145, and the read time generation module 146 for implementing the above functions are all integrated circuits commonly used in the art, and therefore are not described in detail in this application.

It will be understood by those skilled in the art that the high level and the low level in this application are only relative, such as 1 for high level and 0 for low level; the signal lines, the signal terminals and the signals correspond to each other, and the same signal lines, the same signal terminals and the same signals are denoted by the same reference numerals, for example, the first power voltage signal line VDD is used for providing the first power voltage signal VDD, so that the signal terminals can be understood as terminals coupled to the signal lines, and can also be understood as a part of the signal lines; data and signals are synonymous; the transistors are all exemplified by field effect transistors, the first pole of each transistor can be a source, the second pole can be a drain, or vice versa, and the terminal of the signal input is taken as the first pole, and the terminal of the signal output is taken as the second pole for illustration. All or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A write subcircuit of an SRAM memory, comprising: the device comprises an input signal end, a selection signal end, a first enable signal end, a first output signal end and a second output signal end; and is configured to output an input signal provided by the input signal terminal from the first output signal terminal and output the inverted input signal from the second output signal terminal under the control of the selection signal terminal and the first enable signal terminal.

2. The write subcircuit of the SRAM memory of claim 1, further comprising: the first diode and the second diode are configured to stabilize the transmission of the input signal to the first output signal terminal and the second output signal terminal under the control of the first supply voltage signal terminal.

3. The write subcircuit of the SRAM memory of claim 2, further comprising: a reset signal terminal; and is further configured to reset the first output signal terminal and the second output signal terminal under control of the reset signal terminal and the first power supply voltage signal terminal.

4. The write subcircuit of the SRAM memory of claim 1 or 2, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter;

a gate of the second transistor is coupled to the first enable signal terminal, a first pole of the second transistor is coupled to an output terminal of the inverter, and a second pole of the second transistor is coupled to a first pole of the fourth transistor;

a gate of the third transistor is coupled to the selection signal terminal, and a second pole is coupled to the first output signal terminal;

a gate of the fourth transistor is coupled to the selection signal terminal, and a second pole of the fourth transistor is coupled to the second output signal terminal;

the input end of the phase inverter is coupled with the input signal end.

5. The write sub-circuit of the SRAM memory according to claim 4, wherein in case that the write sub-circuit comprises a first power supply voltage signal terminal, a first diode and a second diode, an input terminal of the first diode is coupled to the second pole of the first transistor, and an output terminal is coupled to the first power supply voltage signal terminal; an input end of the second diode is coupled to the second electrode of the second transistor, and an output end of the second diode is coupled to the first power voltage signal end.

6. The write subcircuit of the SRAM memory of claim 3, further comprising: a fifth transistor and a sixth transistor;

a gate of the fifth transistor is coupled to the reset signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the first output signal terminal;

7. A read-out sub-circuit of an SRAM memory, comprising: a first power supply voltage signal end, a second enable signal end, a second gate drive signal end, a third output signal end and a fourth output signal end; is configured to pull up potentials of the third and fourth output signal terminals to a first power supply voltage signal provided from the first power supply voltage signal terminal under control of the first and second power supply voltage signal terminals, and to output signals of different potentials from the third and fourth output signal terminals under control of the second, third, second and second power supply voltage signal terminals.

8. The read-out sub-circuit of the SRAM memory of claim 7, further comprising: a data latch unit configured to latch signals output from the third and fourth output signal terminals.

9. A read-out sub-circuit of an SRAM memory according to claim 7 or 8, comprising: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

a gate of the thirteenth transistor is coupled to the second gate driving signal terminal, a first pole of the thirteenth transistor is coupled to a second pole of the seventeenth transistor, and the second pole of the thirteenth transistor is coupled to the fourth output signal terminal;

a gate of the fourteenth transistor is coupled to the third gate driving signal terminal, a first pole of the fourteenth transistor is coupled to a second pole of the seventeenth transistor, and a second pole of the fourteenth transistor is coupled to the third output signal terminal;

a gate of the fifteenth transistor is coupled to the second enable signal terminal, a first pole of the fifteenth transistor is coupled to the first power voltage signal terminal, and a second pole of the fifteenth transistor is coupled to the fourth output signal terminal;

a gate of the sixteenth transistor is coupled to the second enable signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the third output signal terminal;

10. An SRAM memory, comprising:

a write sub-circuit having a first node and a second node, coupled to an input signal terminal, a selection signal terminal, a first enable signal terminal, a first output signal terminal, and a second output signal terminal, and configured to output an input signal provided from the input signal terminal from the first output signal terminal and output an inverted input signal from the second output signal terminal under the control of the selection signal terminal and the first enable signal terminal; wherein the input signal is transmitted to the first output signal terminal through the first node, and the inverted input signal is transmitted to the second output signal terminal through the second node;

a storage sub-circuit coupled to the first output signal terminal, the second output signal terminal, a first power voltage signal terminal, a second power voltage signal terminal, and a first gate driving signal terminal, and configured to store a first output signal provided by the first output signal terminal and a second output signal provided by the second output signal terminal under the control of the first power voltage signal terminal, the second power voltage signal terminal, and the first gate driving signal terminal;

a readout sub-circuit coupled to the first power supply voltage signal terminal, the second power supply voltage signal terminal, a second enable signal terminal, a second gate driving signal terminal, a third output signal terminal, and a fourth output signal terminal, configured to pull up potentials of the third output signal terminal and the fourth output signal terminal to a first power supply voltage signal provided by the first power supply voltage signal terminal under control of the first power supply voltage signal terminal and the second enable signal terminal, and to output signals of different potentials from the third output signal terminal and the fourth output signal terminal under control of the second gate driving signal terminal, the third gate driving signal terminal, the second enable signal terminal, and the second power supply voltage signal terminal, wherein a second gate driving signal provided by the second gate driving signal terminal is generated from the first output signal stored by the storage sub-circuit, the third gate driving signal provided by the third gate driving signal terminal is generated by the second output signal stored by the storage sub-circuit.

11. The SRAM memory of claim 10, wherein the second gate drive signal terminal is coupled to the first node and the third gate drive signal terminal is coupled to the second node.

12. The SRAM memory of claim 11,

the write subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter;

a gate of the first transistor is coupled to the first enable signal terminal, a first pole is coupled to the input signal terminal, and a second pole is coupled to the first node;

a gate of the second transistor is coupled to the first enable signal terminal, a first pole is coupled to an output terminal of the inverter, and a second pole is coupled to the second node;

a gate of the third transistor is coupled to the selection signal terminal, a first pole of the third transistor is coupled to the first node, and a second pole of the third transistor is coupled to the first output signal terminal;

a gate of the fourth transistor is coupled to the selection signal terminal, a first pole of the fourth transistor is coupled to the second node, and a second pole of the fourth transistor is coupled to the second output signal terminal;

the input end of the phase inverter is coupled with the input signal end;

and/or

The memory sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

a gate of the seventh transistor is coupled to the first control node, a first pole of the seventh transistor is coupled to the second power voltage signal terminal, and a second pole of the seventh transistor is coupled to the second control node;

a gate of the eighth transistor is coupled to the first control node, a first pole of the eighth transistor is coupled to the first power voltage signal terminal, and a second pole of the eighth transistor is coupled to the second control node;

a gate of the ninth transistor is coupled to the second control node, a first pole of the ninth transistor is coupled to the second power voltage signal terminal, and a second pole of the ninth transistor is coupled to the first control node;

a gate of the tenth transistor is coupled to the second control node, a first pole of the tenth transistor is coupled to the first power voltage signal terminal, and a second pole of the tenth transistor is coupled to the first control node;

a gate of the eleventh transistor is coupled to the first gate driving signal terminal, a first pole of the eleventh transistor is coupled to the second output signal terminal, and a second pole of the eleventh transistor is coupled to the second control node;

a gate of the twelfth transistor is coupled to the first gate driving signal terminal, a first pole of the twelfth transistor is coupled to the first output signal terminal, and a second pole of the twelfth transistor is coupled to the first control node;

and/or

The readout sub-circuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

13. The SRAM memory of claim 10,

the input end of the phase inverter is coupled with the input signal end;

the readout sub-circuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

a gate of the thirteenth transistor is coupled to the second gate driving signal terminal, a first pole of the thirteenth transistor is coupled to a second pole of the seventeenth transistor, and a second pole of the thirteenth transistor is coupled to the fourth output signal terminal;

a gate of the fourteenth transistor is coupled to the third gate driving signal terminal, a first pole of the fourteenth transistor is coupled to a second pole of the seventeenth transistor, and the second pole of the fourteenth transistor is coupled to the third output signal terminal;

a gate of the seventeenth transistor is coupled to the second enable signal terminal, and a first pole of the seventeenth transistor is coupled to the second power voltage signal terminal;

a gate of the eighteenth transistor is coupled to the selection signal terminal, a first pole is coupled to the first output signal terminal, and a second pole is coupled to the second gate driving signal terminal;

14. A read-write circuit of an SRAM (static random access memory) is characterized by comprising a write-in sub-circuit and a read-out sub-circuit;

the write subcircuit includes: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first diode, a second diode, a phase inverter, an input signal end, a first enable signal end, a selection signal end, a first power supply voltage signal end, a reset signal end, a first output signal end and a second output signal end;

a gate of the first transistor is coupled to the first enable signal terminal, a first pole is coupled to the input signal terminal, and a second pole is coupled to a first node;

a gate of the second transistor is coupled to the first enable signal terminal, a first pole is coupled to an output terminal of the inverter, and a second pole is coupled to a second node;

a gate of the sixth transistor is coupled to the reset signal terminal, a first pole is coupled to the first power voltage signal terminal, and a second pole is coupled to the second output signal terminal;

the input end of the first diode is coupled with the first node, and the output end of the first diode is coupled with the first power supply voltage signal end; the input end of the second diode is coupled with the second node, and the output end of the second diode is coupled with the first power supply voltage signal end;

the input end of the phase inverter is coupled with the input signal end;

the reading sub-circuit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second enable signal end, a second grid driving signal end, a third grid driving signal end, a first power supply voltage signal end, a second power supply voltage signal end, a third output signal end and a fourth output signal end;

15. A processing circuit chip comprising the SRAM memory of any one of claims 10 to 13 and at least one processing circuit; the SRAM memory is used for storing data required by the at least one processing circuit during operation.

16. An electronic device comprising the processing circuit chip of claim 15 and a power supply for supplying power to the processing circuit chip.

17. A control method of an SRAM memory, the SRAM memory comprises a writing sub-circuit, a storing sub-circuit and a reading sub-circuit; the control method is characterized by comprising the following steps:

the write-in sub-circuit outputs an input signal provided by an input signal end from a first output signal end and outputs the inverted input signal from a second output signal end under the control of a selection signal end and a first enable signal end;

the storage sub-circuit stores a first output signal provided by the first output signal terminal and a second output signal provided by the second output signal terminal under the control of a first power supply voltage signal terminal, a second power supply voltage signal terminal and a first grid drive signal terminal;

18. The method of claim 17, wherein the write sub-circuit has a first node and a second node, the input signal is transmitted to a first output signal terminal through the first node, and the inverted input signal is transmitted to a second output signal terminal through the second node;