WO2014115245A1

WO2014115245A1 - Semiconductor memory and semi conductor device

Info

Publication number: WO2014115245A1
Application number: PCT/JP2013/051203
Authority: WO
Inventors: 健介篠原
Original assignee: 富士通株式会社
Priority date: 2013-01-22
Filing date: 2013-01-22
Publication date: 2014-07-31

Abstract

The present invention reduces the mounting area of a semiconductor memory used for applications which do not require a high-speed read operation, and moderates an increase in test cost. A semiconductor memory (1) is provided with a pluralit y of word lines, a plurality of bit line pairs, a plurality of memory cells (41) provided corresponding to intersecting sections of the plurality of word lines and the plurality of bit line pairs, a plurality of pre-charge circuits (21a, 21b) provided corresponding to each bit line pair, and a plurality of readout circuits (23) provided corresponding to each bit line pair. In the semiconductor memory (1), a write to and a read from the plurality of memory cells are performed in accordance with a clock signal. Furthermore, in the semiconductor memory (1), a write is performed within a single cycle of the clock signal, and a read is performed throughout a read cycle equivalent to a plurality of clock signal cycles.

Description

Semiconductor memory and semiconductor device

The present invention relates to a semiconductor memory and a semiconductor device.

Static RAM (Static Random Access Memory, SRAM) does not have a refresh operation like DRAM (Dynamic Random Access Memory), can operate at high speed, and is widely used as a memory that can be accessed at high speed.

On the other hand, it has recently been desired to reduce the power consumption of memory. One method for realizing a low power consumption memory is to lower the operating voltage. In a DRAM, when the operating voltage is lowered, the charging voltage of the capacitor provided in the memory cell is lowered. Therefore, the refresh operation is frequently performed, and it is not easy to reduce power consumption. Therefore, the operating voltage of the SRAM is lowered to reduce the power consumption of the memory.

A general SRAM includes a plurality of word lines and a plurality of bit line pairs arranged orthogonally, and a plurality of memory cells arranged corresponding to intersections of the plurality of word lines and the plurality of bit line pairs. Have The SRAM further includes a plurality of column circuits provided corresponding to each bit line pair, a row decoder, a column decoder, a word line driver, and a plurality of column switches. Each column circuit has a sense amplifier, a precharge circuit, an equalizer, a keeper circuit, a bit line pair separation switch, etc. in the case of a differential method that reads using a bit line pair, and uses only one side bit line. In the case of a single-ended method of reading out data, a sense amplifier, a precharge circuit, and the like are included.

High-end processors and the like use an SRAM that has a high operating frequency and that performs writing and reading with a minimum number of cycles. During the read operation of the SRAM, the SRAM cell is accessed, the bit line pair is driven by the drive element inside the SRAM cell to discharge, the data stored in the SRAM cell is read, and the read data is transmitted to the output circuit To do. On the other hand, at the time of the SRAM write operation, the operation is completed by accessing the SRAM cell and writing data in the SRAM cell. In the read operation, the bit line pair is driven by the drive element in the SRAM cell having a small drive capability. Therefore, in the SRAM, the access time is longer in the read operation than in the write operation. For this reason, the speed characteristic of the SRAM generally depends on the read time. In order to shorten the SRAM read time, it is known to reduce the number of SRAM cells connected to the same bit line pair and divide the SRAM cell array into a plurality of layers to form a hierarchical structure. Each array divided into a plurality is called a sub-array.

FIG. 1 is a diagram showing a sub-block including an SRAM sub-array having a conventional hierarchical structure and a local control circuit.

The sub-block 110 has a local control circuit 20 and a pair of

sub-arrays

40a and 40b.

The local control circuit 20 includes a pair of

precharge circuits

21a and 21b, a pair of write

column selection circuits

22a and 22b, and a local output circuit 23.

Each of the pair of

precharge circuits

21a and 21b has a pair of pMOS transistors. A precharge signal PCH is output from the precharge signal generation circuit 141 of the local control signal generation circuit 104 to the gates of the pair of pMOS transistors. When the precharge signal PCH becomes L level, the pair of pMOS transistors of the pair of

precharge circuits

21a and 21b are turned on, and the bit line signals BL and BLB become H level signals.

Each of the pair of write

column selection circuits

22a and 22b is a selection circuit that selects a column when writing to the SRAM cell in accordance with a write column selection signal output from the write column selection circuit 142 of the local control signal generation circuit 104. Have

The local output circuit 23 includes a local readout circuit 31, a first transistor 32, and a second transistor 33. The local read circuit 31 has a sense amplifier that amplifies BLB. The first transistor 32 is an nMOS transistor, and is turned on / off based on the read output signal SOUT output from the local read circuit 31. The second transistor 33 is an nMOS transistor and is turned on / off based on the read column selection signal RCOL output from the read column selection circuit 143 of the local control signal generation circuit 104.

Each of the pair of

subarrays

40a and 40b has a plurality of SRAM cells 41. Each of the SRAM cells 41 has a pair of inverter elements that are cross-connected, and a pair of transfer gates that input / output the input / output signals of the pair of inverter elements as bit line signals BL and BLB, respectively.

The global precharge transistor 106 is a pMOS transistor and is arranged for each global bit line. The global precharge signal GPCH is input to the gate of the global precharge transistor 106. When the global precharge signal GPCH is an L level signal, the global bit line signal applied to the global bit line connected to the drain of the global precharge transistor 106 becomes an H level signal. The global bit line is connected to the output circuit of the SRAM. The global precharge transistor 106 and the corresponding global bit line are arranged one by one in a plurality of columns.

FIG. 2 is a timing chart during the read operation of the SRAM having the hierarchical structure shown in FIG.

The SRAM has a clock signal CLK having a predetermined cycle. The word line signal WL [n] selects a desired word line in synchronization with the clock signal CLK. The precharge signal PCH is generated by the precharge signal generation circuit 141 in synchronization with the clock signal CLK, and is output to the pair of

precharge circuits

21a and 21b. When the precharge signal PCH becomes L level, the pair of pMOS transistors of the pair of

precharge circuits

After the bit line signals BL and BLB become H level signals by the pair of

precharge circuits

21a and 21b, the bit lines BL and BLB vary according to the internal state of the selected SRAM cell 40. In the example shown in FIG. 2, the bit line signal BL is maintained at the H level, and the bit line signal BLB is driven to the L level by the driving element inside the SRAM cell 41.

The local read circuit 31 amplifies the BLB signal and outputs a read output signal SOUT to the gate of the first transistor 32. A read column selection signal RCOL generated in synchronization with the clock signal CLK is output to the gate of the second transistor 33.

The global bit line signal RGBL is precharged for each cycle of the clock signal CLK by a global precharge signal GPCH synchronized with the clock signal CLK. As the global bit line signal RGBL, an inverted signal of the read output signal SOUT when the read column selection signal RCOL is at the H level is output. In the example shown in FIG. 2, the global bit line signal RGBL is driven to the L level when the read output signal SOUT and the column selection signal RCOL are respectively at the H level and the vertically stacked

transistors

32 and 33 are turned on.

Even when the SRAM cells arranged in the SRAM cell array are divided into a plurality of subarrays to form a hierarchical structure, the operation speed of the SRAM is determined not by the writing time but by the reading time. For this reason, various techniques have been proposed to prevent the operating frequency of the SRAM from decreasing due to an increase in the read time.

JP 2012-113775 A JP 2000-123576 A JP 2005-267354 A JP 11-3592 A

However, SRAM may be used for applications where the write time is within a single period of the processor operating clock, but the read time is allowed to be greater than the single period of the processor operating clock. . An example of such a case is a history RAM. The history RAM is a memory that is mounted on a semiconductor device such as a processor and records an operation state of the semiconductor device in order to clarify the cause of the failure when the semiconductor device fails. In the history RAM, the write operation is performed in synchronization with the operation clock signal of the system and within a single cycle of the operation clock signal, and the operation state of the semiconductor device is stored for each cycle of the clock signal. On the other hand, the read operation of the history RAM is not performed when the semiconductor device is operating normally, but is used when analyzing a failure of the semiconductor device, so the read time may be longer than a single cycle of the clock signal. .

When an SRAM is used for applications such as history RAM, there is a problem that the mounting area increases if an SRAM divided into sub-blocks so that the read time is within a single cycle of the clock signal is used. When the SRAM is divided into sub-blocks, a control circuit including a sense amplifier is arranged for each sub-block. Therefore, in order to control the sub-array as the number of SRAM cells included in the sub-array decreases, the control circuit included in the sub-block This is because the number increases.

Further, the SRAM cell array is divided so that the write time is within a single cycle of the clock signal, and the clock signal cycle at the time of writing and the cycle of the clock signal at the time of reading are made different, so that the semiconductor is operated during normal operation. The SRAM can be used for applications such as a history RAM by performing a writing operation at the cycle of the apparatus and reading at a slow cycle that can be read when the cause of the failure is clarified.

However, if the period of the clock signal at the time of writing is different from the period of the clock signal at the time of reading, it is necessary to switch the period of the clock signal when the SRAM function test is performed by the tester after the semiconductor device is manufactured. Become. In order to switch the period between the write operation and the read operation in the function test in the tester, there is a problem that an additional test circuit is required, which increases the area and the test time.

In order to solve the above problems, a semiconductor memory includes a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells provided corresponding to intersections of the plurality of word lines and the plurality of bit line pairs, and . The semiconductor memory includes a plurality of precharge circuits provided corresponding to each bit line pair, and a plurality of read circuits provided corresponding to each bit line pair. In a semiconductor memory, writing and reading to a plurality of memory cells are performed according to a clock signal. In the semiconductor memory, writing is performed within a single cycle of the clock signal, and reading is performed over a reading cycle corresponding to a plurality of cycles of the clock signal.

According to one embodiment, the mounting area of a semiconductor memory used for an application that does not require a high-speed read operation is reduced, and the test cost is suppressed.

FIG. 3 is a diagram showing a sub-block including a sub-array of SRAM having a hierarchical structure and a local control circuit. FIG. 2 is a timing diagram of the SRAM shown in FIG. 1. It is a block diagram of the semiconductor device in which SRAM is mounted. It is a block diagram of SRAM. FIG. 4 is a diagram showing a sub block of an SRAM mounted on the semiconductor device shown in FIG. 3 and its control unit. FIG. 5 is a timing diagram of an SRAM including the sub-block shown in FIG. 4 and its control unit. It is a figure which shows the other example of the sub block of SRAM, and its control part. FIG. 7 is a timing diagram of an SRAM including the sub-block shown in FIG. 6 and its control unit. It is a figure which shows the other example of the sub block of SRAM, and its control part. FIG. 9 is a timing diagram of an SRAM including the sub-block shown in FIG. 8 and its control unit. It is a figure which shows the other example of a counter circuit.

FIG. 3A is a diagram illustrating an example of a semiconductor device on which an SRAM is mounted, and FIG. 3B is a block diagram illustrating an example of an SRAM.

The SRAM 1 is mounted on a semiconductor device 100 that is a processor such as a server, and includes an SRAM cell array 101, a timing generation circuit 102a, a decoder 103, a local control signal generation circuit 104a, and a data input / output circuit 105.

The SRAM cell array 101 has a plurality of subarrays 40 arranged in an array. The timing generation circuit 102a is a logic circuit that generates timing signals such as a clock signal and a write enable signal. The decoder 103 is a selection circuit that selects a single SRAM cell during a read operation and a write operation. The local control signal generation circuit 104 a is a logic circuit that generates a signal for controlling each of the plurality of subarrays 40 via the local control circuit 20 disposed in proximity to each of the plurality of subarrays 40. The data input / output circuit 105 is an input / output circuit that inputs data written to each SRAM cell and outputs data output from each SRAM cell.

FIG. 4 is a diagram showing the sub-block 110 of the SRAM 1 and its control unit.

The local control signal generation circuit 104a is different from the conventional local control signal generation circuit 104 shown in FIG. The mask circuit 10 includes a precharge signal mask circuit 50 and a read column selection signal mask circuit 60. In addition, the timing generation circuit 102 a includes a mask signal generation circuit 70 that generates a mask signal MASK that controls the mask circuit 10.

The precharge signal mask circuit 50 includes a first inverter element 51, an AND element 52, and a second inverter element 53. The first inverter element 51 outputs an inverted signal of the precharge signal PCH output from the precharge signal generation circuit 141. The AND element 52 outputs a signal corresponding to the logical sum of the inverted signal of the precharge signal PCH output from the first inverter element 51 and the mask signal MASK output from the mask signal generation circuit 70. The second inverter element 53 supplies a mask precharge signal MPCH, which is an inverted signal of the signal corresponding to the logical sum of the precharge signal PCH output from the AND element 52 and the mask signal MASK, to the

precharge circuits

21a and 21b. Output.

The precharge signal mask circuit 50 outputs a signal corresponding to the precharge signal PCH as the mask precharge signal MPCH to the

precharge circuits

21a and 21b when the mask signal MASK is an H level signal. Further, when the mask signal MASK is an L level signal, the precharge signal mask circuit 50 sets the mask precharge signal MPCH to an H level signal and turns off the pMOS transistors of the

precharge circuits

21a and 21b.

The read column selection signal mask circuit 60 has an AND element 61. The AND element 61 outputs a mask read column selection signal MRCOL from the read column selection signal RCOL output from the read column selection circuit 143 and the mask signal MASK output from the mask signal generation circuit 70. The mask read column selection signal MRCOL corresponds to a logical sum of the read column selection signal RCOL and the mask read column selection signal MRCOL. When the mask signal MASK is an H level signal, the read column selection signal mask circuit 60 outputs a signal corresponding to the read column selection signal RCOL to the

precharge circuits

21a and 21b as a mask read column selection signal MRCOL. Further, when the mask signal MASK is the L level signal, the read column selection signal mask circuit 60 sets the mask precharge signal MPCH to the L level signal and turns off the second transistor 33.

The mask signal generation circuit 70 includes an AND element 71, a first D flip-flop 72, a second D flip-flop 73, a first NAND element 74, and a second NAND element 75. The mask signal generation circuit 70 generates and outputs a mask signal MASK based on the internal clock signal INT_CLK and the write enable inversion signal MWEO.

The AND element 71 outputs a signal corresponding to the logical sum of the internal clock signal INT_CLK generated by the timing generation circuit 102a and the write enable inversion signal MWEO as the read clock signal RCK. The read clock signal RCK is an L level signal during a write operation, and is a signal corresponding to the internal clock signal INT_CLK during a read operation.

Each of the first D flip-flop 72 and the second D flip-flop 73 is a data flip-flop with a reset terminal. The read clock signal RCK is input to the CK terminal of the first D flip-flop 72. The write enable inversion signal MWEO is input to the RN terminal of the first D flip-flop 72. A signal output from the QB terminal, which is the inverting output terminal of the first D flip-flop 72, is input to the D terminal of the first D flip-flop 72. The output signal of the Q terminal of the first D flip-flop 72 is input to the CK terminal of the second D flip-flop 73. The write enable inversion signal MWEO is input to the RN terminal of the second D flip-flop 73. A signal output from the QB terminal of the second D flip-flop 73 is input to the D terminal of the second D flip-flop 73. The first D flip-flop 72 and the second D flip-flop 73 form a 2-bit asynchronous counter circuit (hereinafter also simply referred to as a counter circuit) that operates in response to the read clock signal RCK.

The first NAND element 74 outputs an inverted signal of the logical sum of the first and second count signals COUNT0 and COUNT1 output from the Q terminals of the first D flip-flop 72 and the second D flip-flop 73 as a mask inversion signal MASK_B. . That is, the first NAND element 74 outputs the L level signal as the mask inversion signal MASK_B when both the first count signal COUNT0 and the second count signal COUNT1 are H level signals. In other cases, the first NAND element 74 outputs the H level signal as the mask inversion signal MASK_B.

The second NAND element 75 outputs the inverted signal of the logical sum of the mask inversion signal MASK_B and the write enable inversion signal MWEO as the mask signal MASK. That is, when the write enable inverted signal MWEO is an H level signal, an inverted signal of the mask inverted signal MASK_B is output as the mask signal MASK, and when the write enable inverted signal MWEO is an L level signal, an H level signal is output. .

The mask signal generation circuit 70 outputs an H level signal as a MASK signal when the write enable inversion signal MWEO is an L level signal. Further, when the write enable inversion signal MWEO maintains the H level over the three cycles of the internal clock signal INT_CLK, the mask signal generation circuit 70 converts the L level signal into the mask signal MASK according to the internal clock signal INT_CLK in the last cycle. Output as.

FIG. 5 is a timing chart of the SRAM 1.

The internal clock signal INT_CLK is output by repeating the H level signal and the L level signal at a constant cycle. The write enable inversion signal MWEO is output as an H level signal over three cycles of the internal clock signal INT_CLK. When the write enable inversion signal MWEO is an H level signal, the SRAM 1 is in a read operation state, and when the write enable inversion signal MWEO is an L level signal, the SRAM 1 is in a write operation state.

The read clock signal RCK becomes a signal corresponding to the internal clock signal INT_CLK in three cycles of the internal clock signal INT_CLK in which the write enable inversion signal MWEO is an H level signal. The read clock signal RCK is an L level signal when the write enable inversion signal MWEO is an L level signal.

When the write enable inversion signal MWEO is an L level signal, the L level signal is input to the RN terminals of the first D flip-flop 72 and the second D flip-flop 73, and the first D flip-flop 72 and the second D flip-flop 73 are in the reset state. become. Therefore, the output signals at the Q terminals of the first D flip-flop 72 and the second D flip-flop 73 are both L level signals, and the output signal of the counter circuit is (00).

When the write enable inversion signal MWEO is an H level signal, the output signal of the counter circuit is counted up in the order of (01), (10), and (11) in response to the rise of the read clock signal RCK. When the output signal of the counter circuit becomes (11), the mask inversion signal MASK_B becomes an L level signal.

The mask signal MASK becomes an H level signal when the mask inversion signal MASK_B becomes an L level signal and the write enable inversion signal MWEO becomes an H level signal.

The precharge signal PCH becomes an L level signal according to the internal clock signal INT_CLK. On the other hand, the mask precharge signal MPCH becomes an L level signal according to the internal clock signal INT_CLK when the mask signal MASK becomes an H level signal.

The read column selection signal RCOL becomes an H level signal according to the internal clock signal INT_CLK. On the other hand, the mask read column selection signal MRCOL becomes an H level signal in response to the internal clock signal INT_CLK when the mask signal MASK becomes an H level signal.

Since the bit line signals BL and BLB are not precharged until the mask precharge signal MPCH becomes an L level signal, they are not precharged when the output signals of the counter circuit are (01) and (10). When the output signals of the counter circuit are (01) and (10), since the bit line signals BL and BLB are not precharged, the bit line signals BL and BLB are discharged over three cycles of the internal clock signal INT_CLK. . The

precharge circuits

21a and 21b are enabled in response to the rising edge of the internal clock signal INT_CLK in the third cycle.

The read output signal SOUT gradually rises from an L level signal to an H level signal according to BLB.

Since the second transistor 33 is not turned on until the read column selection signal MRCOL becomes an H level signal, the global bit line signal RGBL is not read when the output signal of the counter circuit is (01) and (10). Regardless of the state, the global bit line signal RGBL does not change. The global bit line signal RGBL changes according to the state of SOUT at that time according to the rising edge of the internal clock signal INT_CLK in the third cycle.

The read operation of the SRAM 1 is executed over three cycles of the internal clock signal INT_CLK.

FIG. 6 is a diagram showing another example of the SRAM sub-block 110 and its control unit.

The timing generation circuit 102b is different from the timing generation circuit 102a shown in FIG. 4 in that it has a mask signal generation circuit 70 ′ instead of the mask signal generation circuit 70.

The mask signal generation circuit 70 ′ is different from the mask signal generation circuit 70 in that an inverter element 76 is inserted between the Q terminal of the first D flip-flop 72 and one input terminal of the first NAND element 74.

FIG. 7 is a timing chart of the SRAM equipped with the timing generation circuit 102b shown in FIG.

When the write enable inversion signal MWEO maintains the H level for two cycles of the internal clock signal INT_CLK, the mask signal generation circuit 70 ′ uses the L level signal as the mask signal MASK according to the internal clock signal INT_CLK in the last cycle. Output.

The read operation of the SRAM equipped with the timing generation circuit 102b is executed over two cycles of the internal clock signal INT_CLK.

FIG. 8 is a diagram showing still another example of the SRAM sub-block 110 and its control unit.

The timing generation circuit 102 c is different from the timing generation circuit 102 a shown in FIG. 4 in that it has a mask signal generation circuit 70 ″ instead of the mask signal generation circuit 70.

The mask signal generation circuit 70 ″ is different from the mask signal generation circuit 70 in that it has a 2-bit match circuit 80 instead of the first NAND element 74.

The 2-bit match circuit 80 includes a first XOR element 81, a second XOR element 82, and an OR element 83. The first XOR element 81 outputs a signal corresponding to the exclusive OR of the first setting signal SET0 input from the outside of the semiconductor device 100 and the first count signal COUNT0. The second XOR element 82 outputs a signal corresponding to the exclusive OR of the second setting signal SET1 input from the outside of the semiconductor device 100 and the second count signal COUNT1. The NOR element 83 outputs a signal corresponding to the logical sum of the output signal of the first XOR element and the output signal of the first XOR element.

The 2-bit match circuit 80 outputs an L level signal when the first count signal COUNT0 and the first setting signal SET0 have the same value, and the second count signal COUNT1 and the second setting signal SET1 have the same value. To do. In the timing generation circuit 102c, the read time can be set to a desired clock cycle by setting the first and second set values SET0 and SET1 to desired values.

FIG. 9 is a timing chart of the SRAM equipped with the timing generation circuit 102c shown in FIG.

Since the SRAM includes the

timing generation circuit

102a, 102b or 102c and the local control signal generation circuit 104a, the write operation and the read operation are controlled by a single clock signal, and the read operation is performed over a plurality of cycles of the clock signal. It can be carried out. Since the read operation can be performed over a plurality of cycles of the clock signal, the number of SRAM cells included in the SRAM sub-array can be determined in consideration only of the write time, and the SRAM cell is more than in the case of considering the read time. Can be reduced. For example, when the number of subarrays dividing the SRAM array is reduced to 1/4, the area of the SRAM is reduced by about 30%.

Hereinafter, other embodiments will be described.

In the present specification, the present invention is described by taking an SRAM as an example, but the present invention may be applied to other semiconductor memories in which a read time is longer than a write time.

The counter circuits of the mask

signal generation circuits

70, 70 ′ and 70 ″ formed by the first D flip-flop 72 and the second D flip-flop 73 are 2-bit counter circuits, but are counter circuits of 3 bits or more. May be. The counter circuit may be a synchronous counter instead of an asynchronous counter circuit.

FIG. 10 is a diagram showing an example of the synchronization counter.

The signal input to the CK terminal of the second D flip-flop 73 of the counter circuit of the mask

signal generation circuits

70, 70 ′ and 70 ″ is a signal output from the QB terminal of the first D flip-flop 72. Therefore, a timing difference is generated between the signals COUNT0 and COUNT1 output from the first D flip-flop 72 and the second D flip-flop 73, respectively. By adopting the synchronous counter shown in FIG. 10, the timing difference is eliminated, and the signals COUNT0 and COUNT1 can be output simultaneously in synchronization with RCK, so that higher speed operation is possible.

3, 5, and 7, the internal circuits of the precharge signal mask circuit 50, the read column selection signal mask circuit, and the mask

signal generation circuits

70, 70 ′, and 70 ″ are examples of circuit configurations. A circuit configuration may be adopted. For example, a NAND element may be arranged in place of the AND element 52 and the second inverter element 53 of the precharge signal mask circuit 50. Further, by inserting a latch circuit between the output terminal of the AND element 71 of the mask signal generation circuit 70 and the CK terminal of the first D flip-flop 72, the read operation cycle of the SRAM 1 is set to four cycles of the internal clock signal INT_CLK. It may be.

Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

1 SRAM
DESCRIPTION OF SYMBOLS 10 Mask circuit 20

Local control circuit

40, 40a, 40b Subarray 41 SRAM cell 50 Precharge signal mask circuit 60 Read column selection signal mask circuit 70, 70 ', 70''Mask signal generation circuit 100 Semiconductor device 101

SRAM cell array

102a, 102b , 102c Timing generation circuit 103

Decoder

104, 104a Local control signal generation circuit 105 Data input / output circuit 110 Sub-block

Claims

Multiple word lines,
Multiple bit line pairs;
A plurality of memory cells provided corresponding to the intersections of the plurality of word lines and the plurality of bit line pairs;
A plurality of precharge circuits provided corresponding to each bit line pair;
A plurality of read circuits provided corresponding to each bit line pair,
Writing to and reading from the plurality of memory cells are performed according to a clock signal,
The writing is performed within a single period of the clock signal, and the reading is performed over a reading period corresponding to a plurality of periods of the clock signal.
A semiconductor memory characterized by that.
2. The semiconductor memory according to claim 1, wherein at the time of reading, the plurality of precharge circuits and the plurality of read circuits are enabled in accordance with a last clock signal of the read cycle.
The semiconductor memory according to claim 1, wherein the read cycle is variable.
4. The plurality of bit line pairs according to claim 1, wherein the plurality of bit line pairs are local bit line pairs connected to a global bit line to which a plurality of bit line pairs arranged in the same column are connected. Semiconductor memory.
A semiconductor device on which the semiconductor memory according to any one of claims 1 to 4 is mounted.