CN114236973B - Method for improving tolerance of splicing process window - Google Patents
Method for improving tolerance of splicing process window Download PDFInfo
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- CN114236973B CN114236973B CN202111526095.7A CN202111526095A CN114236973B CN 114236973 B CN114236973 B CN 114236973B CN 202111526095 A CN202111526095 A CN 202111526095A CN 114236973 B CN114236973 B CN 114236973B
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000000926 separation method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
Abstract
The invention provides a method for improving tolerance of a splicing process window, which comprises the following steps: cutting a target graph to obtain a plurality of initial graphs, wherein each initial graph comprises a plurality of sub-graphs; performing compensation processing on the positions of the cutting lines of each initial graph to obtain a plurality of corrected graphs; the correction pattern is made on a plurality of mask plates; and sequentially exposing the wafer by using a plurality of mask plates, wherein cutting lines of every two adjacent correction patterns exposed on the wafer completely coincide. According to the method and the device, the initial pattern is directly compensated at the position of the cutting line, then the wafer is exposed by utilizing the overlapping of the cutting line on the compensated corrected pattern, the condition of breakage and offset of the initial pattern at the splicing position is avoided, the dislocation of the initial pattern at the splicing position and the tolerance of mutual separation are improved, the accuracy and the reliability of the splicing exposure process are ensured, the overlay precision is improved, and the product yield is improved.
Description
Technical Field
The application relates to the technical field of splicing processes, in particular to a method for improving tolerance of a splicing process window.
Background
Because of the limitation of the maximum exposure field of the lithography machine, the maximum exposure size of the lithography machine is 26×33mm, but there are many single chips with sizes exceeding the size, for example, the area of the large CIS chip to be exposed exceeds 26×33mm, so that the geometric pattern on the mask cannot be transferred onto the CIS wafer through one exposure, and then a stitching exposure process is generally required, and multiple exposures are required to stitch the geometric pattern on the mask onto the wafer. However, the existing stitching exposure process has the problems of geometric figure broken lines and/or offset between adjacent exposure areas, so that the number of defective products is increased.
Disclosure of Invention
The application provides a method for improving tolerance of a splicing process window, which can solve the problems of disconnection and/or deviation of target patterns of adjacent exposure areas in a splicing exposure process.
In one aspect, an embodiment of the present application provides a method for improving tolerance of a splicing process window, including:
a first step of: cutting the target graph to obtain a plurality of initial graphs, wherein each initial graph comprises a plurality of sub-graphs with the same or different patterns;
and a second step of: performing compensation processing on the cutting line positions of the periphery of each initial graph to obtain a plurality of corrected graphs;
and a third step of: making the corrected graph on a mask plate;
fourth step: and sequentially exposing the wafer by using a mask plate with the corrected patterns according to the pattern of the target patterns before cutting, wherein cutting lines of every two adjacent corrected patterns exposed on the wafer are completely overlapped, and the area outside the cutting lines of each corrected pattern is a repeated exposure area.
Optionally, in the method for improving tolerance of the stitching process window, in the second step, in the inner side or the outer side of the cutting line around each initial pattern, the sub-patterns at the edge of the cutting line are subjected to extension and widening processing to obtain the corrected pattern.
Optionally, in the method for improving tolerance of the stitching process window, in the second step, the sub-patterns on the edge of the cutting line are extended and widened outside and inside the cutting line around the initial pattern to obtain the corrected pattern.
Optionally, in the method for improving tolerance of the stitching process window, the length of the sub-pattern extension is greater than 0 and less than the total length of the initial pattern.
Optionally, in the method for improving tolerance of the stitching process window, a width of the sub-pattern widening is greater than 0 and smaller than a distance between the sub-pattern and an adjacent sub-pattern in the same initial pattern.
Optionally, in the method for improving tolerance of the splicing process window, the third step includes: and making the correction patterns of a plurality of different patterns on the same mask plate, or making the correction patterns of a plurality of different patterns on different mask plates.
Optionally, in the method for improving tolerance of the splicing process window, the sub-graph includes: a line pattern and a hole pattern.
The technical scheme of the application at least comprises the following advantages:
according to the method and the device, the initial pattern is directly compensated at the position of the cutting line, then the wafer is exposed by utilizing the overlapping of the cutting line on the compensated corrected pattern, the condition of breakage and offset of the initial pattern at the splicing position is avoided, the dislocation of the initial pattern at the splicing position and the tolerance of mutual distance are improved, the accuracy and the reliability of the splicing exposure process are ensured, the integrity of the pattern transferred to the wafer by the target pattern is ensured, the overlay precision is improved, and the product yield is improved.
Furthermore, the method for improving the tolerance of the splicing process window does not increase an additional mask plate or an additional exposure process, so that the problems of disconnection and deviation of the target graph at the splicing position can be solved, the working efficiency is improved, and the production cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for improving tolerance of a splicing process window according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a target graphic of an embodiment of the present invention;
FIG. 3 is a schematic illustration of an initial diagram of an embodiment of the present invention;
FIGS. 4 (a), 4 (b) and 4 (c) are schematic diagrams of three correction patterns according to embodiments of the present invention;
FIG. 5 is a schematic view of a wafer exposed by a method for improving the window tolerance of a tiled process according to an embodiment of the present invention;
wherein reference numerals are as follows:
100-target pattern, 101-cutting line, 110-initial pattern, 111-sub pattern, 120-corrected pattern, 200-repeated exposure area.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
In one aspect, an embodiment of the present application provides a method for improving tolerance of a splicing process window, referring to fig. 1, fig. 1 is a flowchart of a method for improving tolerance of a splicing process window according to an embodiment of the present invention, where the method for improving tolerance of a splicing process window includes:
a first step S10: cutting the target graph to obtain a plurality of initial graphs, wherein each initial graph comprises a plurality of sub-graphs with the same or different patterns;
a second step S20: performing compensation processing on the cutting line positions of the periphery of each initial graph to obtain a plurality of corrected graphs;
third step S30: making the corrected graph on a mask plate;
fourth step S40: and sequentially exposing the wafer by using a mask plate with the corrected patterns according to the pattern of the target patterns before cutting, wherein cutting lines of every two adjacent corrected patterns exposed on the wafer are completely overlapped, and the area outside the cutting lines of each corrected pattern is a repeated exposure area.
Referring to fig. 2-5, a detailed description of the method for improving tolerance of the splicing process window is provided.
First, as shown in fig. 2 and 3, the target pattern 100 is cut to obtain a plurality of initial patterns 110, wherein each of the initial patterns 110 includes a plurality of sub patterns 111 of the same or different patterns. Specifically, the sub-graph 111 includes: a line pattern and a hole pattern. The embodiment specifically describes the method for improving the tolerance of the splicing process window by taking a line graph as an example. The type and pattern of the sub-graphic 111 on the initial graphic 110 are not limited in this application.
Next, referring to fig. 4 (a), 4 (b) and 4 (c), fig. 4 (a), 4 (b) and 4 (c) are schematic diagrams of three correction patterns according to an embodiment of the present invention, compensation processing is performed on the positions of the cutting lines 101 around each of the initial patterns 110 to obtain a plurality of correction patterns 120. Specifically, in this embodiment, as shown in fig. 4 (a), the sub-patterns 111 at the edge of the cutting line may be extended and widened outside the cutting line 101 around each of the initial patterns 110 to obtain the corrected patterns 120; alternatively, as shown in fig. 4 (b), the sub-patterns 111 at the edges of the cut lines 101 are extended and widened inside the cut lines 101 around each of the initial patterns 110 to obtain the corrected patterns 120; alternatively, as shown in fig. 4 (c), the sub-patterns 111 at the edges of the cut lines 101 are extended and widened outside and inside the cut lines 101 around each of the initial patterns 110 to obtain the corrected patterns 120. The present invention is equivalent to performing compensation processing on the parallel direction and the vertical direction of each cutting line of each initial pattern 110.
Preferably, as shown in fig. 4 (c), the sub-graphic 111 extends a length greater than 0 and less than the total length a of the initial graphic 110. The sub-pattern 111 widens more than 0 and less than the interval b between the sub-pattern 111 and the adjacent sub-pattern 111 in the same initial pattern 110. The sub-patterns 111 of the cut line edge are extended and widened outside or inside the cut line 101 of the circumference of each of the preliminary patterns 110, as well as the sub-patterns 111 are extended by a length greater than 0 and less than the total length a of the preliminary patterns 110. The sub-pattern 111 widens more than 0 and less than the interval b between the sub-pattern 111 and the adjacent sub-pattern 111 in the same initial pattern 110.
Then, the correction pattern 120 is formed on the mask plate. Specifically, in this embodiment, the plurality of corrected patterns 120 with different patterns may be formed on the same mask, or the plurality of corrected patterns 120 with different patterns may be formed on different masks. In this embodiment, the same pattern on the wafer that needs to be repeatedly exposed can be repeatedly used for one mask plate, so as to save mask resources.
Finally, as shown in fig. 5, according to the pattern of the target pattern 100 before dicing, the wafer is sequentially exposed by using the mask plate with the corrected pattern 120, so that a complete target pattern 100 can be obtained on the wafer. Wherein the dicing lines 101 of every two adjacent correction patterns 120 exposed on the wafer completely overlap and the area outside the dicing lines of each correction pattern 120 is a repeated exposure area 200. Specifically, in this embodiment, the sub-patterns 111 at the edges of the cut line are extended and widened outside and inside the cut line 101 around each of the initial patterns 110 using fig. 5. Similarly, the sub-patterns 111 at the edge of the cut line may be extended and widened in the case where each of the initial patterns 110 is located on one side of the outer side or the inner side of the cut line 101 around the periphery. According to the method, the initial pattern 110 is directly compensated (extended and widened) at the position of the cutting line 101, then the wafer is exposed by utilizing the superposition of the cutting line 101 on the compensated correction pattern 120, the condition of breakage and offset of the initial pattern at the splicing position is avoided, the dislocation and mutual far tolerance of the initial pattern 110 at the splicing position are improved, the accuracy and reliability of the splicing exposure process are ensured, the integrity of the pattern transferred onto the wafer by the target pattern 100 is ensured, the overlay precision is also improved, and the product yield is increased. Furthermore, the method for improving the tolerance of the splicing process window does not increase an additional mask plate or an additional exposure process, so that the problems of disconnection and deviation of the target graph at the splicing position can be solved, the working efficiency is improved, and the production cost is saved.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (3)
1. A method for improving tolerance of a splicing process window, comprising:
a first step of: cutting the target graph to obtain a plurality of initial graphs, wherein each initial graph comprises a plurality of sub-graphs with the same or different patterns;
and a second step of: extending and widening the sub-patterns at the edges of the cutting lines at the inner side and/or the outer side of the cutting lines around each initial pattern to obtain corrected patterns; wherein the sub-graphic extends a length greater than 0 and less than the total length of the initial graphic; the widened width of the sub-graph is larger than 0 and smaller than the interval between the sub-graph and the adjacent sub-graph in the same initial graph;
and a third step of: making the corrected graph on a mask plate;
fourth step: and sequentially exposing the wafer by using a mask plate with the corrected patterns according to the pattern of the target patterns before cutting, wherein cutting lines of every two adjacent corrected patterns exposed on the wafer are completely overlapped, and the area outside the cutting lines of each corrected pattern is a repeated exposure area.
2. The method of claim 1, wherein the third step comprises: and making the correction patterns of a plurality of different patterns on the same mask plate, or making the correction patterns of a plurality of different patterns on different mask plates.
3. The method of claim 1, wherein the sub-graph comprises: a line pattern and a hole pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111526095.7A CN114236973B (en) | 2021-12-14 | 2021-12-14 | Method for improving tolerance of splicing process window |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111526095.7A CN114236973B (en) | 2021-12-14 | 2021-12-14 | Method for improving tolerance of splicing process window |
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| Publication Number | Publication Date |
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| CN114236973A CN114236973A (en) | 2022-03-25 |
| CN114236973B true CN114236973B (en) | 2024-03-08 |
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| CN202111526095.7A Active CN114236973B (en) | 2021-12-14 | 2021-12-14 | Method for improving tolerance of splicing process window |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194105B1 (en) * | 1999-05-20 | 2001-02-27 | Tower Semiconductor Ltd. | Method of forming reticle from larger size reticle information |
| CN1782867A (en) * | 2004-11-29 | 2006-06-07 | 富士通株式会社 | Reticle and method of fabricating semiconductor device |
| CN102981356A (en) * | 2012-12-14 | 2013-03-20 | 京东方科技集团股份有限公司 | Method for reducing mask board splicing errors |
| CN110221515A (en) * | 2018-03-02 | 2019-09-10 | 中芯国际集成电路制造(上海)有限公司 | The production method of optical adjacent correction method and mask plate |
| CN111443566A (en) * | 2020-05-08 | 2020-07-24 | 京东方科技集团股份有限公司 | Mask plate |
| CN111736422A (en) * | 2019-03-25 | 2020-10-02 | 上海微电子装备（集团）股份有限公司 | Mask plate and splicing exposure method |
-
2021
- 2021-12-14 CN CN202111526095.7A patent/CN114236973B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194105B1 (en) * | 1999-05-20 | 2001-02-27 | Tower Semiconductor Ltd. | Method of forming reticle from larger size reticle information |
| CN1782867A (en) * | 2004-11-29 | 2006-06-07 | 富士通株式会社 | Reticle and method of fabricating semiconductor device |
| CN102981356A (en) * | 2012-12-14 | 2013-03-20 | 京东方科技集团股份有限公司 | Method for reducing mask board splicing errors |
| CN110221515A (en) * | 2018-03-02 | 2019-09-10 | 中芯国际集成电路制造(上海)有限公司 | The production method of optical adjacent correction method and mask plate |
| CN111736422A (en) * | 2019-03-25 | 2020-10-02 | 上海微电子装备（集团）股份有限公司 | Mask plate and splicing exposure method |
| CN111443566A (en) * | 2020-05-08 | 2020-07-24 | 京东方科技集团股份有限公司 | Mask plate |
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| CN114236973A (en) | 2022-03-25 |
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