CN114236514A - Digital calibration circuit and method for time-amplitude conversion TOF detector - Google Patents

Digital calibration circuit and method for time-amplitude conversion TOF detector Download PDF

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CN114236514A
CN114236514A CN202111578048.7A CN202111578048A CN114236514A CN 114236514 A CN114236514 A CN 114236514A CN 202111578048 A CN202111578048 A CN 202111578048A CN 114236514 A CN114236514 A CN 114236514A
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calibration
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weight factor
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CN114236514B (en
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陆皓琛
徐跃
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Nanjing University of Posts and Telecommunications
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Nanjing University of Posts and Telecommunications
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Abstract

The invention relates to a digital calibration circuit and a digital calibration method for a time-amplitude conversion TOF detector, wherein the calibration circuit comprises a parameter presetting module, a weight factor extracting module and a weight factor calibration module, the output end of the parameter presetting module is connected with the input end of the weight factor extracting module, and the output end of the weight factor extracting module is connected with the weight factor calibration input end module. On the premise of ensuring that the filling factor of the pixel unit and the array integration level meet the array detection requirement, the invention simplifies the calibration time sequence to the maximum extent, reduces the circuit area, reduces the power consumption and the time delay of the circuit and obviously improves the calibration precision.

Description

Digital calibration circuit and method for time-amplitude converting TOF detector
Technical Field
The invention relates to the technical field of photon Time of Flight (TOF) detection, in particular to a Time-amplitude conversion-based TOF array detection digital calibration circuit and method.
Background
The TOF detection is divided into a direct detection mode and an indirect detection mode, wherein the direct TOF detection depends on the flight time of photons, the time measurement precision does not change obviously along with the increase of the test distance, and the performance is stable, so that the direct TOF detection technology has wide application prospects in the aspects of laser ranging, 3D imaging and the like.
The TOF array detection imaging chip based on the direct TOF detection technology mainly adopts a time-to-digital conversion (TDC) circuit to obtain high time resolution and a large measurement range, but generally needs a plurality of delay units, D flip-flops and logic gate circuits, and is not suitable for pixel units for high-density array detection. The time-amplitude conversion (TAC) circuit is simpler in structure and lower in power consumption, meets various requirements of the array detection reading circuit, and simultaneously needs to be matched with a subsequent analog-to-digital conversion (ADC) circuit for quantitative output.
The TAC circuit is essentially different in voltage value obtained by time integration on capacitors in the circuit corresponding to different photon flight times, and then the voltage value is uploaded to an upper computer after analog-to-digital conversion by the ADC circuit. The TOF array detection comprises a plurality of pixel units, and the TAC circuit in each pixel unit comprises capacitors with the same size. Layout parasitic capacitance, process angle and other factors put high requirements on the matching of a large number of capacitors, and capacitance mismatch of each pixel unit in TOF array detection can cause detection misalignment.
The traditional analog domain method for improving the matching of the TAC circuit in the array detection mainly introduces feedback calibration, a switch and a large number of logic circuits to adjust the capacitance and the current in the TAC circuit, but the addition of the circuits can also bring the problems of high power consumption, high time delay, reduction of the filling factor of a pixel unit and the like, and the addition of a large number of front-end circuits makes the advantages of the method compared with the TDC circuit unobvious.
Disclosure of Invention
In order to solve the problems of insufficient calibration precision, high power consumption, high time delay, reduced pixel unit filling factor and the like in the process of calibrating a detection value by a TOF array detection analog domain compensation circuit based on time-amplitude conversion, the invention provides a digital circuit calibration circuit for calibrating in a digital domain and a calibration method thereof.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the present invention is a digital calibration circuit and method for a time-amplitude converted TOF array detector, the digital calibration circuit comprising: the device comprises a parameter presetting module, a weight factor extracting module and a weight factor calibrating module. The output end of the parameter presetting module is connected with the input end of the weight factor extracting module, and the output end of the weight factor extracting module is connected with the weight factor calibrating input end module. The external input signals of the parameter presetting module comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimal, and the output end of the parameter presetting module inputs the delay selection signal out _ latency, the integer precision determining signal out _ integer and the decimal precision determining signal out _ decimal to the weight factor extraction module. The external input signals of the weight factor extraction module comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc _ value, an integer result signal result _ integer and a decimal result signal result _ decimal which are output to the weight factor calibration module, and a module completion signal done. The input signals of the weighting factor calibration module comprise an external clock signal clk, a reset signal rst _ n and an analog-to-digital conversion signal adc _ value, and an integer result signal integer _ verify and a decimal result signal decimamal _ verify of the output end of the weighting factor calibration module are connected to the external output end.
The function of the parameter presetting module is to set the precision and performance of the whole digital calibration circuit, and belongs to the preparation stage of digital calibration. The externally input operation mode selection signal mode _ select is an enable signal, and when the signal is at a low level, the parameter presetting module operates. The external input clock signal clk and the reset signal rst _ n determine the calibration period of the whole digital calibration circuit, so that the digital calibration circuit can better match with the whole array detection system. The external input signal set _ win is a periodic window signal with fixed width, the delay time selection signal latency, the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal which are externally input are counted in the window signal set _ win through a clock signal clk, the area and the power consumption of the digital calibration circuit are directly determined by the delay time selection signal latency in the digital calibration circuit, and the precision of the digital calibration circuit can be determined by the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal. Since the three signals are directly input from the outside and can control the frequencies of the three signals, different circuit areas, power consumption and precision required by different array detection applications can be controlled by different values counted in the window signal. And finally, connecting the output delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimal obtained by counting to a weight factor extraction module.
The function of the weight factor extraction module is to find the deviation between the actual value and the ideal value of all the pixel units, which belongs to the key stage of digital calibration. The delay selection signal out _ latency, the integer precision determination signal out _ integer and the fractional precision determination signal out _ decimal which are input into the weighting factor extraction module by the parameter presetting module determine the area and the precision of the whole digital calibration circuit. The external input clock signal clk, the reset signal rst _ n and the mode selection signal mode _ select are consistent with the parameter presetting module, the clock and the reset signal enable the weighting factor extraction module to be matched with the whole array detection system module in time sequence, and meanwhile, the weighting factor extraction module can work only when the mode selection signal mode _ select is at a high level. The weight factor extraction module can perform linear regression according to time sequence after working, and the linear regression comprises the following main steps: enabling each pixel unit to work three times before formal array detection, sending the TAC circuit actual output values of each pixel unit, which are different for three times, to a weight factor extraction module through an analog-to-digital conversion signal adc _ value, fitting the actual voltage value of each pixel unit TAC circuit working in a full scale to enable the TAC circuit to have the ideal high linearity characteristic of the TAC circuit, and finally storing the TAC circuit to finish linear regression once. The secondary linear regression comprises the following main steps: after the actual voltage value of each pixel unit in full-scale operation is obtained, due to the characteristic of high linearity of the TAC circuit, the ideal threshold signal threshold input from the outside and the actual value of each pixel unit are subjected to linear operation, and a weight factor composed of an integer result signal result _ integer and a decimal result signal result _ decimal at the output end of each pixel unit is obtained on the premise of presetting the size and precision of the circuit, and is stored in the storage circuit. And when the secondary linear regression is finished, the weight factor extraction module generates a module completion signal done at the output end while finishing the work, and the high level is effective and used for enabling the weight factor calibration module to work.
The function of the weight factor calibration module is to perform linear operation on the detection value of each pixel unit and the corresponding weight factor when formal array detection is performed after the weight factor is successfully extracted, so that the purpose of digital calibration is achieved. Once the signal done input by the weight factor extraction module is changed into high level, the weight factor calibration module starts to work. The external input clock signal clk and the reset signal rst _ n are consistent with the weight factor extraction module, the clock and the reset signal enable the weight factor calibration module to be matched with the whole array detection system in time sequence, the external input analog-to-digital conversion signal adc _ value sequentially sends real-time detection values of all pixel units to the weight factor calibration module, the weight factors of all the pixel units input by the weight factor extraction module and actual detection values are subjected to final digital calibration, and finally calibrated array detection values are composed of output end integer result signals integer _ verify and decimal result signals decimall _ verify and are transmitted to an upper computer for data processing.
The invention discloses a digital calibration method for a time-amplitude conversion TOF array detector, which comprises the following steps:
in the first step, under the control of a logic circuit, photon flight time analog signals of each pixel unit in the array detector are converted into digital signals. Under the control of the logic circuit, photon flight time analog signals of each pixel unit in array detection are converted into digital signals through an ADC (analog to digital converter), namely photon flight time corresponding to capacitor voltage in a TAC (TAC) circuit of each pixel unit in TOF (time of flight) array detection is subjected to sequential analog-to-digital conversion according to the sequence of each pixel unit in the array.
And secondly, the parameter presetting module works. And when the working mode selection signal is at a low level, the parameter presetting module works. The period, the area and the calibration precision of the whole digital calibration circuit are determined through an externally input signal, so that the index and the performance of the digital calibration circuit are controlled.
And thirdly, performing linear regression by the weight factor extraction module. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times in advance, fitting the actual voltage value of the TAC circuit of each pixel unit in full-scale work through the actual output of the TAC circuit of each pixel unit three times, enabling the TAC circuit to have ideal high-linearity characteristics, and finally storing the TAC circuit after analog-to-digital conversion through a storage circuit.
And fourthly, performing secondary linear regression by the weight factor extraction module. The secondary linear regression comprises the following main steps: the whole digital calibration circuit aims to find the difference between an actual value and an ideal value during each array detection, and because the third step obtains the actual voltage value of each pixel unit in full-scale operation and the ideal value of each pixel unit is known, the ideal value and the actual value are linearly calculated according to the sequence of detecting each pixel unit by the array under the control of the digital logic circuit, and finally the weight factor corresponding to each pixel unit in the array detection is obtained and stored in the circuit.
And fifthly, the array detection normally works. And fourthly, after the weight factors are successfully extracted, a signal is sent to a weight factor calibration module sending module to complete the signal, the high level is effective, at the moment, the weight factor calibration module works, namely ADC quantization data of the pixel units are sent to the weight factor calibration module in sequence when the array detection normally works, the module carries out linear digital calibration on the actual value and the corresponding weight factors when reading in the actual value of one pixel unit in sequence, and finally the array detection value obtained through calibration is sent to an upper computer for data processing.
The invention has the beneficial effects that:
compared with the method that feedback calibration, a switch and a large number of logic circuits are introduced in an analog domain to adjust the capacitance and the current in the TAC circuit, the method improves the filling factor of each pixel unit in array detection, enhances the stability of the array detection, and has the characteristics of low time delay and low power consumption.
Compared with the traditional analog circuit which introduces a complex feedback calibration circuit, the parameter presetting module included in the invention can realize real-time adjustment of calibration precision and circuit area size, and can adjust the calibration period through external signals, so that the digital calibration module has the characteristics of controllability and flexibility.
According to the invention, the weight factors required by calibration are extracted once and stored in the circuit before formal calibration, and only linear model calculation needs to be repeated with the array detection during normal work, so that the calibration circuit has a simple structure and low hardware consumption.
The digital calibration result of the invention improves the calibration accuracy by combining the integer and the decimal, and the whole digital calibration module has high stability and strong anti-interference capability due to the characteristic of a large signal of a digital signal.
Drawings
Fig. 1 is a schematic diagram of a pixel unit according to the present invention.
FIG. 2 is a flow chart of the method steps of the present invention.
FIG. 3 is a schematic diagram of the first and second linear regression obtained by the weight factor extraction module according to the present invention.
Fig. 4 is a hardware circuit framework diagram of the present invention.
Fig. 5 is a timing diagram of the operation of the present invention.
FIG. 6 is a timing verification diagram of the present invention.
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary.
As shown in fig. 1, the schematic diagram of the pixel unit of the digital calibration circuit and method of the present invention, the whole pixel unit mainly includes a TOF photon detecting device and a TAC circuit. When a photon is detected by the photon detection device, the corresponding TAC circuit generates a TOF voltage value. The TOF voltage values corresponding to different photon arrival times are different, under an ideal condition, the photon arrival times and the TOF voltage are in a linear relation, under an actual condition, due to the fact that an analog circuit has the influence of parasitic capacitance and the like, the TOF actual voltage value has the problem that the TOF actual voltage value is smaller than the ideal voltage value and is nonlinear, and the problem directly causes that an array detector cannot accurately detect the TOF voltage value and the TOF actual voltage value are infinitely approximate to an ideal curve, so that false detection of the array detector is avoided.
The core of the whole digital calibration circuit is a weight factor extraction module, and the weight factor extraction module consists of primary and secondary linear regression. As shown in fig. 3, the abscissa represents the photon flight time, and the ordinate represents the voltage digital quantity corresponding to the pixel unit passing through the analog-to-digital conversion circuit at each time point, and theoretically, the photon flight time is in direct proportion to the voltage, i.e., corresponds to an ideal value after quadratic regression. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times in advance, namely t1, t2 and t3, fitting the actual voltage value of the TAC circuit of each pixel unit in full-scale work through the TAC circuit actual voltage output values of the pixel units which are different three times, storing the actual voltage value in the circuit, and finishing the linear regression. At this time, the difference between the actual value and the ideal value of the TAC circuit in the full-scale working process is only one linear weight factor, and the secondary linear regression step is as follows: and performing linear operation on an ideal value input by an external circuit and an actual value of the pixel unit under the conditions of calibration precision and the like defined by the parameter presetting module, wherein the final result after the operation is the weight factor of a single pixel unit to be extracted, and if the NxN array is to be extracted, the process is sequentially performed for NxN times.
As shown in fig. 4, the overall hardware circuitry includes logic control circuitry, array detection circuitry, digital calibration circuitry, and analog-to-digital conversion (ADC) interface circuitry. The array detection circuit comprises N multiplied by N pixel units, wherein the digital calibration circuit consists of three parts, namely a parameter presetting module, a weight factor extracting module and a weight factor calibrating module.
As shown in fig. 5, the calibration circuit of the present invention mainly includes three modules, a parameter presetting module, a weight factor extracting module, and a weight factor calibrating module. According to the three modules, the whole digital calibration circuit time sequence is divided into three stages of parameter presetting, weight factor extraction and weight factor calibration.
In the first stage, the externally input operation mode selection signal mode _ select is an enable signal, and when the signal is at a low level, the parameter presetting module operates. The external input clock signal clk and the reset signal rst _ n determine the calibration period of the whole digital calibration circuit, so that the digital calibration circuit can better match with the whole array detection system. The external input signal set _ win is a periodic window signal with fixed width, the delay time selection signal latency, the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal which are externally input are counted in the set _ win window signal through the clock signal clk, the area and the power consumption of the circuit are directly determined by the delay time selection signal latency in the digital calibration circuit, and the precision of the digital calibration circuit can be determined by the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal. Since the three signals are directly input from the outside and can control the frequencies of the three signals, different circuit areas, power consumption and precision required by different array detection applications can be controlled by different values counted in the window signal. And finally, the output delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimal obtained through counting are sent to a weight factor extraction module.
And in the second stage, after the preset value of the parameter is finished, the weight factor extraction module starts to work. The delay selection signal out _ latency, the integer precision determination signal out _ integer and the fractional precision determination signal out _ decimal which are input into the weighting factor extraction module by the parameter presetting module determine the area and the precision of the whole digital calibration circuit. The external input clock signal clk, the reset signal rst _ n and the mode selection signal mode _ select are consistent with the parameter presetting module, the clock and the reset signal enable the weighting factor extraction module to be matched with the whole array detection system module in time sequence, and meanwhile, the weighting factor extraction module can work only when the mode selection signal mode _ select is at a high level. After the module works, linear regression is carried out according to the time sequence. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times before formal array detection, sending the TAC circuit actual output values of each pixel unit, which are different for three times, to a weight factor extraction module through an analog-to-digital conversion signal adc _ value, fitting the actual voltage value of each pixel unit TAC circuit working in a full scale to enable the TAC circuit to have the ideal high linearity characteristic of the TAC circuit, and finally storing the TAC circuit to finish linear regression once. The secondary linear regression comprises the following main steps: after the actual voltage value of each pixel unit in full-scale operation is obtained, due to the characteristic of high linearity of the TAC circuit, the ideal threshold signal threshold input from the outside and the actual value of each pixel unit are subjected to linear operation, and a weight factor composed of an integer result signal result _ integer and a decimal result signal result _ decimal at the output end of each pixel unit is obtained on the premise of presetting the size and precision of the circuit, and is stored in the storage circuit. And when the secondary linear regression is finished, the weight factor extraction module generates a module completion signal done at the output end while finishing the work, and the high level is effective and used for enabling the weight factor calibration module to work.
In the third stage, the weight factor extraction module finishes two clk periods of the done signal delay mode selection signal, the done signal is high-level effective, the weight factor calibration module starts to work, and when the formal array is detected, linear operation is performed on the detection value of each pixel unit and the corresponding weight factor, so that the purpose of digital calibration is achieved. The external input clock signal clk and the reset signal rst _ n are consistent with the weight factor calibration module, the clock and the reset signal enable the weight factor extraction module to be matched with the whole array detection system in time sequence, the external input analog-to-digital conversion signal adc _ value sequentially sends real-time detection values of all pixel units to the weight factor calibration module, the weight factors of all the pixel units and the real-time detection values input by the weight factor extraction module are subjected to final linear calibration, and finally calibrated array detection values are transmitted to an upper computer through the combination of an output end integer result signal integer _ verify and a decimal result signal decimall _ verify.
As shown in the flowchart of the calibration method of the digital calibration circuit of fig. 2, the calibration method of the present invention includes the following steps:
step 1, time-to-digital conversion of array detection data. Photon flight time analog signals of all pixel units in the array detector are converted into digital signals through an ADC (analog to digital converter), namely photon flight time corresponding to TAC (capacitor voltage) of all pixel units in the TOF detection array is subjected to sequential analog-to-digital conversion according to the sequence of all pixel units in the array.
And 2, selecting a working mode of the parameter presetting module. And judging whether the working mode of the system is low level, wherein the parameter presetting module works at the low level, and setting the data integer and decimal digit of the subsequent weight factor extraction module through signals such as external input window counting and the like so as to determine the precision of the digital calibration circuit. The work period and the delay time of the digital calibration circuit module are determined by an externally input clock and a reset signal.
And 3, preparing linear regression data by a weight factor extraction module. The establishment of the primary linear regression model requires that the array carries out three times of detection of known input, and ADC analog-to-digital conversion is carried out on the detected actual voltage values of the three groups of TAC circuits of each pixel unit and the actual voltage values are stored in the circuits.
And 4, starting linear regression by the weight factor extraction module. And (3) performing linear regression once through the actual voltage values of the TAC circuits in the three groups of the pixel units in the step (3) according to the extraction precision and the extraction delay of the weight factors set in the step (2), and then storing the actual voltage value of each pixel unit in the full-scale working process of the TAC circuit after the linear regression once.
And 5, starting secondary linear regression by the weight factor extraction module. Under the condition of known input, the actual value of each pixel unit obtained by array detection is known. Under the control of the logic circuit, the ideal value of each pixel unit is input in order from the outside, the ideal value and the corresponding actual value are subjected to secondary linear regression while being input, the output obtained after the secondary linear regression is the weight factor corresponding to each pixel unit, and finally the weight factor is stored in the circuit in order. And after the weight factor extraction module finishes working, the pull-up module finishes the signal and enables the weight factor calibration module to work.
And 6, orderly reading the pixel unit values into the weight factor calibration module normally in the array detection. The high level of the enable signal after the weight factor extraction is completed is effective, and the weight factor calibration module normally reads in the photon flight time data of each pixel unit after analog-to-digital conversion in order after judging that the working mode is the high level, so as to prepare for formal calibration.
And 7, the weight factor calibration module works normally. And enabling the weight factor calibration module to work by an enabling signal sent by the weight factor extraction module, orderly reading the actual values of the pixel units after analog-to-digital conversion into the calibration module when the array detection normally works, orderly reading the weight factors of the pixel units stored in the circuit in the step 5, and performing linear model calculation on the weight factors and the actual values of the corresponding pixel units.
And 8, finishing the array detection digital calibration. And performing linear model calculation on the actual values of the pixel units and the corresponding weight factors to obtain the calibrated photon flight time, and finally sequentially reading the photon flight time to an upper computer through an output end to perform data processing.
As shown in fig. 6, the entire digital calibration involves 14 external input/output signals, which are respectively included in the parameter presetting module circuit, the weighting factor extracting module circuit and the weighting factor calibrating module circuit. The input signals of the parameter presetting module circuit comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimall, and the output end of the parameter presetting module circuit inputs the delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimall to the weight factor extraction module. The input signals of the weight factor extraction module circuit comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc _ value, an integer result signal result _ integer and a decimal result signal result _ decimal which are output to the weight factor calibration module circuit, and a module completion signal done. The input signals of the weighting factor calibration module circuit comprise an external clock signal clk, a reset signal rst _ n and an analog-to-digital conversion signal adc _ value, and an integer result signal integer _ verify and a decimal result signal decimamal _ verify of the output end of the weighting factor calibration module circuit are connected to the external output end.
The designed digital circuit verilog code is subjected to synthesis and simulation of detection of a plurality of pixel units through Vivado software of Saint Corp, analysis of each path of signals in FIG. 6 can find that the whole digital circuit time sequence is divided into three parts of parameter presetting, weight factor extraction and weight factor calibration, in the parameter presetting part, the delay of the digital calibration is determined to be 2 clk through a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimall which are input externally, and the calibrated value comprises a 16-bit integer and a 16-bit decimal, the calibration precision is determined by the decimal, so that the calibration precision is 0.00001526 LSB (minimum unit of ADC quantization). The voltage value of each pixel unit input externally obtains a weight factor integer result signal result _ integer and a decimal result signal result _ decimal through primary and secondary linear regression of 2 clk. The method comprises the steps that when an enabling signal done is pulled high, a weighting factor calibration module works, because the experiment is based on the fact that the ideal value input of each pixel unit is known, the weighting factor is obtained and then is directly subjected to linear fitting with the actual value of the pixel unit, an integer result signal result _ integer and a decimal result signal result _ default at the output end represent the ideal value of each pixel unit after calibration, the result at the output end is directly compared with the ideal value of each pixel unit input from the outside, the theoretical time sequence is consistent with the theoretical time sequence designed in the figure 5, meanwhile, through a large number of statistical calculations, the precision loss caused by the fact that the weighting factor is introduced into a calibration method is 0.00001 LSB different from the ideal value to the maximum, and the expectation of digital calibration is achieved. The feasibility of such a digital calibration circuit and method for a time-amplitude converted TOF array detector was verified.
The invention realizes the function of digital calibration of array detection in a digital domain. Compared with the method that feedback calibration, a switch and a large number of logic circuits are introduced in an analog domain to adjust the capacitance and the current in the TAC circuit, the method improves the filling factor of each pixel unit in array detection, enhances the stability of the array detection, and enables a front-end circuit to have the characteristics of low time delay and low power consumption. In addition, the included parameter presetting module can realize real-time adjustment of calibration precision and circuit area size, and meanwhile, the calibration period can be adjusted through external signals, so that the digital calibration module has the characteristics of controllability and flexibility. According to the invention, the weight factors required by calibration are extracted once and stored in the circuit before formal calibration, and only linear model calculation needs to be repeated with the array detection during normal work, so that the calibration circuit has a simple structure and low hardware consumption. And finally, the digital calibration result is combined by using an integer and a decimal, so that the calibration accuracy is improved, and the whole digital calibration module has strong anti-interference capability due to the characteristic of a digital signal large signal.
The above description is only an embodiment of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (6)

1.一种用于时间-幅度转换TOF探测器的数字校准电路，其特征在于：所述校准电路包括参数预设置模块、权重因子提取模块、权重因子校准模块，所述参数预设置模块输出端与所述权重因子提取模块输入端相连，所述权重因子提取模块输出端与所述权重因子校准输入端模块相连。1. a digital calibration circuit for time-amplitude conversion TOF detector, is characterized in that: described calibration circuit comprises parameter preset module, weight factor extraction module, weight factor calibration module, and described parameter preset module output terminal It is connected to the input end of the weight factor extraction module, and the output end of the weight factor extraction module is connected to the weight factor calibration input end module. 2.根据权利要求1所述用于时间-幅度转换TOF探测器的数字校准电路，其特征在于：所述权重因子校准模块的功能是找到所有像素单元实际值与理想值之间的偏差，所述权重因子提取模块的外部输入信号包括外部时钟信号clk、复位信号rst_n、工作模式选择信号mode_select、理想阈值信号threshold、模数转换信号adc_value以及输出到权重因子校准模块的整数结果信号result_integer、小数结果信号result_decimal以及模块完成信号done，外部时钟信号clk、复位信号rst_n、工作模式选择信号mode_select与所述所述参数预设置模块一致，外部时钟信号clk、复位信号rst_n使得所述权重因子校准模块在时序上与整个阵列探测系统模块匹配，在工作模式选择信号mode_select为高电平时，权重因子提取模块工作。2. The digital calibration circuit for time-amplitude conversion TOF detector according to claim 1, wherein the function of the weighting factor calibration module is to find the deviation between the actual value and the ideal value of all pixel units, so The external input signals of the weighting factor extraction module include the external clock signal clk, the reset signal rst_n, the working mode selection signal mode_select, the ideal threshold signal threshold, the analog-to-digital conversion signal adc_value, and the integer result signal result_integer, the fractional result output to the weighting factor calibration module The signal result_decimal and the module completion signal done, the external clock signal clk, the reset signal rst_n, and the working mode selection signal mode_select are consistent with the parameter preset module, and the external clock signal clk and reset signal rst_n make the weighting factor calibration module in the timing sequence The above is matched with the whole array detection system module. When the working mode selection signal mode_select is at a high level, the weight factor extraction module works. 3.根据权利要求2所述用于时间-幅度转换TOF探测器的数字校准电路，其特征在于：权重因子提取模块后会根据时序进行一次线性回归和二次线性回归，所述一次线性回归具体为：正式阵列探测前使能各像素单元工作三次，通过模数转换信号adc_value将各像素单元三次不同的TAC电路实际输出值送入权重因子提取模块，拟合出各像素单元TAC电路满量程工作的实际电压值，使之具备TAC电路理想的高线性度特性，最终将其存储起来，至此一次线性回归结束，所述二次线性回归具体为：在得到各像素单元满量程工作的实际电压值后，由于TAC电路的线性度高的特性，将外部输入的理想阈值信号threshold与各像素单元实际值做线性运算，在预置电路大小与精度的前提下得到各像素单元输出端整数结果信号result_integer和小数结果信号result_decimal两者组成的权重因子，并保存在存储电路中，至此，二次线性回归结束，权重因子提取模块工作完成的同时会在输出端产生一个模块完成信号done，高电平有效，用于使能权重因子校准模块工作。3. the digital calibration circuit for time-amplitude conversion TOF detector according to claim 2, is characterized in that: after the weight factor extraction module, can carry out a linear regression and a quadratic linear regression according to the time sequence, and the linear regression is specifically It is: enable each pixel unit to work three times before the formal array detection, send the actual output value of each pixel unit three different TAC circuits to the weight factor extraction module through the analog-to-digital conversion signal adc_value, and fit the full-scale operation of the TAC circuit of each pixel unit The actual voltage value of the TAC circuit makes it have the ideal high linearity characteristics of the TAC circuit, and finally it is stored. At this point, the first linear regression ends. The second linear regression is specifically: after obtaining the actual voltage value of each pixel unit full-scale operation Then, due to the high linearity of the TAC circuit, a linear operation is performed between the ideal threshold signal threshold input externally and the actual value of each pixel unit, and the integer result signal result_integer at the output end of each pixel unit is obtained under the premise of the preset circuit size and accuracy. The weight factor composed of the decimal result signal result_decimal and the fractional result signal result_decimal is stored in the storage circuit. At this point, the quadratic linear regression is over. When the weight factor extraction module is completed, a module completion signal done will be generated at the output, and the high level is active. , used to enable the weight factor calibration module to work. 4.根据权利要求3所述用于时间-幅度转换TOF探测器的数字校准电路，其特征在于：所述权重因子校准模块的功能是在成功提取权重因子后，在正式阵列探测时，对每一个像素单元的探测值与其对应的权重因子进行线性运算，使之达到数字校准的目的，所述权重因子校准模块的输入信号包括外部时钟信号clk、复位信号rst_n、模数转换信号adc_value，所述权重因子校准模块的输出端的整数结果信号integer_verify和小数结果信号decimal_verify连接到外部输出端，所述权重因子提取模块输入的模块完成信号done一旦变为高电平，所述权重因子校准模块开始工作，所述权重因子校准模块的外部时钟信号clk、复位信号rst_n与所述权重因子提取模块一致，外部时钟信号clk和复位信号rst_n使得权重因子校准模块在时序上与整个阵列探测系统匹配，正式探测时，所述权重因子校准模块的模数转换信号adc_value将各像素单元的实时探测值依次送入权重因子校准模块，权重因子提取模块输入的各像素单元权重因子与实际探测值进行最终数字校准，最终校准后的阵列探测值由输出端整数结果信号integer_verify和小数结果信号decimal_verify组成传送至上位机进行数据处理。4. The digital calibration circuit for time-amplitude conversion TOF detector according to claim 3, characterized in that: the function of the weighting factor calibration module is that after the weighting factor is successfully extracted, during formal array detection, for each The detection value of a pixel unit and its corresponding weight factor are subjected to linear operation to achieve the purpose of digital calibration. The input signal of the weight factor calibration module includes an external clock signal clk, a reset signal rst_n, and an analog-to-digital conversion signal adc_value. The integer result signal integer_verify and the decimal result signal decimal_verify of the output terminal of the weighting factor calibration module are connected to the external output terminal. Once the module completion signal done input by the weighting factor extraction module becomes a high level, the weighting factor calibration module starts to work, The external clock signal clk and reset signal rst_n of the weighting factor calibration module are consistent with the weighting factor extraction module. The external clock signal clk and the reset signal rst_n make the weighting factor calibration module match the entire array detection system in timing. , the analog-to-digital conversion signal adc_value of the weighting factor calibration module sends the real-time detection value of each pixel unit to the weighting factor calibration module in turn, and the weighting factor of each pixel unit input by the weighting factor extraction module and the actual detection value are finally digitally calibrated, and finally The calibrated array detection value is composed of the integer result signal integer_verify and the decimal result signal decimal_verify of the output terminal and is sent to the upper computer for data processing. 5.根据权利要求1所述用于时间-幅度转换TOF探测器的数字校准电路，其特征在于：所述参数预设置模块的功能是设置整个数字校准电路的精度及性能，所述参数预设置模块的外部输入信号包括外部时钟信号clk、复位信号rst_n、工作模式选择信号mode_select、延迟选择信号latency、设置窗口信号set_win、整数精度设置信号set_integer和小数精度设置信号set_decimal，所述参数预设置模块的输出端向所述权重因子提取模块输入延迟选择信号out_latency、整数精度确定信号out_integer及小数精度确定信号out_decimal，外部输入的工作模式选择信号mode_select是使能信号，该信号低电平时，所述参数预设置模块工作，外部输入的外部时钟信号clk和复位信号rst_n确定整个数字校准电路的校准周期，延迟选择信号latency、整数精度设置信号set_integer和小数精度设置信号set_decimal在set_win窗口信号中通过外部时钟信号clk进行计数，将计数得到的输出所述延迟选择信号out_latency、整数精度确定信号out_integer及小数精度确定信号out_decimal接至所述权重因子提取模块。5. the digital calibration circuit for time-amplitude conversion TOF detector according to claim 1, is characterized in that: the function of described parameter preset module is to set the precision and performance of the whole digital calibration circuit, and described parameter preset The external input signals of the module include the external clock signal clk, the reset signal rst_n, the working mode selection signal mode_select, the delay selection signal latency, the setting window signal set_win, the integer precision setting signal set_integer and the decimal precision setting signal set_decimal. The output terminal inputs the delay selection signal out_latency, the integer precision determination signal out_integer, and the decimal precision determination signal out_decimal to the weighting factor extraction module, and the externally input working mode selection signal mode_select is an enable signal. When the signal is low, the parameter is preset. The setting module works, the external clock signal clk and reset signal rst_n input from the outside determine the calibration cycle of the entire digital calibration circuit, the delay selection signal latency, the integer precision setting signal set_integer and the decimal precision setting signal set_decimal pass the external clock signal clk in the set_win window signal Counting is performed, and the output delay selection signal out_latency, integer precision determination signal out_integer and decimal precision determination signal out_decimal obtained by counting are connected to the weight factor extraction module. 6.根据权利要求1所述用于时间-幅度转换TOF探测器的数字校准电路的校准方法，其特征在于：所述电路按照如下步骤进行校准：6. the calibration method for the digital calibration circuit of time-amplitude conversion TOF detector according to claim 1, is characterized in that: described circuit is calibrated according to the following steps: 步骤1：在逻辑电路的控制下，将阵列探测中的各像素单元光子飞行时间模拟信号通过ADC转换成数字信号，即将TOF阵列探测中各像素单元TAC电路中，电容电压所对应的光子飞行时间按照阵列各像素单元顺序进行有序模数转换；Step 1: Under the control of the logic circuit, convert the photon time-of-flight analog signal of each pixel unit in the array detection into a digital signal through ADC, that is, in the TAC circuit of each pixel unit in the TOF array detection, the photon time-of-flight corresponding to the capacitor voltage Perform ordered analog-to-digital conversion according to the sequence of each pixel unit of the array; 步骤2：参数预设值模块工作：当工作模式选择信号为低电平时，参数预设值模块工作，通过外部输入的信号外部时钟信号clk和复位信号rst_n确定整个数字校准电路的周期、面积以及校准精度，从而控制数字校准电路的指标及性能；Step 2: The parameter preset value module works: when the working mode selection signal is at a low level, the parameter preset value module works, and the cycle, area and Calibration accuracy, thereby controlling the index and performance of the digital calibration circuit; 步骤3：权重因子提取模块进行一次线性回归：正式阵列探测前使能各像素单元工作三次，将各像素单元三次不同的TAC电路实际输出通过一次、二次线性回归，拟合出各像素单元TAC电路满量程工作的实际电压值，使之具备TAC电路理想的高线性度特性，最终将其存储起来；Step 3: The weight factor extraction module performs a linear regression: enable each pixel unit to work three times before the formal array detection, pass the actual output of the three different TAC circuits of each pixel unit through a linear regression, and fit the TAC of each pixel unit The actual voltage value of the full-scale operation of the circuit makes it have the ideal high linearity characteristics of the TAC circuit, and finally stores it; 步骤4：在数字逻辑电路的控制下，按阵列探测各像素单元的顺序将理想值与实际值进行线性计算，最终得到阵列探测中每个像素单元对应的权重因子，并将他们存储在电路中；Step 4: Under the control of the digital logic circuit, linearly calculate the ideal value and the actual value in the order of the array detection of each pixel unit, and finally obtain the corresponding weight factor of each pixel unit in the array detection, and store them in the circuit. ; 步骤5：阵列探测正常进行工作：步骤4权重因子提取成功后会给权重因子校准模块发送模块完成信号，高电平有效，此时权重因子校准模块工作，即阵列探测正常工作时像素单元的ADC量化数据按顺序送入权重因子校准模块，该模块正常按顺序每读入一个像素单元的实际值，就将其与对应的权重因子进行线性数字校准，最终将校准得到的阵列探测值发送到上位机进行数据处理。Step 5: The array detection works normally: After the weight factor extraction is successful in Step 4, a module completion signal will be sent to the weight factor calibration module, and the high level is active. At this time, the weight factor calibration module is working, that is, the ADC of the pixel unit when the array detection works normally The quantized data is sent to the weighting factor calibration module in sequence. The module normally reads the actual value of a pixel unit in sequence, and performs linear digital calibration with the corresponding weighting factor, and finally sends the calibrated array detection value to the upper position. machine for data processing.
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