CN114236514A - Digital calibration circuit and method for time-amplitude converting TOF detector - Google Patents
Digital calibration circuit and method for time-amplitude converting TOF detector Download PDFInfo
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Abstract
The invention relates to a digital calibration circuit and a digital calibration method for a time-amplitude conversion TOF detector, wherein the calibration circuit comprises a parameter presetting module, a weight factor extracting module and a weight factor calibration module, the output end of the parameter presetting module is connected with the input end of the weight factor extracting module, and the output end of the weight factor extracting module is connected with the weight factor calibration input end module. On the premise of ensuring that the filling factor of the pixel unit and the array integration level meet the array detection requirement, the invention simplifies the calibration time sequence to the maximum extent, reduces the circuit area, reduces the power consumption and the time delay of the circuit and obviously improves the calibration precision.
Description
Technical Field
The invention relates to the technical field of photon Time of Flight (TOF) detection, in particular to a Time-amplitude conversion-based TOF array detection digital calibration circuit and method.
Background
The TOF detection is divided into a direct detection mode and an indirect detection mode, wherein the direct TOF detection depends on the flight time of photons, the time measurement precision does not change obviously along with the increase of the test distance, and the performance is stable, so that the direct TOF detection technology has wide application prospects in the aspects of laser ranging, 3D imaging and the like.
The TOF array detection imaging chip based on the direct TOF detection technology mainly adopts a time-to-digital conversion (TDC) circuit to obtain high time resolution and a large measurement range, but generally needs a plurality of delay units, D flip-flops and logic gate circuits, and is not suitable for pixel units for high-density array detection. The time-amplitude conversion (TAC) circuit is simpler in structure and lower in power consumption, meets various requirements of the array detection reading circuit, and simultaneously needs to be matched with a subsequent analog-to-digital conversion (ADC) circuit for quantitative output.
The TAC circuit is essentially different in voltage value obtained by time integration on capacitors in the circuit corresponding to different photon flight times, and then the voltage value is uploaded to an upper computer after analog-to-digital conversion by the ADC circuit. The TOF array detection comprises a plurality of pixel units, and the TAC circuit in each pixel unit comprises capacitors with the same size. Layout parasitic capacitance, process angle and other factors put high requirements on the matching of a large number of capacitors, and capacitance mismatch of each pixel unit in TOF array detection can cause detection misalignment.
The traditional analog domain method for improving the matching of the TAC circuit in the array detection mainly introduces feedback calibration, a switch and a large number of logic circuits to adjust the capacitance and the current in the TAC circuit, but the addition of the circuits can also bring the problems of high power consumption, high time delay, reduction of the filling factor of a pixel unit and the like, and the addition of a large number of front-end circuits makes the advantages of the method compared with the TDC circuit unobvious.
Disclosure of Invention
In order to solve the problems of insufficient calibration precision, high power consumption, high time delay, reduced pixel unit filling factor and the like in the process of calibrating a detection value by a TOF array detection analog domain compensation circuit based on time-amplitude conversion, the invention provides a digital circuit calibration circuit for calibrating in a digital domain and a calibration method thereof.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the present invention is a digital calibration circuit and method for a time-amplitude converted TOF array detector, the digital calibration circuit comprising: the device comprises a parameter presetting module, a weight factor extracting module and a weight factor calibrating module. The output end of the parameter presetting module is connected with the input end of the weight factor extracting module, and the output end of the weight factor extracting module is connected with the weight factor calibrating input end module. The external input signals of the parameter presetting module comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimal, and the output end of the parameter presetting module inputs the delay selection signal out _ latency, the integer precision determining signal out _ integer and the decimal precision determining signal out _ decimal to the weight factor extraction module. The external input signals of the weight factor extraction module comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc _ value, an integer result signal result _ integer and a decimal result signal result _ decimal which are output to the weight factor calibration module, and a module completion signal done. The input signals of the weighting factor calibration module comprise an external clock signal clk, a reset signal rst _ n and an analog-to-digital conversion signal adc _ value, and an integer result signal integer _ verify and a decimal result signal decimamal _ verify of the output end of the weighting factor calibration module are connected to the external output end.
The function of the parameter presetting module is to set the precision and performance of the whole digital calibration circuit, and belongs to the preparation stage of digital calibration. The externally input operation mode selection signal mode _ select is an enable signal, and when the signal is at a low level, the parameter presetting module operates. The external input clock signal clk and the reset signal rst _ n determine the calibration period of the whole digital calibration circuit, so that the digital calibration circuit can better match with the whole array detection system. The external input signal set _ win is a periodic window signal with fixed width, the delay time selection signal latency, the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal which are externally input are counted in the window signal set _ win through a clock signal clk, the area and the power consumption of the digital calibration circuit are directly determined by the delay time selection signal latency in the digital calibration circuit, and the precision of the digital calibration circuit can be determined by the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal. Since the three signals are directly input from the outside and can control the frequencies of the three signals, different circuit areas, power consumption and precision required by different array detection applications can be controlled by different values counted in the window signal. And finally, connecting the output delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimal obtained by counting to a weight factor extraction module.
The function of the weight factor extraction module is to find the deviation between the actual value and the ideal value of all the pixel units, which belongs to the key stage of digital calibration. The delay selection signal out _ latency, the integer precision determination signal out _ integer and the fractional precision determination signal out _ decimal which are input into the weighting factor extraction module by the parameter presetting module determine the area and the precision of the whole digital calibration circuit. The external input clock signal clk, the reset signal rst _ n and the mode selection signal mode _ select are consistent with the parameter presetting module, the clock and the reset signal enable the weighting factor extraction module to be matched with the whole array detection system module in time sequence, and meanwhile, the weighting factor extraction module can work only when the mode selection signal mode _ select is at a high level. The weight factor extraction module can perform linear regression according to time sequence after working, and the linear regression comprises the following main steps: enabling each pixel unit to work three times before formal array detection, sending the TAC circuit actual output values of each pixel unit, which are different for three times, to a weight factor extraction module through an analog-to-digital conversion signal adc _ value, fitting the actual voltage value of each pixel unit TAC circuit working in a full scale to enable the TAC circuit to have the ideal high linearity characteristic of the TAC circuit, and finally storing the TAC circuit to finish linear regression once. The secondary linear regression comprises the following main steps: after the actual voltage value of each pixel unit in full-scale operation is obtained, due to the characteristic of high linearity of the TAC circuit, the ideal threshold signal threshold input from the outside and the actual value of each pixel unit are subjected to linear operation, and a weight factor composed of an integer result signal result _ integer and a decimal result signal result _ decimal at the output end of each pixel unit is obtained on the premise of presetting the size and precision of the circuit, and is stored in the storage circuit. And when the secondary linear regression is finished, the weight factor extraction module generates a module completion signal done at the output end while finishing the work, and the high level is effective and used for enabling the weight factor calibration module to work.
The function of the weight factor calibration module is to perform linear operation on the detection value of each pixel unit and the corresponding weight factor when formal array detection is performed after the weight factor is successfully extracted, so that the purpose of digital calibration is achieved. Once the signal done input by the weight factor extraction module is changed into high level, the weight factor calibration module starts to work. The external input clock signal clk and the reset signal rst _ n are consistent with the weight factor extraction module, the clock and the reset signal enable the weight factor calibration module to be matched with the whole array detection system in time sequence, the external input analog-to-digital conversion signal adc _ value sequentially sends real-time detection values of all pixel units to the weight factor calibration module, the weight factors of all the pixel units input by the weight factor extraction module and actual detection values are subjected to final digital calibration, and finally calibrated array detection values are composed of output end integer result signals integer _ verify and decimal result signals decimall _ verify and are transmitted to an upper computer for data processing.
The invention discloses a digital calibration method for a time-amplitude conversion TOF array detector, which comprises the following steps:
in the first step, under the control of a logic circuit, photon flight time analog signals of each pixel unit in the array detector are converted into digital signals. Under the control of the logic circuit, photon flight time analog signals of each pixel unit in array detection are converted into digital signals through an ADC (analog to digital converter), namely photon flight time corresponding to capacitor voltage in a TAC (TAC) circuit of each pixel unit in TOF (time of flight) array detection is subjected to sequential analog-to-digital conversion according to the sequence of each pixel unit in the array.
And secondly, the parameter presetting module works. And when the working mode selection signal is at a low level, the parameter presetting module works. The period, the area and the calibration precision of the whole digital calibration circuit are determined through an externally input signal, so that the index and the performance of the digital calibration circuit are controlled.
And thirdly, performing linear regression by the weight factor extraction module. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times in advance, fitting the actual voltage value of the TAC circuit of each pixel unit in full-scale work through the actual output of the TAC circuit of each pixel unit three times, enabling the TAC circuit to have ideal high-linearity characteristics, and finally storing the TAC circuit after analog-to-digital conversion through a storage circuit.
And fourthly, performing secondary linear regression by the weight factor extraction module. The secondary linear regression comprises the following main steps: the whole digital calibration circuit aims to find the difference between an actual value and an ideal value during each array detection, and because the third step obtains the actual voltage value of each pixel unit in full-scale operation and the ideal value of each pixel unit is known, the ideal value and the actual value are linearly calculated according to the sequence of detecting each pixel unit by the array under the control of the digital logic circuit, and finally the weight factor corresponding to each pixel unit in the array detection is obtained and stored in the circuit.
And fifthly, the array detection normally works. And fourthly, after the weight factors are successfully extracted, a signal is sent to a weight factor calibration module sending module to complete the signal, the high level is effective, at the moment, the weight factor calibration module works, namely ADC quantization data of the pixel units are sent to the weight factor calibration module in sequence when the array detection normally works, the module carries out linear digital calibration on the actual value and the corresponding weight factors when reading in the actual value of one pixel unit in sequence, and finally the array detection value obtained through calibration is sent to an upper computer for data processing.
The invention has the beneficial effects that:
compared with the method that feedback calibration, a switch and a large number of logic circuits are introduced in an analog domain to adjust the capacitance and the current in the TAC circuit, the method improves the filling factor of each pixel unit in array detection, enhances the stability of the array detection, and has the characteristics of low time delay and low power consumption.
Compared with the traditional analog circuit which introduces a complex feedback calibration circuit, the parameter presetting module included in the invention can realize real-time adjustment of calibration precision and circuit area size, and can adjust the calibration period through external signals, so that the digital calibration module has the characteristics of controllability and flexibility.
According to the invention, the weight factors required by calibration are extracted once and stored in the circuit before formal calibration, and only linear model calculation needs to be repeated with the array detection during normal work, so that the calibration circuit has a simple structure and low hardware consumption.
The digital calibration result of the invention improves the calibration accuracy by combining the integer and the decimal, and the whole digital calibration module has high stability and strong anti-interference capability due to the characteristic of a large signal of a digital signal.
Drawings
Fig. 1 is a schematic diagram of a pixel unit according to the present invention.
FIG. 2 is a flow chart of the method steps of the present invention.
FIG. 3 is a schematic diagram of the first and second linear regression obtained by the weight factor extraction module according to the present invention.
Fig. 4 is a hardware circuit framework diagram of the present invention.
Fig. 5 is a timing diagram of the operation of the present invention.
FIG. 6 is a timing verification diagram of the present invention.
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary.
As shown in fig. 1, the schematic diagram of the pixel unit of the digital calibration circuit and method of the present invention, the whole pixel unit mainly includes a TOF photon detecting device and a TAC circuit. When a photon is detected by the photon detection device, the corresponding TAC circuit generates a TOF voltage value. The TOF voltage values corresponding to different photon arrival times are different, under an ideal condition, the photon arrival times and the TOF voltage are in a linear relation, under an actual condition, due to the fact that an analog circuit has the influence of parasitic capacitance and the like, the TOF actual voltage value has the problem that the TOF actual voltage value is smaller than the ideal voltage value and is nonlinear, and the problem directly causes that an array detector cannot accurately detect the TOF voltage value and the TOF actual voltage value are infinitely approximate to an ideal curve, so that false detection of the array detector is avoided.
The core of the whole digital calibration circuit is a weight factor extraction module, and the weight factor extraction module consists of primary and secondary linear regression. As shown in fig. 3, the abscissa represents the photon flight time, and the ordinate represents the voltage digital quantity corresponding to the pixel unit passing through the analog-to-digital conversion circuit at each time point, and theoretically, the photon flight time is in direct proportion to the voltage, i.e., corresponds to an ideal value after quadratic regression. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times in advance, namely t1, t2 and t3, fitting the actual voltage value of the TAC circuit of each pixel unit in full-scale work through the TAC circuit actual voltage output values of the pixel units which are different three times, storing the actual voltage value in the circuit, and finishing the linear regression. At this time, the difference between the actual value and the ideal value of the TAC circuit in the full-scale working process is only one linear weight factor, and the secondary linear regression step is as follows: and performing linear operation on an ideal value input by an external circuit and an actual value of the pixel unit under the conditions of calibration precision and the like defined by the parameter presetting module, wherein the final result after the operation is the weight factor of a single pixel unit to be extracted, and if the NxN array is to be extracted, the process is sequentially performed for NxN times.
As shown in fig. 4, the overall hardware circuitry includes logic control circuitry, array detection circuitry, digital calibration circuitry, and analog-to-digital conversion (ADC) interface circuitry. The array detection circuit comprises N multiplied by N pixel units, wherein the digital calibration circuit consists of three parts, namely a parameter presetting module, a weight factor extracting module and a weight factor calibrating module.
As shown in fig. 5, the calibration circuit of the present invention mainly includes three modules, a parameter presetting module, a weight factor extracting module, and a weight factor calibrating module. According to the three modules, the whole digital calibration circuit time sequence is divided into three stages of parameter presetting, weight factor extraction and weight factor calibration.
In the first stage, the externally input operation mode selection signal mode _ select is an enable signal, and when the signal is at a low level, the parameter presetting module operates. The external input clock signal clk and the reset signal rst _ n determine the calibration period of the whole digital calibration circuit, so that the digital calibration circuit can better match with the whole array detection system. The external input signal set _ win is a periodic window signal with fixed width, the delay time selection signal latency, the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal which are externally input are counted in the set _ win window signal through the clock signal clk, the area and the power consumption of the circuit are directly determined by the delay time selection signal latency in the digital calibration circuit, and the precision of the digital calibration circuit can be determined by the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimal. Since the three signals are directly input from the outside and can control the frequencies of the three signals, different circuit areas, power consumption and precision required by different array detection applications can be controlled by different values counted in the window signal. And finally, the output delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimal obtained through counting are sent to a weight factor extraction module.
And in the second stage, after the preset value of the parameter is finished, the weight factor extraction module starts to work. The delay selection signal out _ latency, the integer precision determination signal out _ integer and the fractional precision determination signal out _ decimal which are input into the weighting factor extraction module by the parameter presetting module determine the area and the precision of the whole digital calibration circuit. The external input clock signal clk, the reset signal rst _ n and the mode selection signal mode _ select are consistent with the parameter presetting module, the clock and the reset signal enable the weighting factor extraction module to be matched with the whole array detection system module in time sequence, and meanwhile, the weighting factor extraction module can work only when the mode selection signal mode _ select is at a high level. After the module works, linear regression is carried out according to the time sequence. The primary linear regression mainly comprises the following steps: enabling each pixel unit to work three times before formal array detection, sending the TAC circuit actual output values of each pixel unit, which are different for three times, to a weight factor extraction module through an analog-to-digital conversion signal adc _ value, fitting the actual voltage value of each pixel unit TAC circuit working in a full scale to enable the TAC circuit to have the ideal high linearity characteristic of the TAC circuit, and finally storing the TAC circuit to finish linear regression once. The secondary linear regression comprises the following main steps: after the actual voltage value of each pixel unit in full-scale operation is obtained, due to the characteristic of high linearity of the TAC circuit, the ideal threshold signal threshold input from the outside and the actual value of each pixel unit are subjected to linear operation, and a weight factor composed of an integer result signal result _ integer and a decimal result signal result _ decimal at the output end of each pixel unit is obtained on the premise of presetting the size and precision of the circuit, and is stored in the storage circuit. And when the secondary linear regression is finished, the weight factor extraction module generates a module completion signal done at the output end while finishing the work, and the high level is effective and used for enabling the weight factor calibration module to work.
In the third stage, the weight factor extraction module finishes two clk periods of the done signal delay mode selection signal, the done signal is high-level effective, the weight factor calibration module starts to work, and when the formal array is detected, linear operation is performed on the detection value of each pixel unit and the corresponding weight factor, so that the purpose of digital calibration is achieved. The external input clock signal clk and the reset signal rst _ n are consistent with the weight factor calibration module, the clock and the reset signal enable the weight factor extraction module to be matched with the whole array detection system in time sequence, the external input analog-to-digital conversion signal adc _ value sequentially sends real-time detection values of all pixel units to the weight factor calibration module, the weight factors of all the pixel units and the real-time detection values input by the weight factor extraction module are subjected to final linear calibration, and finally calibrated array detection values are transmitted to an upper computer through the combination of an output end integer result signal integer _ verify and a decimal result signal decimall _ verify.
As shown in the flowchart of the calibration method of the digital calibration circuit of fig. 2, the calibration method of the present invention includes the following steps:
And 2, selecting a working mode of the parameter presetting module. And judging whether the working mode of the system is low level, wherein the parameter presetting module works at the low level, and setting the data integer and decimal digit of the subsequent weight factor extraction module through signals such as external input window counting and the like so as to determine the precision of the digital calibration circuit. The work period and the delay time of the digital calibration circuit module are determined by an externally input clock and a reset signal.
And 3, preparing linear regression data by a weight factor extraction module. The establishment of the primary linear regression model requires that the array carries out three times of detection of known input, and ADC analog-to-digital conversion is carried out on the detected actual voltage values of the three groups of TAC circuits of each pixel unit and the actual voltage values are stored in the circuits.
And 4, starting linear regression by the weight factor extraction module. And (3) performing linear regression once through the actual voltage values of the TAC circuits in the three groups of the pixel units in the step (3) according to the extraction precision and the extraction delay of the weight factors set in the step (2), and then storing the actual voltage value of each pixel unit in the full-scale working process of the TAC circuit after the linear regression once.
And 5, starting secondary linear regression by the weight factor extraction module. Under the condition of known input, the actual value of each pixel unit obtained by array detection is known. Under the control of the logic circuit, the ideal value of each pixel unit is input in order from the outside, the ideal value and the corresponding actual value are subjected to secondary linear regression while being input, the output obtained after the secondary linear regression is the weight factor corresponding to each pixel unit, and finally the weight factor is stored in the circuit in order. And after the weight factor extraction module finishes working, the pull-up module finishes the signal and enables the weight factor calibration module to work.
And 6, orderly reading the pixel unit values into the weight factor calibration module normally in the array detection. The high level of the enable signal after the weight factor extraction is completed is effective, and the weight factor calibration module normally reads in the photon flight time data of each pixel unit after analog-to-digital conversion in order after judging that the working mode is the high level, so as to prepare for formal calibration.
And 7, the weight factor calibration module works normally. And enabling the weight factor calibration module to work by an enabling signal sent by the weight factor extraction module, orderly reading the actual values of the pixel units after analog-to-digital conversion into the calibration module when the array detection normally works, orderly reading the weight factors of the pixel units stored in the circuit in the step 5, and performing linear model calculation on the weight factors and the actual values of the corresponding pixel units.
And 8, finishing the array detection digital calibration. And performing linear model calculation on the actual values of the pixel units and the corresponding weight factors to obtain the calibrated photon flight time, and finally sequentially reading the photon flight time to an upper computer through an output end to perform data processing.
As shown in fig. 6, the entire digital calibration involves 14 external input/output signals, which are respectively included in the parameter presetting module circuit, the weighting factor extracting module circuit and the weighting factor calibrating module circuit. The input signals of the parameter presetting module circuit comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimall, and the output end of the parameter presetting module circuit inputs the delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimall to the weight factor extraction module. The input signals of the weight factor extraction module circuit comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc _ value, an integer result signal result _ integer and a decimal result signal result _ decimal which are output to the weight factor calibration module circuit, and a module completion signal done. The input signals of the weighting factor calibration module circuit comprise an external clock signal clk, a reset signal rst _ n and an analog-to-digital conversion signal adc _ value, and an integer result signal integer _ verify and a decimal result signal decimamal _ verify of the output end of the weighting factor calibration module circuit are connected to the external output end.
The designed digital circuit verilog code is subjected to synthesis and simulation of detection of a plurality of pixel units through Vivado software of Saint Corp, analysis of each path of signals in FIG. 6 can find that the whole digital circuit time sequence is divided into three parts of parameter presetting, weight factor extraction and weight factor calibration, in the parameter presetting part, the delay of the digital calibration is determined to be 2 clk through a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimall which are input externally, and the calibrated value comprises a 16-bit integer and a 16-bit decimal, the calibration precision is determined by the decimal, so that the calibration precision is 0.00001526 LSB (minimum unit of ADC quantization). The voltage value of each pixel unit input externally obtains a weight factor integer result signal result _ integer and a decimal result signal result _ decimal through primary and secondary linear regression of 2 clk. The method comprises the steps that when an enabling signal done is pulled high, a weighting factor calibration module works, because the experiment is based on the fact that the ideal value input of each pixel unit is known, the weighting factor is obtained and then is directly subjected to linear fitting with the actual value of the pixel unit, an integer result signal result _ integer and a decimal result signal result _ default at the output end represent the ideal value of each pixel unit after calibration, the result at the output end is directly compared with the ideal value of each pixel unit input from the outside, the theoretical time sequence is consistent with the theoretical time sequence designed in the figure 5, meanwhile, through a large number of statistical calculations, the precision loss caused by the fact that the weighting factor is introduced into a calibration method is 0.00001 LSB different from the ideal value to the maximum, and the expectation of digital calibration is achieved. The feasibility of such a digital calibration circuit and method for a time-amplitude converted TOF array detector was verified.
The invention realizes the function of digital calibration of array detection in a digital domain. Compared with the method that feedback calibration, a switch and a large number of logic circuits are introduced in an analog domain to adjust the capacitance and the current in the TAC circuit, the method improves the filling factor of each pixel unit in array detection, enhances the stability of the array detection, and enables a front-end circuit to have the characteristics of low time delay and low power consumption. In addition, the included parameter presetting module can realize real-time adjustment of calibration precision and circuit area size, and meanwhile, the calibration period can be adjusted through external signals, so that the digital calibration module has the characteristics of controllability and flexibility. According to the invention, the weight factors required by calibration are extracted once and stored in the circuit before formal calibration, and only linear model calculation needs to be repeated with the array detection during normal work, so that the calibration circuit has a simple structure and low hardware consumption. And finally, the digital calibration result is combined by using an integer and a decimal, so that the calibration accuracy is improved, and the whole digital calibration module has strong anti-interference capability due to the characteristic of a digital signal large signal.
The above description is only an embodiment of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (6)
1. A digital calibration circuit for a time-to-amplitude converting TOF detector, characterized by: the calibration circuit comprises a parameter presetting module, a weight factor extracting module and a weight factor calibration module, wherein the output end of the parameter presetting module is connected with the input end of the weight factor extracting module, and the output end of the weight factor extracting module is connected with the weight factor calibration input end module.
2. The digital calibration circuit for a time-amplitude converting TOF detector according to claim 1, wherein: the function of the weight factor calibration module is to find the deviation between the actual value and the ideal value of all pixel cells, the external input signals of the weight factor extraction module comprise an external clock signal clk, a reset signal rst _ n, an operating mode selection signal mode _ select, an ideal threshold signal threshold, an analog-to-digital conversion signal adc _ value, an integer result signal result _ integer and a decimal result signal result _ decimal which are output to the weight factor calibration module, and a module completion signal done, wherein the external clock signal clk, the reset signal rst _ n and the operating mode selection signal mode _ select are consistent with the parameter presetting module, and the external clock signal clk and the reset signal rst _ n enable the weight factor calibration module to be matched with the whole array detection system module in time sequence, when the operation mode selection signal mode _ select is high, the weight factor extraction block operates.
3. The digital calibration circuit for a time-amplitude converting TOF detector according to claim 2, wherein: and after the weight factor extraction module, performing primary linear regression and secondary linear regression according to a time sequence, wherein the primary linear regression specifically comprises the following steps: enabling each pixel unit to work three times before formal array detection, sending the TAC circuit actual output values of each pixel unit, which are different for three times, to a weight factor extraction module through an analog-to-digital conversion signal adc _ value, fitting the actual voltage values of each pixel unit TAC circuit working in a full scale to enable the TAC circuit to have ideal high linearity characteristics of the TAC circuit, and finally storing the TAC circuit actual voltage values until primary linear regression is finished, wherein the secondary linear regression specifically comprises the following steps: after the actual voltage value of each pixel unit in full-scale operation is obtained, due to the characteristic of high linearity of the TAC circuit, an externally input ideal threshold signal threshold and the actual value of each pixel unit are subjected to linear operation, a weight factor composed of an integer result signal result _ integer and a decimal result signal result _ decimal at the output end of each pixel unit is obtained on the premise of presetting the size and the precision of the circuit, and the weight factor is stored in a storage circuit, so far, when the secondary linear regression is finished, a module completion signal done is generated at the output end while the weight factor extraction module is finished, and the high level is effective and used for enabling the weight factor calibration module to work.
4. The digital calibration circuit for a time-amplitude converting TOF detector according to claim 3, wherein: the function of the weight factor calibration module is to perform linear operation on the detection value of each pixel unit and the corresponding weight factor when formal array detection is performed after the weight factor is successfully extracted, so as to achieve the purpose of digital calibration, the input signals of the weight factor calibration module include an external clock signal clk, a reset signal rst _ n and an analog-to-digital conversion signal adc _ value, an integer result signal integer _ verify and a decimal result signal decimall _ verify at the output end of the weight factor calibration module are connected to the external output end, once a module completion signal done input by the weight factor extraction module is changed into a high level, the weight factor calibration module starts to work, an external clock signal clk and a reset signal rst _ n of the weight factor calibration module are consistent with the weight factor extraction module, and the external clock signal clk and the reset signal rst _ n enable the weight factor calibration module to be matched with the whole array detection system in time sequence, during formal detection, the analog-to-digital conversion signal adc _ value of the weighting factor calibration module sequentially sends real-time detection values of all pixel units to the weighting factor calibration module, the weighting factors of all pixel units input by the weighting factor extraction module and actual detection values are subjected to final digital calibration, and array detection values after final calibration are composed of an output end integer result signal integer _ verify and a decimal result signal decimall _ verify and are transmitted to an upper computer for data processing.
5. The digital calibration circuit for a time-amplitude converting TOF detector according to claim 1, wherein: the function of the parameter presetting module is to set the precision and performance of the whole digital calibration circuit, the external input signals of the parameter presetting module comprise an external clock signal clk, a reset signal rst _ n, a working mode selection signal mode _ select, a delay selection signal latency, a setting window signal set _ win, an integer precision setting signal set _ integer and a decimal precision setting signal set _ decimal, the output end of the parameter presetting module inputs the delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimal to the weight factor extraction module, the externally input working mode selection signal mode _ select is an enable signal, when the signal is at low level, the parameter presetting module works, the externally input external clock signal clk and the reset signal rst _ n determine the calibration period of the whole digital calibration circuit, the delay selection signal latency, the integer selection signal, the setting window signal, the integer precision determination signal and the decimal precision determination signal set _ decimal, Counting the integer precision setting signal set _ integer and the decimal precision setting signal set _ decimall in a set _ win window signal through an external clock signal clk, and connecting the counted output delay selection signal out _ latency, the integer precision determination signal out _ integer and the decimal precision determination signal out _ decimall to the weight factor extraction module.
6. The method of calibrating a digital calibration circuit for a time-amplitude converting TOF detector according to claim 1, characterized in that: the circuit is calibrated as follows:
step 1: under the control of a logic circuit, converting photon flight time analog signals of each pixel unit in array detection into digital signals through an ADC (analog to digital converter), namely, in a TAC (TAC) circuit of each pixel unit in TOF (time of flight) array detection, carrying out sequential analog-to-digital conversion on photon flight time corresponding to capacitor voltage according to the sequence of each pixel unit in the array;
step 2: the parameter presetting module works: when the working mode selection signal is at a low level, the parameter presetting module works, and the period, the area and the calibration precision of the whole digital calibration circuit are determined through an external clock signal clk and a reset signal rst _ n which are externally input signals, so that the index and the performance of the digital calibration circuit are controlled;
and step 3: the weight factor extraction module performs a linear regression: enabling each pixel unit to work for three times before formal array detection, fitting actual voltage values of TAC circuits of each pixel unit working in full range by performing primary and secondary linear regression on TAC circuit actual outputs of each pixel unit with different three times, enabling the TAC circuits to have ideal high linearity characteristics of the TAC circuits, and finally storing the TAC circuits;
and 4, step 4: under the control of a digital logic circuit, carrying out linear calculation on the ideal value and the actual value according to the sequence of array detection of each pixel unit, finally obtaining a weight factor corresponding to each pixel unit in the array detection, and storing the weight factors in the circuit;
and 5: the array detection works normally: and 4, after the weight factors are successfully extracted, a signal is sent to the weight factor calibration module to complete the module sending, the high level is effective, at the moment, the weight factor calibration module works, namely ADC (analog to digital converter) quantization data of the pixel units are sequentially sent to the weight factor calibration module when the array detection normally works, the module carries out linear digital calibration on the actual value and the corresponding weight factor when the module normally reads in the actual value of one pixel unit in sequence, and finally the array detection value obtained through calibration is sent to an upper computer for data processing.
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