CN114221540A - Boost circuit and amplifier - Google Patents
Boost circuit and amplifier Download PDFInfo
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- CN114221540A CN114221540A CN202111546653.6A CN202111546653A CN114221540A CN 114221540 A CN114221540 A CN 114221540A CN 202111546653 A CN202111546653 A CN 202111546653A CN 114221540 A CN114221540 A CN 114221540A
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- pmos transistor
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- 238000000034 method Methods 0.000 abstract description 5
- 230000000052 comparative effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
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- 230000007717 exclusion Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- Engineering & Computer Science (AREA)
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Abstract
The invention discloses a booster circuit and an amplifier, wherein the booster circuit comprises: switch tube, voltage circuit and control circuit. The switch tube is connected with the power supply voltage and the output end; the voltage circuit receives the zero temperature coefficient current and provides a comparison voltage; the control circuit is connected between the power supply voltage and the voltage circuit and is simultaneously connected with the switch tube, when the power supply voltage is greater than the comparison voltage, the output end outputs the comparison voltage, and when the power supply voltage is less than the comparison voltage, the control circuit controls the switch tube to be turned off through the control end, and the output end outputs the power supply voltage. According to the booster circuit provided by the embodiment of the invention, the comparison voltage VB is compared with the power supply voltage VDD, and the output end outputs the higher voltage of the comparison voltage and the power supply voltage under the condition that the comparison voltage is not more than the power supply voltage, wherein the comparison voltage is mainly influenced by the zero temperature coefficient voltage, so that the influence of the process can be avoided, the accurate boosting is realized, and the precision is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a boost circuit and an amplifier.
Background
The booster circuit is one of the circuit structures commonly used in amplifiers. The existing boosting circuit is complex in structure and high in cost, and meanwhile, the boosting size is easily influenced by the process, so that uncertainty is brought to the boosting precision of the whole circuit.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a booster circuit and an amplifier, wherein the boosting precision of the booster circuit is not influenced by the process.
To achieve the above object, an embodiment of the present invention provides a booster circuit, including: switch tube, voltage circuit and control circuit.
The switching tube is connected with a power supply voltage VDD and an output end VOUT; the voltage circuit receives the zero temperature coefficient current and provides a comparison voltage VB at the same time; control circuit connect in between power supply voltage VDD and the voltage circuit and be connected with the switch tube simultaneously, when power supply voltage VDD is greater than comparative voltage VB, output VOUT exports comparative voltage VB, when power supply voltage VDD is less than comparative voltage VB, control circuit passes through control end VGP control switch tube and cuts off, output VOUT output power supply voltage VDD.
In one or more embodiments of the present invention, the switch transistor is a PMOS transistor MP, a source of the PMOS transistor MP is connected to a power voltage VDD, a gate of the PMOS transistor MP is connected to a control terminal VGP, and a drain of the PMOS transistor MP is connected to an output terminal VOUT.
In one or more embodiments of the present invention, the voltage circuit includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1, a source of the PMOS transistor M3 is connected to one end of the resistor R1 and receives a zero temperature coefficient current at the same time, another end of the resistor R1 is connected to a source of the PMOS transistor M4, a gate of the PMOS transistor M3 is connected to the output terminal VOUT, and a gate of the PMOS transistor M4 is connected to the input terminal VIN.
In one or more embodiments of the present invention, the comparison voltage VB ═ VIN+ IM 4R 1, wherein VINFor the voltage input at input VIN, IM4 is a zero temperature coefficient current flowing through resistor R1.
In one or more embodiments of the present invention, the control circuit includes a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6, the first current mirror is connected to the power voltage VDD and the voltage circuit, the drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M5, the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the control terminal VGP.
In one or more embodiments of the present invention, the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and to the power voltage VDD, the gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
In one or more embodiments of the present invention, the boost circuit further includes a zero temperature coefficient current circuit generating a zero temperature coefficient current, the zero temperature coefficient current circuit being connected between the power supply voltage VDD and the control circuit.
In one or more embodiments of the present invention, the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS tube M0, a current mirror, and a resistor R0, wherein a positive input terminal of the amplifier OPA0 is connected to a reference voltage VREF, a negative input terminal of the amplifier OPA0 is grounded through the resistor R0, a negative input terminal of the amplifier OPA0 is connected to a source of the NMOS tube M0, a gate of the NMOS tube M0 is connected to an output terminal of the amplifier OPA0, a drain of the NMOS tube M0 is connected to the current mirror, and the current mirror is connected to a power supply voltage VDD and a control circuit.
In one or more embodiments of the invention, the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, a drain and a gate of the PMOS transistor MS0 are connected to and connected to a drain of the NMOS transistor M0 and a gate of the PMOS transistor MS1, a source of the PMOS transistor MS0 is connected to a source of the PMOS transistor MS1 and a power supply voltage VDD, and a drain of the PMOS transistor MS1 is connected to the control circuit.
The invention also provides an amplifier comprising the booster circuit.
Compared with the prior art, according to the booster circuit and the amplifier provided by the embodiment of the invention, the comparison voltage VB and the power supply voltage VDD are compared, under the condition that the comparison voltage VB and the power supply voltage VDD are not exceeded, the output end VOUT outputs higher voltage in the comparison voltage VB and the power supply voltage VDD, and the comparison voltage VB is mainly influenced by zero temperature coefficient voltage, so that the influence of the process can be avoided, the accurate boosting is realized, and the precision is improved.
Drawings
FIG. 1 is a circuit schematic of a boost circuit according to an embodiment of the present invention;
FIG. 2 is a circuit schematic of a zero temperature coefficient current circuit according to an embodiment of the present invention;
fig. 3 is a system block diagram of an amplifier OPA according to an embodiment of the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Example 1
As shown in fig. 1, the booster circuit includes: a switch tube, a zero temperature coefficient current circuit 10, a voltage circuit 20 and a control circuit 30.
The switch tube is connected with the power supply voltage VDD and the output end VOUT. The zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence, the zero temperature coefficient current circuit 10 is simultaneously connected with the power voltage VDD, and the voltage circuit 20 is simultaneously connected with the input terminal VIN, the output terminal VOUT and the internal circuit 40 of the amplifier OPA. The voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB. The control circuit 30 is used for controlling the on and off of the switching tube. When power supply voltage VDD is greater than comparison voltage VB, output terminal VOUT outputs comparison voltage VB, and when power supply voltage VDD is less than comparison voltage VB, control circuit 30 passes through control end VGP control switch tube and shuts off, and output terminal VOUT output power supply voltage VDD to the voltage that realizes output terminal VOUT output is not more than power supply voltage VDD.
As shown in fig. 1, the switch transistor is a PMOS transistor MP, a source of the PMOS transistor MP is connected to the power voltage VDD, a gate of the PMOS transistor MP is connected to the control terminal VGP and connected to the internal circuit 40 of the amplifier OPA through the control terminal VGP, and a drain of the PMOS transistor MP is connected to the output terminal VOUT. The booster circuit is a part of the amplifier OPA, and the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors, and the internal circuit 40 is used for maintaining the operation of the booster circuit and other circuits.
As shown in fig. 2 and fig. 1, the zero temperature coefficient current circuit 10 includes an amplifier OPA0, an NMOS transistor M0, a current mirror, and a resistor R0. The positive pole input end of the amplifier OPA0 is connected with the reference voltage VREF, the negative pole input end of the amplifier OPA0 is grounded through a resistor R0, and the negative pole input end of the amplifier OPA0 is connected with the source electrode of the NMOS tube M0. The gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0, the drain of the NMOS transistor M0 is connected to a current mirror, and the current mirror is connected to the power supply voltage VDD and the control circuit 30.
The current mirror comprises a PMOS tube MS0 and a PMOS tube MS1, the drain electrode and the gate electrode of the PMOS tube MS0 are connected with the drain electrode of the NMOS tube M0 and the gate electrode of the PMOS tube MS1, the source electrode of the PMOS tube MS0 is connected with the source electrode of the PMOS tube MS1 and the power supply voltage VDD, and the drain electrode of the PMOS tube MS1 is connected with the control circuit 30 through the VS2 end. The zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance of resistor R0. Zero temperature coefficient current flows through the VS2 terminal to the voltage circuit 20.
As shown in fig. 1, the voltage circuit 20 includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1. The source of the PMOS transistor M3 is connected to one end of the resistor R1 and receives the zero temperature coefficient current at the same time, and specifically, the source of the PMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD 2. The other end of the resistor R1 is connected with the source electrode of the PMOS tube M4, the grid electrode of the PMOS tube M3 is connected with the output end VOUT, and the grid electrode of the PMOS tube M4 is connected with the input end VIN. PMOS tubes are adopted by the PMOS tube M3 and the PMOS tube M4, rail-to-rail input is achieved, and circuit cost is reduced.
Comparison voltage VB ═ VIN+ IM 4R 1, wherein VINFor the voltage input at input VIN, IM4 is a zero temperature coefficient current flowing through resistor R1. The zero temperature coefficient current is determined by a reference voltage VREF and a resistor R0. Namely, the voltage on the resistor R1 is mainly influenced by the reference voltage VREF, so that accurate boosting can be realized, the process influence is avoided, and the precision is improved.
As shown in fig. 1, the control circuit 30 includes a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6. The first current mirror is connected to a supply voltage VDD and voltage circuit 20, and in this embodiment, a zero temperature coefficient current circuit 10 is connected between the first current mirror and the supply voltage VDD. The drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M5, the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the gate of the PMOS transistor MP through the control terminal VGP.
The first current mirror includes a PMOS transistor M1 and a PMOS transistor M2. The source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and to the power supply voltage VDD, and in this embodiment, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and to the VS2 connected to the drain of the PMOS transistor MS 1. The grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2 and forms a VG2 terminal. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5 and forms a VG5 terminal. The drain of the NMOS transistor M2 is connected with the resistor R1 and the source of the PMOS transistor M3 through the VD2 terminal.
According to the above boosting circuit, when the power supply voltage VDD is greater than the comparison voltage VB, the current of the current source I1 is set to be smaller than the current passing through the PMOS transistor M1, and the voltage at the VG5 terminal is low, the NMOS transistor M6 is turned off, and the output terminal OUT outputs the comparison voltage VB.
When the power supply voltage VDD is smaller than the comparison voltage VB, the PMOS transistor M2 enters a linear region, the difference between the voltage at the VS2 end and the voltage at the VG2 end becomes large, the current passing through the PMOS transistor M1 is larger than the current of the current source I1, the NMOS transistor M6 is turned on, so that the VGP end is at a low voltage, the PMOS transistor MP is turned on, and the output end OUT outputs the power supply voltage VDD.
As shown in fig. 3, in another embodiment, an amplifier OPA is further provided, which includes the above-mentioned boost circuit. The booster circuit is part of the amplifier OPA. The output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA. The positive input terminal of the amplifier OPA is connected to the input terminal VIN.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A boost circuit, comprising:
the switching tube is connected with a power supply voltage VDD and an output end VOUT;
the voltage circuit receives the zero temperature coefficient current and provides a comparison voltage VB; and
the control circuit is connected between the power supply voltage VDD and the voltage circuit and is simultaneously connected with the switch tube, when the power supply voltage VDD is greater than the comparison voltage VB, the output end VOUT outputs the comparison voltage VB, when the power supply voltage VDD is less than the comparison voltage VB, the control circuit controls the switch tube to be switched off through the control end VGP, and the output end VOUT outputs the power supply voltage VDD.
2. The boost circuit of claim 1, wherein the switch transistor is a PMOS transistor MP, a source of the PMOS transistor MP is connected to a power voltage VDD, a gate of the PMOS transistor MP is connected to a control terminal VGP, and a drain of the PMOS transistor MP is connected to an output terminal VOUT.
3. The boost circuit of claim 1, wherein the voltage circuit comprises a PMOS transistor M3, a PMOS transistor M4, and a resistor R1, wherein a source of the PMOS transistor M3 is connected to one end of the resistor R1 and receives a zero temperature coefficient current at the same time, another end of the resistor R1 is connected to a source of the PMOS transistor M4, a gate of the PMOS transistor M3 is connected to the output terminal VOUT, and a gate of the PMOS transistor M4 is connected to the input terminal VIN.
4. A booster circuit as claimed in claim 3, characterized in that the comparison voltage VB ═ VIN+ IM 4R 1, wherein VINThe voltage input to the input terminal VIN is,IM4 is the zero temperature coefficient current flowing through resistor R1.
5. The boost circuit of claim 1, wherein the control circuit comprises a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6, the first current mirror is connected to the power supply voltage VDD and the voltage circuit, the drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M5, the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the control terminal VGP.
6. The voltage boosting circuit as claimed in claim 5, wherein said first current mirror comprises a PMOS transistor M1 and a PMOS transistor M2, wherein the source of said PMOS transistor M1 is connected to the source of PMOS transistor M2 and to the supply voltage VDD, the gate of said PMOS transistor M1 is connected to the gate of PMOS transistor M2, the drain of said PMOS transistor M1 is connected to the drain of NMOS transistor M5, and the drain of said NMOS transistor M2 is connected to the voltage circuit.
7. The booster circuit of claim 1, wherein the booster circuit further comprises a zero temperature coefficient current circuit that generates a zero temperature coefficient current, the zero temperature coefficient current circuit being coupled between a supply voltage VDD and the control circuit.
8. The booster circuit according to claim 7, wherein the zero temperature coefficient current circuit comprises an amplifier OPA0, an NMOS tube M0, a current mirror, and a resistor R0, wherein a positive input terminal of the amplifier OPA0 is connected to a reference voltage VREF, a negative input terminal of the amplifier OPA0 is grounded through a resistor R0, a negative input terminal of the amplifier OPA0 is connected to a source of the NMOS tube M0, a gate of the NMOS tube M0 is connected to an output terminal of the amplifier OPA0, a drain of the NMOS tube M0 is connected to the current mirror, and the current mirror is connected to a power supply voltage VDD and the control circuit.
9. The booster circuit as claimed in claim 8, wherein the current mirror comprises a PMOS transistor MS0 and a PMOS transistor MS1, the drain and gate of the PMOS transistor MS0 are connected to and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1, the source of the PMOS transistor MS0 is connected to the source of the PMOS transistor MS1 and the power supply voltage VDD, and the drain of the PMOS transistor MS1 is connected to the control circuit.
10. An amplifier comprising the booster circuit according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111546653.6A CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
| PCT/CN2022/139331 WO2023109908A1 (en) | 2021-12-16 | 2022-12-15 | Booster circuit, buck circuit and amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111546653.6A CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
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| Publication Number | Publication Date |
|---|---|
| CN114221540A true CN114221540A (en) | 2022-03-22 |
| CN114221540B CN114221540B (en) | 2023-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111546653.6A Active CN114221540B (en) | 2021-12-16 | 2021-12-16 | Boost circuit and amplifier |
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| Country | Link |
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| CN (1) | CN114221540B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114489214A (en) * | 2022-03-28 | 2022-05-13 | 苏州贝克微电子股份有限公司 | Circuit structure capable of reducing input-output voltage difference |
| WO2023109908A1 (en) * | 2021-12-16 | 2023-06-22 | 思瑞浦微电子科技(上海)有限责任公司 | Booster circuit, buck circuit and amplifier |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070115741A1 (en) * | 2005-11-21 | 2007-05-24 | Sang-Hwa Jung | Current Sensing Circuit and Boost Converter Having the Same |
| US7301321B1 (en) * | 2006-09-06 | 2007-11-27 | Faraday Technology Corp. | Voltage reference circuit |
| CN101136248A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Charge pump output high-pressure control device |
| US20110012581A1 (en) * | 2009-07-15 | 2011-01-20 | Aicestar Technology(Suzhou) Corporation | Bandgap circuit having a zero temperature coefficient |
| TW201336226A (en) * | 2012-02-24 | 2013-09-01 | Novatek Microelectronics Corp | Multi power domain operational amplifier and voltage generator using the same |
| CN105743343A (en) * | 2016-03-24 | 2016-07-06 | 西安电子科技大学昆山创新研究院 | High-efficiency DC-DC boost converter |
| CN107179797A (en) * | 2017-05-27 | 2017-09-19 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator |
| CN109392218A (en) * | 2017-08-09 | 2019-02-26 | 富士电机株式会社 | Dimming device and power-converting device |
| CN109656299A (en) * | 2019-01-08 | 2019-04-19 | 上海华虹宏力半导体制造有限公司 | LDO circuit |
-
2021
- 2021-12-16 CN CN202111546653.6A patent/CN114221540B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070115741A1 (en) * | 2005-11-21 | 2007-05-24 | Sang-Hwa Jung | Current Sensing Circuit and Boost Converter Having the Same |
| US7301321B1 (en) * | 2006-09-06 | 2007-11-27 | Faraday Technology Corp. | Voltage reference circuit |
| CN101136248A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Charge pump output high-pressure control device |
| US20110012581A1 (en) * | 2009-07-15 | 2011-01-20 | Aicestar Technology(Suzhou) Corporation | Bandgap circuit having a zero temperature coefficient |
| TW201336226A (en) * | 2012-02-24 | 2013-09-01 | Novatek Microelectronics Corp | Multi power domain operational amplifier and voltage generator using the same |
| CN105743343A (en) * | 2016-03-24 | 2016-07-06 | 西安电子科技大学昆山创新研究院 | High-efficiency DC-DC boost converter |
| CN107179797A (en) * | 2017-05-27 | 2017-09-19 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator |
| CN109392218A (en) * | 2017-08-09 | 2019-02-26 | 富士电机株式会社 | Dimming device and power-converting device |
| CN109656299A (en) * | 2019-01-08 | 2019-04-19 | 上海华虹宏力半导体制造有限公司 | LDO circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109908A1 (en) * | 2021-12-16 | 2023-06-22 | 思瑞浦微电子科技(上海)有限责任公司 | Booster circuit, buck circuit and amplifier |
| CN114489214A (en) * | 2022-03-28 | 2022-05-13 | 苏州贝克微电子股份有限公司 | Circuit structure capable of reducing input-output voltage difference |
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|---|---|
| CN114221540B (en) | 2023-12-12 |
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