WO2023109908A1 - Booster circuit, buck circuit and amplifier - Google Patents

Booster circuit, buck circuit and amplifier Download PDF

Info

Publication number
WO2023109908A1
WO2023109908A1 PCT/CN2022/139331 CN2022139331W WO2023109908A1 WO 2023109908 A1 WO2023109908 A1 WO 2023109908A1 CN 2022139331 W CN2022139331 W CN 2022139331W WO 2023109908 A1 WO2023109908 A1 WO 2023109908A1
Authority
WO
WIPO (PCT)
Prior art keywords
nmos transistor
pmos transistor
circuit
source
gate
Prior art date
Application number
PCT/CN2022/139331
Other languages
French (fr)
Chinese (zh)
Inventor
汪鹏
Original Assignee
思瑞浦微电子科技(上海)有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202111546682.2A external-priority patent/CN114221541A/en
Priority claimed from CN202111546653.6A external-priority patent/CN114221540B/en
Application filed by 思瑞浦微电子科技(上海)有限责任公司 filed Critical 思瑞浦微电子科技(上海)有限责任公司
Publication of WO2023109908A1 publication Critical patent/WO2023109908A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the invention relates to the field of integrated circuits, in particular to a voltage boosting circuit, a voltage reducing circuit and an amplifier.
  • Both the boost circuit and the step-down circuit are one of the commonly used circuit structures in amplifiers.
  • the existing boost circuit and step-down circuit have complicated structure and high cost, and the step-up and step-down values are easily affected by the process, thus bringing uncertainty to the accuracy of the step-up and step-down of the entire circuit.
  • the object of the present invention is to provide a voltage boosting circuit, a voltage reducing circuit and an amplifier, the accuracy of which is not affected by the process.
  • an embodiment of the present invention provides a boost circuit, including: a switch tube, a voltage circuit and a control circuit.
  • the switch tube is connected to the power supply voltage VDD and the output terminal VOUT; the voltage circuit receives a zero temperature coefficient current and provides a comparison voltage VB at the same time; the control circuit is connected between the power supply voltage VDD and the voltage circuit and is connected to the switch tube at the same time.
  • VDD is greater than the comparison voltage VB
  • the output terminal VOUT outputs the comparison voltage VB;
  • the control circuit controls the switch to conduct through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD .
  • the switch transistor is a PMOS transistor MP
  • the source of the PMOS transistor MP is connected to the power supply voltage VDD
  • the gate of the PMOS transistor MP is connected to the control terminal VGP
  • the PMOS transistor MP is connected to the control terminal VGP.
  • the drain of the tube MP is connected to the output terminal VOUT.
  • the voltage circuit includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1.
  • the source of the PMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current, so The other end of the resistor R1 is connected to the source of the PMOS transistor M4, the gate of the PMOS transistor M3 is connected to the output terminal VOUT, and the gate of the PMOS transistor M4 is connected to the input terminal VIN.
  • the comparison voltage VB VIN+IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
  • the control circuit includes a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6, and the first current mirror is connected to a power supply voltage VDD and a voltage circuit, so
  • the drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, and the gate of the NMOS transistor M6 is connected to the NMOS
  • the gate of the transistor M5, the source of the NMOS transistor M6 are grounded, and the drain of the NMOS transistor M6 is connected to the control terminal VGP.
  • the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the power supply voltage VDD, the The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
  • the boost circuit further includes a zero temperature coefficient current circuit that generates a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the power supply voltage VDD and the control circuit.
  • the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS transistor M0, a current mirror, and a resistor R0, the positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, and the amplifier OPA0
  • the negative input end of the amplifier OPA0 is grounded through the resistor R0, the negative input end of the amplifier OPA0 is connected to the source of the NMOS transistor M0, the gate of the NMOS transistor M0 is connected to the output end of the amplifier OPA0, and the drain of the NMOS transistor M0 is connected to A current mirror, the current mirror is connected to the power supply voltage VDD and the control circuit.
  • the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, and the drain of the PMOS transistor MS0 is connected to the gate and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1.
  • the gate, the source of the PMOS transistor MS0 is connected to the source of the PMOS transistor MS1 and the power supply voltage VDD, and the drain of the PMOS transistor MS1 is connected to the control circuit.
  • the present invention also provides an amplifier, including the above-mentioned boosting circuit.
  • the invention also provides a step-down circuit, including: a switch tube, a voltage circuit and a control circuit.
  • the switch tube is connected to the ground voltage VSS and the output terminal VOUT; the voltage circuit receives a zero temperature coefficient current and simultaneously provides a comparison voltage VB; the control circuit is connected between the ground voltage VSS and the voltage circuit and is connected to the switch tube at the same time; the local voltage VSS When the voltage is lower than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB. When the ground voltage VSS is greater than the comparison voltage VB, the control circuit controls the switch to conduct through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS.
  • the switch tube is an NMOS transistor MN
  • the source of the NMOS transistor MN is connected to the ground voltage VSS
  • the gate of the NMOS transistor MN is connected to the control terminal VGN
  • the NMOS transistor MN The drain of the tube MN is connected to the output terminal VOUT.
  • the voltage circuit includes an NMOS transistor M3, an NMOS transistor M4, and a resistor R1.
  • the source of the NMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current, so The other end of the resistor R1 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the output terminal VOUT, and the gate of the NMOS transistor M4 is connected to the input terminal VIN.
  • the comparison voltage VB VIN-IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the current with zero temperature coefficient flowing through the resistor R1.
  • the control circuit includes a current mirror, a current source I1, a PMOS transistor M5, and a PMOS transistor M6, the current mirror is connected to the ground voltage VSS and a voltage circuit, and the PMOS transistor M5
  • the drain of the PMOS transistor M5 is connected to the gate and one end of the current source I1 and the current mirror, the source of the PMOS transistor M5 is connected to the other end of the current source I1 and the power supply voltage VDD, and the gate of the PMOS transistor M6 is connected to the PMOS transistor M5
  • the gate, the source of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M6 is connected to the control terminal VGN.
  • the current mirror includes an NMOS transistor M1 and an NMOS transistor M2, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS, and the NMOS transistor M1
  • the gate of M1 is connected to the gate of the NMOS transistor M2, the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
  • the step-down circuit further includes a zero temperature coefficient current circuit that generates a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the ground voltage VSS and the control circuit.
  • the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS transistor M0, a resistor R0, a first current mirror, and a second current mirror, and the positive input terminal of the amplifier OPA0 is connected to a reference Voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0, the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0, the The drain of the NMOS transistor M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit.
  • the first current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1
  • the second current mirror includes an NMOS transistor MS2 and an NMOS transistor MS3, and the drain of the PMOS transistor MS0 connected to the gate and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1, the source of the PMOS transistor MS0 is connected to the power supply voltage VDD, the source of the PMOS transistor MS1 is connected to the power supply voltage VDD, and the PMOS transistor MS1 is connected to the power supply voltage VDD.
  • the drain of MS1 is connected to the drain and gate of the NMOS transistor MS2 and the gate of the NMOS transistor MS3, the source of the PMOS transistor MS2 is grounded, the drain of the PMOS transistor MS3 is connected to the control circuit, and the gate of the PMOS transistor MS3 Source ground.
  • the present invention also provides an amplifier, including the above-mentioned step-down circuit.
  • the step-up circuit compares the comparison voltage VB with the power supply voltage VDD, and when the power supply voltage VDD is not exceeded, the output terminal VOUT outputs the lower voltage between the comparison voltage VB and the power supply voltage VDD. Since the comparison voltage VB is mainly affected by the zero temperature coefficient voltage, it can avoid being affected by the process, realize precise boosting, and improve boosting accuracy.
  • the step-down circuit compares the comparison voltage VB with the ground voltage VSS, and when it is not lower than the ground voltage VSS, the output terminal VOUT outputs the higher voltage of the comparison voltage VB and the ground voltage VSS, because the comparison voltage VB is mainly affected by the zero temperature coefficient Voltage influence, so as to avoid being affected by the process, realize precise step-down, and improve step-down accuracy.
  • FIG. 1 is a schematic circuit diagram of a boost circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic circuit diagram of a zero temperature coefficient current circuit according to Embodiment 1 of the present invention.
  • Fig. 3 is a system block diagram of an amplifier according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic circuit diagram of a step-down circuit according to Embodiment 2 of the present invention.
  • FIG. 5 is a circuit schematic diagram of a zero temperature coefficient current circuit according to Embodiment 2 of the present invention.
  • Fig. 6 is a system block diagram of an amplifier according to Embodiment 2 of the present invention.
  • the boost circuit includes: a switch tube, a zero temperature coefficient current circuit 10 , a voltage circuit 20 and a control circuit 30 .
  • the switch tube is connected to the power supply voltage VDD and the output terminal VOUT.
  • the zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence, the zero temperature coefficient current circuit 10 is connected to the power supply voltage VDD at the same time, and the voltage circuit 20 is connected to the input terminal VIN, the output terminal VOUT and the internal circuit 40 of the amplifier OPA at the same time .
  • the voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB at the same time.
  • the control circuit 30 is used to control the turn-on and turn-off of the switch tube.
  • the control circuit 30 controls the switch to conduct through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD, thereby It is realized that the output voltage of the output terminal VOUT does not exceed the power supply voltage VDD.
  • the switch tube is a PMOS tube MP
  • the source of the PMOS tube MP is connected to the power supply voltage VDD
  • the gate of the PMOS tube MP is connected to the control terminal VGP and is connected to the internal circuit 40 of the amplifier OPA through the control terminal VGP
  • the PMOS tube MP The drain is connected to the output terminal VOUT.
  • the boost circuit is a part of the amplifier OPA.
  • the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors. The internal circuit 40 is used to maintain the operation of the boost circuit and other circuits.
  • the zero temperature coefficient current circuit 10 includes an amplifier OPA0 , an NMOS transistor M0 , a current mirror, and a resistor R0 .
  • the positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, and the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0.
  • the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0 , the drain of the NMOS transistor M0 is connected to the current mirror, and the current mirror is connected to the power supply voltage VDD and the control circuit 30 .
  • the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, the drain and the gate of the PMOS transistor MS0 are connected and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1, and the source of the PMOS transistor MS0 is connected to the gate of the PMOS transistor MS1.
  • the source and the power supply voltage VDD, and the drain of the PMOS transistor MS1 are connected to the control circuit 30 through the VS2 terminal.
  • the zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance value of the resistor R0.
  • the zero temperature coefficient current flows to the voltage circuit 20 through the VS2 terminal.
  • the voltage circuit 20 includes a PMOS transistor M3 , a PMOS transistor M4 and a resistor R1 .
  • the source of the PMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current.
  • the source of the PMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD2 end.
  • the other end of the resistor R1 is connected to the source of the PMOS transistor M4, the gate of the PMOS transistor M3 is connected to the output terminal VOUT, and the gate of the PMOS transistor M4 is connected to the input terminal VIN.
  • Both the PMOS transistor M3 and the PMOS transistor M4 are PMOS transistors, which realize rail-to-rail input and reduce circuit cost.
  • the comparison voltage VB VIN+IM4*R1, wherein, VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
  • the zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. That is, the voltage on the resistor R1 is mainly affected by the reference voltage VREF, which can realize precise boosting, avoid process influence, and improve precision.
  • the control circuit 30 includes a first current mirror, a current source I1 , an NMOS transistor M5 and an NMOS transistor M6 .
  • the first current mirror is connected to the power supply voltage VDD and the voltage circuit 20 .
  • the zero temperature coefficient current circuit 10 is connected between the first current mirror and the power supply voltage VDD.
  • the drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, and the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M5 , the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the gate of the PMOS transistor MP through the control terminal VGP.
  • the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2.
  • the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the power supply voltage VDD.
  • the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the drain connected to the PMOS transistor MS1. VS2 side.
  • the gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2 to form a VG2 terminal.
  • the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5 to form a VG5 terminal.
  • the drain of the NMOS transistor M2 is connected to the source of the resistor R1 and the PMOS transistor M3 through the VD2 terminal.
  • the boost circuit when the power supply voltage VDD is greater than the comparison voltage VB, by setting the current of the current source I1 to be greater than the current passing through the PMOS transistor M1, the VG5 terminal is at a low voltage at this time, and the NMOS transistor M6 is turned off.
  • the output terminal OUT outputs the comparison voltage VB.
  • the PMOS transistor M2 When the power supply voltage VDD is lower than the comparison voltage VB, the PMOS transistor M2 enters the linear region, and the difference between the voltage at the VS2 terminal and the voltage at the VG2 terminal becomes larger. At this time, the current passing through the PMOS transistor M1 is greater than the current of the current source I1, and the NMOS transistor M6 is turned on. Therefore, the VGP terminal is at a low voltage, the PMOS transistor MP is turned on, and the output terminal OUT outputs the power supply voltage VDD at this time.
  • other embodiments also provide an amplifier OPA, including the above-mentioned boosting circuit.
  • the boost circuit is part of the amplifier OPA.
  • the output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA.
  • the positive input terminal of the amplifier OPA is connected to the input terminal VIN.
  • the step-down circuit includes: a switch tube, a zero temperature coefficient current circuit 10 , a voltage circuit 20 and a control circuit 30 .
  • the switch tube is connected to the ground voltage VSS and the output terminal VOUT.
  • the zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence.
  • the zero temperature coefficient current circuit 10 is also connected to the ground voltage VSS.
  • the voltage circuit 20 is simultaneously connected to an internal circuit 40 of the amplifier OPA.
  • the voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB at the same time.
  • the control circuit 30 is used to control the turn-on and turn-off of the switch tube. When the local voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB.
  • the control circuit controls the conduction of the switch through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS, thereby ensuring the output terminal The output voltage of VOUT is not less than the ground voltage VSS.
  • the switch tube is an NMOS tube MN
  • the source of the NMOS tube MN is connected to the ground voltage VSS
  • the gate of the NMOS tube MN is connected to the control terminal VGN and is connected to the internal circuit 40 of the amplifier OPA through the control terminal VGN
  • the NMOS tube MN The drain is connected to the output terminal VOUT.
  • the step-down circuit is a part of the amplifier OPA, wherein the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors, and the internal circuit 40 is used to maintain the operation of the step-down circuit and other circuits.
  • the zero temperature coefficient current circuit 10 includes an amplifier OPA0 , an NMOS transistor M0 , a resistor R0 , a first current mirror and a second current mirror.
  • the positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF
  • the negative input terminal of the amplifier OPA0 is grounded through the resistor R0
  • the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0
  • the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0.
  • the drain of the NMOS transistor M0 is connected to the first current mirror
  • the first current mirror is connected to the second current mirror
  • the second current mirror is connected to the ground voltage VSS and the control circuit 30 .
  • the first current mirror includes PMOS transistor MS0 and PMOS transistor MS1
  • the second current mirror includes NMOS transistor MS2 and NMOS transistor MS3.
  • the drain and gate of the PMOS transistor MS0 are connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1
  • the source of the PMOS transistor MS0 is connected to the power supply voltage VDD.
  • the source of the PMOS transistor MS1 is connected to the power supply voltage VDD
  • the drain of the PMOS transistor MS1 is connected to the drain and gate of the NMOS transistor MS2 and the gate of the NMOS transistor MS3.
  • the source of the PMOS transistor MS2 is grounded, the drain of the PMOS transistor MS3 is connected to the control circuit 30 through the VS2 terminal, and the source of the PMOS transistor MS3 is grounded.
  • the zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance value of the resistor R0.
  • the zero temperature coefficient current flows to the voltage circuit 20 through the VS2 terminal.
  • the voltage circuit 20 includes an NMOS transistor M3 , an NMOS transistor M4 and a resistor R1 .
  • the source of the NMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current.
  • the source of the NMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD2 terminal.
  • the other end of the resistor R1 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the output terminal VOUT, and the gate of the NMOS transistor M4 is connected to the input voltage VIN.
  • Both the NMOS tube M3 and the NMOS tube M4 use NMOS tubes, which realize rail-to-rail input and reduce circuit costs.
  • Comparison voltage VB VIN-IM4*R1, wherein, VIN is the voltage input from the input terminal VIN, and IM4 is the current with zero temperature coefficient flowing through the resistor R1.
  • the zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. That is, the voltage on the resistor R1 is mainly affected by the reference voltage VREF, so that precise drop can be achieved, the influence of the process is avoided, and the precision is improved.
  • the control circuit 30 includes a current mirror, a current source I1 , a PMOS transistor M5 and a PMOS transistor M6 .
  • the current mirror is connected to the ground voltage VSS and the voltage circuit 20.
  • a zero temperature coefficient current circuit 10 is connected between the current mirror and the ground voltage VSS, and the current mirror is connected to the zero temperature coefficient current circuit 10 through the VS2 terminal.
  • the mirror is connected to the voltage circuit 20 through the VD2 terminal.
  • the drain of the PMOS transistor M5 is connected to the gate, one end of the current source I1 and the current mirror, and the source of the PMOS transistor M5 is connected to the other end of the current source I1 and to the power supply voltage VDD.
  • the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M5, the source of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M6 is connected to the gate of the NMOS transistor MN through the control terminal VGN.
  • the current mirror includes NMOS transistor M1 and NMOS transistor M2.
  • the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS.
  • the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS.
  • the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the drain of the NMOS transistor MS3 through the VS2 terminal.
  • the gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 to form a VG2 terminal.
  • the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M5 to form a VG5 terminal.
  • the drain of the NMOS transistor M2 is connected to the resistor R1 and the source of the NMOS transistor M3 through the VD2 terminal.
  • step-down circuit it can be seen that when the local voltage VSS is lower than the comparison voltage VB, by setting the current of the current source I1 to be greater than the current passing through the NMOS transistor M1, the VG5 terminal is at a high voltage at this time, and the PMOS transistor M6 is turned off. At this time The output terminal OUT outputs a comparison voltage VB.
  • the NMOS transistor M2 When the local voltage VSS is greater than the voltage VB, the NMOS transistor M2 enters the linear region, and the difference between the voltage at the VS2 terminal and the voltage at the VG2 terminal becomes larger. At this time, the current passing through the NMOS transistor M1 is greater than the current of the current source I1, and the PMOS transistor M6 is turned on so that The VGN terminal is a high voltage, the NMOS transistor MN is turned on, and the output terminal OUT outputs the ground voltage VSS at this time.
  • other embodiments also provide an amplifier OPA, including the above-mentioned step-down circuit.
  • the step-down circuit is part of the amplifier OPA.
  • the output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA.
  • the positive input terminal of the amplifier OPA is connected to the input terminal VIN.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The present invention relates to a booster circuit, a buck circuit and an amplifier. The booster circuit and the buck circuit each comprise a switch tube, a voltage circuit and a control circuit. According to the booster circuit, the buck circuit and the amplifier provided by embodiments of the present invention, in the booster circuit, a comparison voltage is compared with a power supply voltage, in the case of not exceeding the power supply voltage, an output end outputs the higher one in the comparison voltage and the power supply voltage, and the comparison voltage is mainly affected by a zero temperature coefficient voltage, so that the influence of a process can be avoided, accurate boosting is realized, and the precision is improved. According to the buck circuit, by comparing a comparison voltage with a ground voltage, in the case of being not lower than the ground voltage, an output end outputs the higher one in the comparison voltage and the ground voltage, and the comparison voltage is mainly affected by a zero temperature coefficient voltage, so that the influence of a process can be avoided, accurate voltage reduction is realized, and the precision is improved.

Description

升压电路、降压电路及放大器Step-up circuit, step-down circuit and amplifier
本发明要求2021年12月16日向中国专利局提交的、申请号为202111546653.6、发明名称为“升压电路及放大器”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。The present invention claims the priority of the Chinese patent application with the application number 202111546653.6 and the invention title "Boost Circuit and Amplifier" filed with the Chinese Patent Office on December 16, 2021, the entire content of which is incorporated herein by reference.
本发明要求2021年12月16日向中国专利局提交的、申请号为202111546682.2、发明名称为“降压电路及放大器”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。The present invention claims the priority of the Chinese patent application with the application number 202111546682.2 and the invention title "Step-down Circuit and Amplifier" filed with the Chinese Patent Office on December 16, 2021, the entire contents of which are incorporated herein by reference.
技术领域technical field
本发明关于集成电路领域，特别是关于一种升压电路、降压电路及放大器。The invention relates to the field of integrated circuits, in particular to a voltage boosting circuit, a voltage reducing circuit and an amplifier.
背景技术Background technique
升压电路和降压电路都是放大器中常用的电路结构之一。现有的升压电路和降压电路的结构复杂，成本高，同时升压、降压大小容易受工艺影响，从而对整个电路的升压和降压的精度带来不确定性。Both the boost circuit and the step-down circuit are one of the commonly used circuit structures in amplifiers. The existing boost circuit and step-down circuit have complicated structure and high cost, and the step-up and step-down values are easily affected by the process, thus bringing uncertainty to the accuracy of the step-up and step-down of the entire circuit.
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。The information disclosed in this Background section is only for enhancing the understanding of the general background of the present invention and should not be taken as an acknowledgment or any form of suggestion that the information constitutes the prior art that is already known to those skilled in the art.
发明内容Contents of the invention
本发明的目的在于提供一种升压电路、降压电路及放大器，其升压和降压的精度不受工艺影响。The object of the present invention is to provide a voltage boosting circuit, a voltage reducing circuit and an amplifier, the accuracy of which is not affected by the process.
为实现上述目的，本发明的实施例提供了一种升压电路，包括：开关管、电压电路以及控制电路。To achieve the above object, an embodiment of the present invention provides a boost circuit, including: a switch tube, a voltage circuit and a control circuit.
开关管连接电源电压VDD和输出端VOUT；电压电路接收零温度系数电流，同时提供一比较电压VB；控制电路连接于所述电源电压VDD与电压电路之间且同时与开关管连接，当电源电压VDD大于比较电压VB时，所述输出端VOUT输出比较电压VB，当电源电压VDD小于比较电压VB时，所述控制电路通过控制端VGP控制开关管导通，所述输出端VOUT输出电源电压VDD。The switch tube is connected to the power supply voltage VDD and the output terminal VOUT; the voltage circuit receives a zero temperature coefficient current and provides a comparison voltage VB at the same time; the control circuit is connected between the power supply voltage VDD and the voltage circuit and is connected to the switch tube at the same time. When VDD is greater than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB; when the power supply voltage VDD is less than the comparison voltage VB, the control circuit controls the switch to conduct through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD .
在本发明的一个或多个实施方式中，所述开关管为PMOS管MP，所述PMOS管MP的源极连接电源电压VDD，所述PMOS管MP的栅极连接控制端VGP，所述PMOS管MP的漏极连接输出端VOUT。In one or more embodiments of the present invention, the switch transistor is a PMOS transistor MP, the source of the PMOS transistor MP is connected to the power supply voltage VDD, the gate of the PMOS transistor MP is connected to the control terminal VGP, and the PMOS transistor MP is connected to the control terminal VGP. The drain of the tube MP is connected to the output terminal VOUT.
在本发明的一个或多个实施方式中，所述电压电路包括PMOS管M3、PMOS管M4和电阻R1，所述PMOS管M3的源极连接电阻R1的一端且同时接收零温度系数电流，所述电阻R1的另一端连接PMOS管M4的源极，所述PMOS管M3的栅极连接输出端VOUT，所述PMOS管M4的栅极连接输入端VIN。In one or more embodiments of the present invention, the voltage circuit includes a PMOS transistor M3, a PMOS transistor M4, and a resistor R1. The source of the PMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current, so The other end of the resistor R1 is connected to the source of the PMOS transistor M4, the gate of the PMOS transistor M3 is connected to the output terminal VOUT, and the gate of the PMOS transistor M4 is connected to the input terminal VIN.
在本发明的一个或多个实施方式中，所述比较电压VB＝VIN+IM4*R1，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。In one or more embodiments of the present invention, the comparison voltage VB=VIN+IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
在本发明的一个或多个实施方式中，所述控制电路包括第一电流镜、电流源I1、NMOS管M5和NMOS管M6，所述第一电流镜与电源电压VDD和电压电路连接，所述NMOS管M5的漏极连接栅极以及电流源I1的一端和第一电流镜，所述NMOS管M5的源极连接电流源I1的另一端并接地，所述NMOS管M6的栅极连接NMOS管M5的栅极，所述NMOS管M6的源极接地，所述NMOS管M6的漏极连接控制端VGP。In one or more embodiments of the present invention, the control circuit includes a first current mirror, a current source I1, an NMOS transistor M5, and an NMOS transistor M6, and the first current mirror is connected to a power supply voltage VDD and a voltage circuit, so The drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, and the gate of the NMOS transistor M6 is connected to the NMOS The gate of the transistor M5, the source of the NMOS transistor M6 are grounded, and the drain of the NMOS transistor M6 is connected to the control terminal VGP.
在本发明的一个或多个实施方式中，所述第一电流镜包括PMOS管M1和PMOS管M2，所述PMOS管M1的源极连接PMOS管M2的源极并连接电源电压VDD，所述PMOS管M1的栅极连接PMOS管M2的栅极，所述PMOS管M1的漏极连接NMOS管M5的漏极，所述NMOS管M2的漏极连接电压电路。In one or more embodiments of the present invention, the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the power supply voltage VDD, the The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
在本发明的一个或多个实施方式中，所述升压电路还包括产生零温度系数电流的零温度系数电流电路，所述零温度系数电流电路连接于电源电压VDD和控制电路之间。In one or more embodiments of the present invention, the boost circuit further includes a zero temperature coefficient current circuit that generates a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the power supply voltage VDD and the control circuit.
在本发明的一个或多个实施方式中，所述零温度系数电流电路包括放大器OPA0、NMOS管M0、电流镜、电阻R0，所述放大器OPA0的正极输入端连接基准电压VREF，所述放大器OPA0的负极输入端通过电阻R0接地，所述放大器OPA0的负极输入端与NMOS管M0的源极连接，所述NMOS管M0的栅极连接放大器OPA0的输出端，所述NMOS管M0的漏极连接电流镜，所述电流镜连接电源电压VDD和控制电路。In one or more embodiments of the present invention, the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS transistor M0, a current mirror, and a resistor R0, the positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, and the amplifier OPA0 The negative input end of the amplifier OPA0 is grounded through the resistor R0, the negative input end of the amplifier OPA0 is connected to the source of the NMOS transistor M0, the gate of the NMOS transistor M0 is connected to the output end of the amplifier OPA0, and the drain of the NMOS transistor M0 is connected to A current mirror, the current mirror is connected to the power supply voltage VDD and the control circuit.
在本发明的一个或多个实施方式中，所述电流镜包括PMOS管MS0和PMOS管MS1，所述PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，所述PMOS管MS0的源极连接PMOS管MS1的源极和电源电压VDD，所述PMOS管MS1的漏极连接控制电路。In one or more embodiments of the present invention, the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, and the drain of the PMOS transistor MS0 is connected to the gate and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1. The gate, the source of the PMOS transistor MS0 is connected to the source of the PMOS transistor MS1 and the power supply voltage VDD, and the drain of the PMOS transistor MS1 is connected to the control circuit.
本发明还提供了一种放大器，包括上述的升压电路。The present invention also provides an amplifier, including the above-mentioned boosting circuit.
本发明还提供了一种降压电路，包括：开关管、电压电路以及控制电路。The invention also provides a step-down circuit, including: a switch tube, a voltage circuit and a control circuit.
开关管连接地电压VSS和输出端VOUT；电压电路接收零温度系数电流，同时提供一比较电压VB；控制电路连接于所述地电压VSS与电压电路之间且同时与开关管连接；当地电压VSS小于比较电压VB时，所述输出端VOUT输出比较电压VB，当地电压VSS大于比较电压VB时，所述控制电路通过控制端VGN控制开关管导通，所述输出端VOUT输出地电压VSS。The switch tube is connected to the ground voltage VSS and the output terminal VOUT; the voltage circuit receives a zero temperature coefficient current and simultaneously provides a comparison voltage VB; the control circuit is connected between the ground voltage VSS and the voltage circuit and is connected to the switch tube at the same time; the local voltage VSS When the voltage is lower than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB. When the ground voltage VSS is greater than the comparison voltage VB, the control circuit controls the switch to conduct through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS.
在本发明的一个或多个实施方式中，所述开关管为NMOS管MN，所述NMOS管MN的源极连接地电压VSS，所述NMOS管MN的栅极连接控制端VGN，所述NMOS管MN的漏极连接输出端VOUT。In one or more embodiments of the present invention, the switch tube is an NMOS transistor MN, the source of the NMOS transistor MN is connected to the ground voltage VSS, the gate of the NMOS transistor MN is connected to the control terminal VGN, and the NMOS transistor MN The drain of the tube MN is connected to the output terminal VOUT.
在本发明的一个或多个实施方式中，所述电压电路包括NMOS管M3、NMOS管M4和电阻R1，所述NMOS管M3的源极连接电阻R1的一端且同时接收零温度系数电流，所述电阻R1的另一端连接NMOS管M4的源极，所述NMOS管M3的栅极连接输出端VOUT，所述NMOS管M4的栅极连接输入端VIN。In one or more embodiments of the present invention, the voltage circuit includes an NMOS transistor M3, an NMOS transistor M4, and a resistor R1. The source of the NMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current, so The other end of the resistor R1 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the output terminal VOUT, and the gate of the NMOS transistor M4 is connected to the input terminal VIN.
在本发明的一个或多个实施方式中，所述比较电压VB＝VIN-IM4*R1，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。In one or more embodiments of the present invention, the comparison voltage VB=VIN-IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the current with zero temperature coefficient flowing through the resistor R1.
在本发明的一个或多个实施方式中，所述控制电路包括电流镜、电流源I1、PMOS管M5和PMOS管M6，所述电流镜与地电压VSS和电压电路连接，所述PMOS管M5的漏极连接栅极以及电流源I1的一端和电流镜，所述PMOS管M5的源极连接电流源I1的另一端并连接电源电压VDD，所述PMOS管M6的栅极连接PMOS管M5的栅极，所述PMOS管M6的源极连接电源电压VDD，所述PMOS管M6的漏极连接控制端VGN。In one or more embodiments of the present invention, the control circuit includes a current mirror, a current source I1, a PMOS transistor M5, and a PMOS transistor M6, the current mirror is connected to the ground voltage VSS and a voltage circuit, and the PMOS transistor M5 The drain of the PMOS transistor M5 is connected to the gate and one end of the current source I1 and the current mirror, the source of the PMOS transistor M5 is connected to the other end of the current source I1 and the power supply voltage VDD, and the gate of the PMOS transistor M6 is connected to the PMOS transistor M5 The gate, the source of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M6 is connected to the control terminal VGN.
在本发明的一个或多个实施方式中，所述电流镜包括NMOS管M1和NMOS管M2，所述NMOS管M1的源极连接NMOS管M2的源极并连接地电压VSS，所述NMOS管M1的栅极连接NMOS管M2的栅极，所述NMOS管M1的漏极连接PMOS管M5的漏极，所述NMOS管M2的漏极连接电压电路。In one or more embodiments of the present invention, the current mirror includes an NMOS transistor M1 and an NMOS transistor M2, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS, and the NMOS transistor M1 The gate of M1 is connected to the gate of the NMOS transistor M2, the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
在本发明的一个或多个实施方式中，所述降压电路还包括产生零温度系数电流的零温度系数电流电路，所述零温度系数电流电路连接于地电压VSS和控制电路之间。In one or more embodiments of the present invention, the step-down circuit further includes a zero temperature coefficient current circuit that generates a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the ground voltage VSS and the control circuit.
在本发明的一个或多个实施方式中，所述零温度系数电流电路包括放大器OPA0、NMOS管M0、电阻R0、第一电流镜和第二电流镜，所述放大器OPA0的正极输入端连接基准电压VREF，所述放大器OPA0的负极输入端通过电阻R0接地，所述放大器OPA0的负极输入端与NMOS管M0的源极连接，所述NMOS管M0的栅极连接放大器OPA0 的输出端，所述NMOS管M0的漏极连接第一电流镜，所述第一电流镜连接第二电流镜，所述第二电流镜连接地电压VSS和控制电路。In one or more embodiments of the present invention, the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS transistor M0, a resistor R0, a first current mirror, and a second current mirror, and the positive input terminal of the amplifier OPA0 is connected to a reference Voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0, the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0, the The drain of the NMOS transistor M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit.
在本发明的一个或多个实施方式中，所述第一电流镜包括PMOS管MS0和PMOS管MS1，所述第二电流镜包括NMOS管MS2和NMOS管MS3，所述PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，所述PMOS管MS0的源极连接电源电压VDD，所述PMOS管MS1的源极连接电源电压VDD，所述PMOS管MS1的漏极连接NMOS管MS2的漏极和栅极以及NMOS管MS3的栅极，所述PMOS管MS2的源极接地，所述PMOS管MS3的漏极连接控制电路，所述PMOS管MS3的源极接地。In one or more embodiments of the present invention, the first current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, the second current mirror includes an NMOS transistor MS2 and an NMOS transistor MS3, and the drain of the PMOS transistor MS0 connected to the gate and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1, the source of the PMOS transistor MS0 is connected to the power supply voltage VDD, the source of the PMOS transistor MS1 is connected to the power supply voltage VDD, and the PMOS transistor MS1 is connected to the power supply voltage VDD. The drain of MS1 is connected to the drain and gate of the NMOS transistor MS2 and the gate of the NMOS transistor MS3, the source of the PMOS transistor MS2 is grounded, the drain of the PMOS transistor MS3 is connected to the control circuit, and the gate of the PMOS transistor MS3 Source ground.
本发明还提供了一种放大器，包括上述的降压电路。The present invention also provides an amplifier, including the above-mentioned step-down circuit.
与现有技术相比，根据本发明实施方式的升压电路、降压电路及放大器，升压电路通过将比较电压VB和电源电压VDD进行比较，在不超过电源电压VDD的情况下，输出端VOUT输出比较电压VB和电源电压VDD中低的电压，由于比较电压VB主要受零温度系数电压影响，从而能够避免受到工艺的影响，实现了精准升压，提高了升压精度。Compared with the prior art, according to the step-up circuit, the step-down circuit and the amplifier of the embodiment of the present invention, the step-up circuit compares the comparison voltage VB with the power supply voltage VDD, and when the power supply voltage VDD is not exceeded, the output terminal VOUT outputs the lower voltage between the comparison voltage VB and the power supply voltage VDD. Since the comparison voltage VB is mainly affected by the zero temperature coefficient voltage, it can avoid being affected by the process, realize precise boosting, and improve boosting accuracy.
降压电路通过将比较电压VB和地电压VSS进行比较，在不低于地电压VSS的情况下，输出端VOUT输出比较电压VB和地电压VSS中高的电压，由于比较电压VB主要受零温度系数电压影响，从而能够避免受到工艺的影响，实现了精准降压，提高了降压精度。The step-down circuit compares the comparison voltage VB with the ground voltage VSS, and when it is not lower than the ground voltage VSS, the output terminal VOUT outputs the higher voltage of the comparison voltage VB and the ground voltage VSS, because the comparison voltage VB is mainly affected by the zero temperature coefficient Voltage influence, so as to avoid being affected by the process, realize precise step-down, and improve step-down accuracy.
附图说明Description of drawings
图1是根据本发明实施例一的一种升压电路的电路原理图；FIG. 1 is a schematic circuit diagram of a boost circuit according to Embodiment 1 of the present invention;
图2是根据本发明实施例一的零温度系数电流电路的电路原理图；2 is a schematic circuit diagram of a zero temperature coefficient current circuit according to Embodiment 1 of the present invention;
图3是根据本发明实施例一的放大器的系统框图。Fig. 3 is a system block diagram of an amplifier according to Embodiment 1 of the present invention.
图4是根据本发明实施例二的一种降压电路的电路原理图；FIG. 4 is a schematic circuit diagram of a step-down circuit according to Embodiment 2 of the present invention;
图5是根据本发明实施例二的零温度系数电流电路的电路原理图；5 is a circuit schematic diagram of a zero temperature coefficient current circuit according to Embodiment 2 of the present invention;
图6是根据本发明实施例二的放大器的系统框图。Fig. 6 is a system block diagram of an amplifier according to Embodiment 2 of the present invention.
具体实施方式Detailed ways
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.
实施例1Example 1
如图1所示，升压电路包括：开关管、零温度系数电流电路10、电压电路20以及控制电路30。As shown in FIG. 1 , the boost circuit includes: a switch tube, a zero temperature coefficient current circuit 10 , a voltage circuit 20 and a control circuit 30 .
开关管连接电源电压VDD和输出端VOUT。零温度系数电流电路10、电压电路20和控制电路30依次连接，零温度系数电流电路10同时与电源电压VDD连接，电压电路20同时与输入端VIN、输出端VOUT和放大器OPA的内部电路40连接。电压电路20接收零温度系数电流电路10产生的零温度系数电流，同时提供一比较电压VB。控制电路30用于控制开关管的导通和关断。当电源电压VDD大于比较电压VB时，输出端VOUT输出比较电压VB，当电源电压VDD小于比较电压VB时，控制电路30通过控制端VGP控制开关管导通，输出端VOUT输出电源电压VDD，从而实现输出端VOUT输出的电压不超过电源电压VDD。The switch tube is connected to the power supply voltage VDD and the output terminal VOUT. The zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence, the zero temperature coefficient current circuit 10 is connected to the power supply voltage VDD at the same time, and the voltage circuit 20 is connected to the input terminal VIN, the output terminal VOUT and the internal circuit 40 of the amplifier OPA at the same time . The voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB at the same time. The control circuit 30 is used to control the turn-on and turn-off of the switch tube. When the power supply voltage VDD is greater than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB; when the power supply voltage VDD is less than the comparison voltage VB, the control circuit 30 controls the switch to conduct through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD, thereby It is realized that the output voltage of the output terminal VOUT does not exceed the power supply voltage VDD.
如图1所示，开关管为PMOS管MP，PMOS管MP的源极连接电源电压VDD，PMOS管MP的栅极连接控制端VGP并通过控制端VGP连接放大器OPA的内部电路40，PMOS管MP的漏极连接输出端VOUT。升压电路为放大器OPA的一部分，放大器OPA的内部电路40由多个相连的NMOS管和PMOS管组成，内部电路40用于维持升压电路以及其他电路的运行。As shown in Figure 1, the switch tube is a PMOS tube MP, the source of the PMOS tube MP is connected to the power supply voltage VDD, the gate of the PMOS tube MP is connected to the control terminal VGP and is connected to the internal circuit 40 of the amplifier OPA through the control terminal VGP, and the PMOS tube MP The drain is connected to the output terminal VOUT. The boost circuit is a part of the amplifier OPA. The internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors. The internal circuit 40 is used to maintain the operation of the boost circuit and other circuits.
如图2和图1所示，零温度系数电流电路10包括放大器OPA0、NMOS管M0、电流镜、电阻R0。放大器OPA0的正极输入端连接基准电压VREF，放大器OPA0的负极输入端通过电阻R0接地，放大器OPA0的负极输入端与NMOS管M0的源极连接。NMOS管M0的栅极连接放大器OPA0的输出端，NMOS管M0的漏极连接电流镜，电流镜连接电源电压VDD和控制电路30。As shown in FIG. 2 and FIG. 1 , the zero temperature coefficient current circuit 10 includes an amplifier OPA0 , an NMOS transistor M0 , a current mirror, and a resistor R0 . The positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, and the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0. The gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0 , the drain of the NMOS transistor M0 is connected to the current mirror, and the current mirror is connected to the power supply voltage VDD and the control circuit 30 .
其中，电流镜包括PMOS管MS0和PMOS管MS1，PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，PMOS管MS0的源极连接PMOS管MS1的源极和电源电压VDD，PMOS管MS1的漏极通过VS2端连接控制电路30。零温度系数电流等于基准电压VREF除以电阻R0的阻值。零温度系数电流通过VS2端流向电压电路20。Wherein, the current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, the drain and the gate of the PMOS transistor MS0 are connected and connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1, and the source of the PMOS transistor MS0 is connected to the gate of the PMOS transistor MS1. The source and the power supply voltage VDD, and the drain of the PMOS transistor MS1 are connected to the control circuit 30 through the VS2 terminal. The zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance value of the resistor R0. The zero temperature coefficient current flows to the voltage circuit 20 through the VS2 terminal.
如图1所示，电压电路20包括PMOS管M3、PMOS管M4和电阻R1。PMOS管 M3的源极连接电阻R1的一端且同时接收零温度系数电流，具体的，PMOS管M3的源极连接电阻R1的一端且通过VD2端连接控制电路30。电阻R1的另一端连接PMOS管M4的源极，PMOS管M3的栅极连接输出端VOUT，PMOS管M4的栅极连接输入端VIN。PMOS管M3、PMOS管M4均采用PMOS管，实现了轨到轨输入，降低了电路成本。As shown in FIG. 1 , the voltage circuit 20 includes a PMOS transistor M3 , a PMOS transistor M4 and a resistor R1 . The source of the PMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current. Specifically, the source of the PMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD2 end. The other end of the resistor R1 is connected to the source of the PMOS transistor M4, the gate of the PMOS transistor M3 is connected to the output terminal VOUT, and the gate of the PMOS transistor M4 is connected to the input terminal VIN. Both the PMOS transistor M3 and the PMOS transistor M4 are PMOS transistors, which realize rail-to-rail input and reduce circuit cost.
比较电压VB＝VIN+IM4*R1，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。该零温度系数电流由基准电压VREF和电阻R0决定。即电阻R1上的电压主要受到基准电压VREF的影响，可实现精准升压，避免了工艺影响，提高了精度。The comparison voltage VB=VIN+IM4*R1, wherein, VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1. The zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. That is, the voltage on the resistor R1 is mainly affected by the reference voltage VREF, which can realize precise boosting, avoid process influence, and improve precision.
如图1所示，控制电路30包括第一电流镜、电流源I1、NMOS管M5和NMOS管M6。第一电流镜与电源电压VDD和电压电路20连接，在本实施例中，第一电流镜与电源电压VDD之间连接有零温度系数电流电路10。NMOS管M5的漏极连接栅极以及电流源I1的一端和第一电流镜，NMOS管M5的源极连接电流源I1的另一端并接地，NMOS管M6的栅极连接NMOS管M5的栅极，NMOS管M6的源极接地，NMOS管M6的漏极通过控制端VGP连接PMOS管MP的栅极。As shown in FIG. 1 , the control circuit 30 includes a first current mirror, a current source I1 , an NMOS transistor M5 and an NMOS transistor M6 . The first current mirror is connected to the power supply voltage VDD and the voltage circuit 20 . In this embodiment, the zero temperature coefficient current circuit 10 is connected between the first current mirror and the power supply voltage VDD. The drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, and the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M5 , the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the gate of the PMOS transistor MP through the control terminal VGP.
第一电流镜包括PMOS管M1和PMOS管M2。PMOS管M1的源极连接PMOS管M2的源极并连接电源电压VDD，在本实施例中，PMOS管M1的源极和PMOS管M2的源极相连并连接与PMOS管MS1的漏极连接的VS2端。PMOS管M1的栅极连接PMOS管M2的栅极并形成VG2端。PMOS管M1的漏极连接NMOS管M5的漏极并形成VG5端。NMOS管M2的漏极通过VD2端连接电阻R1和PMOS管M3的源极。The first current mirror includes a PMOS transistor M1 and a PMOS transistor M2. The source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the power supply voltage VDD. In this embodiment, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the drain connected to the PMOS transistor MS1. VS2 side. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2 to form a VG2 terminal. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5 to form a VG5 terminal. The drain of the NMOS transistor M2 is connected to the source of the resistor R1 and the PMOS transistor M3 through the VD2 terminal.
根据上述升压电路可知，当电源电压VDD大于比较电压VB时，通过将电流源I1的电流设置成大于经过PMOS管M1的电流，此时VG5端处为低电压，NMOS管M6关断，此时输出端OUT输出比较电压VB。According to the above boost circuit, when the power supply voltage VDD is greater than the comparison voltage VB, by setting the current of the current source I1 to be greater than the current passing through the PMOS transistor M1, the VG5 terminal is at a low voltage at this time, and the NMOS transistor M6 is turned off. When the output terminal OUT outputs the comparison voltage VB.
当电源电压VDD小于比较电压VB时，PMOS管M2进入线性区，VS2端的电压和VG2端的电压的差值变大，此时经过PMOS管M1的电流大于电流源I1的电流，NMOS管M6导通从而使得VGP端为低电压，PMOS管MP导通，此时输出端OUT输出电源电压VDD。When the power supply voltage VDD is lower than the comparison voltage VB, the PMOS transistor M2 enters the linear region, and the difference between the voltage at the VS2 terminal and the voltage at the VG2 terminal becomes larger. At this time, the current passing through the PMOS transistor M1 is greater than the current of the current source I1, and the NMOS transistor M6 is turned on. Therefore, the VGP terminal is at a low voltage, the PMOS transistor MP is turned on, and the output terminal OUT outputs the power supply voltage VDD at this time.
如图3所示，其他实施例中还提供了一种放大器OPA，包括上述的升压电路。升压电路为放大器OPA的一部分。放大器OPA的输出端VOUT连接放大器OPA的负极输入端。放大器OPA的正极输入端连接输入端VIN。As shown in FIG. 3 , other embodiments also provide an amplifier OPA, including the above-mentioned boosting circuit. The boost circuit is part of the amplifier OPA. The output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA. The positive input terminal of the amplifier OPA is connected to the input terminal VIN.
实施例2Example 2
如图4所示，降压电路包括：开关管、零温度系数电流电路10、电压电路20以及控制电路30。As shown in FIG. 4 , the step-down circuit includes: a switch tube, a zero temperature coefficient current circuit 10 , a voltage circuit 20 and a control circuit 30 .
开关管连接地电压VSS和输出端VOUT。零温度系数电流电路10、电压电路20和控制电路30依次连接。零温度系数电流电路10同时与地电压VSS连接。电压电路20同时与放大器OPA的内部电路40连接。电压电路20接收零温度系数电流电路10产生的零温度系数电流，同时提供一比较电压VB。控制电路30用于控制开关管的导通和关断。当地电压VSS小于比较电压VB时，输出端VOUT输出比较电压VB，当地电压VSS大于比较电压VB时，控制电路通过控制端VGN控制开关管导通，输出端VOUT输出地电压VSS，从而保证输出端VOUT输出的电压不小于地电压VSS。The switch tube is connected to the ground voltage VSS and the output terminal VOUT. The zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence. The zero temperature coefficient current circuit 10 is also connected to the ground voltage VSS. The voltage circuit 20 is simultaneously connected to an internal circuit 40 of the amplifier OPA. The voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10 and provides a comparison voltage VB at the same time. The control circuit 30 is used to control the turn-on and turn-off of the switch tube. When the local voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB. When the local voltage VSS is greater than the comparison voltage VB, the control circuit controls the conduction of the switch through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS, thereby ensuring the output terminal The output voltage of VOUT is not less than the ground voltage VSS.
如图4所示，开关管为NMOS管MN，NMOS管MN的源极连接地电压VSS，NMOS管MN的栅极连接控制端VGN并通过控制端VGN连接放大器OPA的内部电路40，NMOS管MN的漏极连接输出端VOUT。降压电路为放大器OPA的一部分，其中，放大器OPA的内部电路40由多个相连的NMOS管和PMOS管组成，内部电路40用于维持降压电路以及其他电路的运行。As shown in FIG. 4, the switch tube is an NMOS tube MN, the source of the NMOS tube MN is connected to the ground voltage VSS, the gate of the NMOS tube MN is connected to the control terminal VGN and is connected to the internal circuit 40 of the amplifier OPA through the control terminal VGN, and the NMOS tube MN The drain is connected to the output terminal VOUT. The step-down circuit is a part of the amplifier OPA, wherein the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS transistors and PMOS transistors, and the internal circuit 40 is used to maintain the operation of the step-down circuit and other circuits.
如图5和图4所示，零温度系数电流电路10包括放大器OPA0、NMOS管M0、电阻R0、第一电流镜和第二电流镜。放大器OPA0的正极输入端连接基准电压VREF，放大器OPA0的负极输入端通过电阻R0接地，放大器OPA0的负极输入端与NMOS管M0的源极连接，NMOS管M0的栅极连接放大器OPA0的输出端。NMOS管M0的漏极连接第一电流镜，第一电流镜连接第二电流镜，第二电流镜连接地电压VSS和控制电路30。As shown in FIG. 5 and FIG. 4 , the zero temperature coefficient current circuit 10 includes an amplifier OPA0 , an NMOS transistor M0 , a resistor R0 , a first current mirror and a second current mirror. The positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0, and the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0. The drain of the NMOS transistor M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit 30 .
其中，第一电流镜包括PMOS管MS0和PMOS管MS1，第二电流镜包括NMOS管MS2和NMOS管MS3。PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，PMOS管MS0的源极连接电源电压VDD。PMOS管MS1的源极连接电源电压VDD，PMOS管MS1的漏极连接NMOS管MS2的漏极和栅极以及NMOS管MS3的栅极。PMOS管MS2的源极接地，PMOS管MS3的漏极通过VS2端连接控制电路30，PMOS管MS3的源极接地。零温度系数电流等于基准电压VREF除以电阻R0的阻值。零温度系数电流通过VS2端流向电压电路20。Wherein, the first current mirror includes PMOS transistor MS0 and PMOS transistor MS1, and the second current mirror includes NMOS transistor MS2 and NMOS transistor MS3. The drain and gate of the PMOS transistor MS0 are connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor MS1 , and the source of the PMOS transistor MS0 is connected to the power supply voltage VDD. The source of the PMOS transistor MS1 is connected to the power supply voltage VDD, and the drain of the PMOS transistor MS1 is connected to the drain and gate of the NMOS transistor MS2 and the gate of the NMOS transistor MS3. The source of the PMOS transistor MS2 is grounded, the drain of the PMOS transistor MS3 is connected to the control circuit 30 through the VS2 terminal, and the source of the PMOS transistor MS3 is grounded. The zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance value of the resistor R0. The zero temperature coefficient current flows to the voltage circuit 20 through the VS2 terminal.
如图4所示，电压电路20包括NMOS管M3、NMOS管M4和电阻R1。NMOS管M3的源极连接电阻R1的一端且同时接收零温度系数电流，具体的，NMOS管M3的源极连接电阻R1的一端且通过VD2端连接控制电路30。电阻R1的另一端连接NMOS管 M4的源极，NMOS管M3的栅极连接输出端VOUT，NMOS管M4的栅极连接输入端电压VIN。NMOS管M3、NMOS管M4均采用NMOS管，实现了轨到轨输入，降低了电路成本。As shown in FIG. 4 , the voltage circuit 20 includes an NMOS transistor M3 , an NMOS transistor M4 and a resistor R1 . The source of the NMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient current. Specifically, the source of the NMOS transistor M3 is connected to one end of the resistor R1 and connected to the control circuit 30 through the VD2 terminal. The other end of the resistor R1 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the output terminal VOUT, and the gate of the NMOS transistor M4 is connected to the input voltage VIN. Both the NMOS tube M3 and the NMOS tube M4 use NMOS tubes, which realize rail-to-rail input and reduce circuit costs.
比较电压VB＝VIN-IM4*R1，其中，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。该零温度系数电流由基准电压VREF和电阻R0决定。即电阻R1上的电压主要受到基准电压VREF的影响，从而可实现精准降，避免了工艺影响，提高了精度。Comparison voltage VB=VIN-IM4*R1, wherein, VIN is the voltage input from the input terminal VIN, and IM4 is the current with zero temperature coefficient flowing through the resistor R1. The zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. That is, the voltage on the resistor R1 is mainly affected by the reference voltage VREF, so that precise drop can be achieved, the influence of the process is avoided, and the precision is improved.
如图4所示，控制电路30包括电流镜、电流源I1、PMOS管M5和PMOS管M6。电流镜与地电压VSS和电压电路20连接，在本实施例中，电流镜与地电压VSS之间连接有零温度系数电流电路10，电流镜通过VS2端与零温度系数电流电路10连接，电流镜通过VD2端与电压电路20连接。PMOS管M5的漏极连接栅极以及电流源I1的一端和电流镜，PMOS管M5的源极连接电流源I1的另一端并连接电源电压VDD。PMOS管M6的栅极连接PMOS管M5的栅极，PMOS管M6的源极连接电源电压VDD，PMOS管M6的漏极通过控制端VGN连接NMOS管MN的栅极。As shown in FIG. 4 , the control circuit 30 includes a current mirror, a current source I1 , a PMOS transistor M5 and a PMOS transistor M6 . The current mirror is connected to the ground voltage VSS and the voltage circuit 20. In this embodiment, a zero temperature coefficient current circuit 10 is connected between the current mirror and the ground voltage VSS, and the current mirror is connected to the zero temperature coefficient current circuit 10 through the VS2 terminal. The mirror is connected to the voltage circuit 20 through the VD2 terminal. The drain of the PMOS transistor M5 is connected to the gate, one end of the current source I1 and the current mirror, and the source of the PMOS transistor M5 is connected to the other end of the current source I1 and to the power supply voltage VDD. The gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M5, the source of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M6 is connected to the gate of the NMOS transistor MN through the control terminal VGN.
电流镜包括NMOS管M1和NMOS管M2。NMOS管M1的源极连接NMOS管M2的源极并连接地电压VSS，在本实施例中，NMOS管M1的源极与NMOS管M2的源极相连且与地电压VSS之间连接有零温度系数电流电路10，即NMOS管M1的源极和NMOS管M2的源极相连并通过VS2端连接NMOS管MS3的漏极。NMOS管M1的栅极连接NMOS管M2的栅极并形成VG2端。NMOS管M1的漏极连接PMOS管M5的漏极并形成VG5端。NMOS管M2的漏极通过VD2端连接电阻R1和NMOS管M3的源极。The current mirror includes NMOS transistor M1 and NMOS transistor M2. The source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS. In this embodiment, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS. In the coefficient current circuit 10, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the drain of the NMOS transistor MS3 through the VS2 terminal. The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 to form a VG2 terminal. The drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M5 to form a VG5 terminal. The drain of the NMOS transistor M2 is connected to the resistor R1 and the source of the NMOS transistor M3 through the VD2 terminal.
根据上述降压电路可知，当地电压VSS小于比较电压VB时，通过将电流源I1的电流设置成大于经过NMOS管M1的电流，此时VG5端处为高电压，PMOS管M6关断，此时输出端OUT输出比较电压VB。According to the above step-down circuit, it can be seen that when the local voltage VSS is lower than the comparison voltage VB, by setting the current of the current source I1 to be greater than the current passing through the NMOS transistor M1, the VG5 terminal is at a high voltage at this time, and the PMOS transistor M6 is turned off. At this time The output terminal OUT outputs a comparison voltage VB.
当地电压VSS大于电压VB时，NMOS管M2进入线性区，VS2端的电压和VG2端的电压的差值变大，此时经过NMOS管M1的电流大于电流源I1的电流，PMOS管M6导通从而使得VGN端为高电压，NMOS管MN导通，此时输出端OUT输出地电压VSS。When the local voltage VSS is greater than the voltage VB, the NMOS transistor M2 enters the linear region, and the difference between the voltage at the VS2 terminal and the voltage at the VG2 terminal becomes larger. At this time, the current passing through the NMOS transistor M1 is greater than the current of the current source I1, and the PMOS transistor M6 is turned on so that The VGN terminal is a high voltage, the NMOS transistor MN is turned on, and the output terminal OUT outputs the ground voltage VSS at this time.
如图6所示，其他实施例中还提供了一种放大器OPA，包括上述的降压电路。降压电路为放大器OPA的一部分。放大器OPA的输出端VOUT连接放大器OPA的负极输入端。放大器OPA的正极输入端连接输入端VIN。As shown in FIG. 6 , other embodiments also provide an amplifier OPA, including the above-mentioned step-down circuit. The step-down circuit is part of the amplifier OPA. The output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA. The positive input terminal of the amplifier OPA is connected to the input terminal VIN.
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非 想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling others skilled in the art to make and use various exemplary embodiments of the invention, as well as various Choose and change. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (20)

  1. 一种升压电路，其特征在于，包括：A booster circuit, characterized in that it comprises:
    开关管，连接电源电压VDD和输出端VOUT；The switch tube is connected to the power supply voltage VDD and the output terminal VOUT;
    电压电路，接收零温度系数电流，同时提供一比较电压VB；以及a voltage circuit, receiving a zero temperature coefficient current, and simultaneously providing a comparison voltage VB; and
    控制电路，连接于所述电源电压VDD与电压电路之间且同时与开关管连接，当电源电压VDD大于比较电压VB时，所述输出端VOUT输出比较电压VB，当电源电压VDD小于比较电压VB时，所述控制电路通过控制端VGP控制开关管导通，所述输出端VOUT输出电源电压VDD。The control circuit is connected between the power supply voltage VDD and the voltage circuit and is connected to the switch tube at the same time. When the power supply voltage VDD is greater than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB. When the power supply voltage VDD is less than the comparison voltage VB , the control circuit controls the switch tube to be turned on through the control terminal VGP, and the output terminal VOUT outputs the power supply voltage VDD.
  2. 如权利要求1所述的升压电路，其特征在于，所述开关管为PMOS管MP，所述PMOS管MP的源极连接电源电压VDD，所述PMOS管MP的栅极连接控制端VGP，所述PMOS管MP的漏极连接输出端VOUT。The boost circuit according to claim 1, wherein the switch tube is a PMOS tube MP, the source of the PMOS tube MP is connected to the power supply voltage VDD, the gate of the PMOS tube MP is connected to the control terminal VGP, The drain of the PMOS transistor MP is connected to the output terminal VOUT.
  3. 如权利要求1所述的升压电路，其特征在于，所述电压电路包括PMOS管M3、PMOS管M4和电阻R1，所述PMOS管M3的源极连接电阻R1的一端且同时接收零温度系数电流，所述电阻R1的另一端连接PMOS管M4的源极，所述PMOS管M3的栅极连接输出端VOUT，所述PMOS管M4的栅极连接输入端VIN。The boost circuit according to claim 1, wherein the voltage circuit comprises a PMOS transistor M3, a PMOS transistor M4 and a resistor R1, the source of the PMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient The other end of the resistor R1 is connected to the source of the PMOS transistor M4, the gate of the PMOS transistor M3 is connected to the output terminal VOUT, and the gate of the PMOS transistor M4 is connected to the input terminal VIN.
  4. 如权利要求3所述的升压电路，其特征在于，所述比较电压VB＝VIN+IM4*R1，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。The boost circuit according to claim 3, wherein the comparison voltage VB=VIN+IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
  5. 如权利要求1所述的升压电路，其特征在于，所述控制电路包括第一电流镜、电流源I1、NMOS管M5和NMOS管M6，所述第一电流镜与电源电压VDD和电压电路连接，所述NMOS管M5的漏极连接栅极以及电流源I1的一端和第一电流镜，所述NMOS管M5的源极连接电流源I1的另一端并接地，所述NMOS管M6的栅极连接NMOS管M5的栅极，所述NMOS管M6的源极接地，所述NMOS管M6的漏极连接控制端VGP。The boost circuit according to claim 1, wherein the control circuit comprises a first current mirror, a current source I1, an NMOS transistor M5 and an NMOS transistor M6, and the first current mirror is connected to the power supply voltage VDD and the voltage circuit connected, the drain of the NMOS transistor M5 is connected to the gate and one end of the current source I1 and the first current mirror, the source of the NMOS transistor M5 is connected to the other end of the current source I1 and grounded, and the gate of the NMOS transistor M6 The pole is connected to the gate of the NMOS transistor M5, the source of the NMOS transistor M6 is grounded, and the drain of the NMOS transistor M6 is connected to the control terminal VGP.
  6. 如权利要求5所述的升压电路，其特征在于，所述第一电流镜包括PMOS管M1和PMOS管M2，所述PMOS管M1的源极连接PMOS管M2的源极并连接电源电压VDD，所述PMOS管M1的栅极连接PMOS管M2的栅极，所述PMOS管M1的漏极连接NMOS管M5的漏极，所述NMOS管M2的漏极连接电压电路。The boost circuit according to claim 5, wherein the first current mirror includes a PMOS transistor M1 and a PMOS transistor M2, the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and connected to the power supply voltage VDD The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
  7. 如权利要求1所述的升压电路，其特征在于，所述升压电路还包括产生零温度系数电流的零温度系数电流电路，所述零温度系数电流电路连接于电源电压VDD和控制电路之间。The boosting circuit according to claim 1, wherein the boosting circuit further comprises a zero temperature coefficient current circuit generating a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the power supply voltage VDD and the control circuit between.
  8. 如权利要求7所述的升压电路，其特征在于，所述零温度系数电流电路包括放大 器OPA0、NMOS管M0、电流镜、电阻R0，所述放大器OPA0的正极输入端连接基准电压VREF，所述放大器OPA0的负极输入端通过电阻R0接地，所述放大器OPA0的负极输入端与NMOS管M0的源极连接，所述NMOS管M0的栅极连接放大器OPA0的输出端，所述NMOS管M0的漏极连接电流镜，所述电流镜连接电源电压VDD和控制电路。The boosting circuit according to claim 7, wherein the zero temperature coefficient current circuit comprises an amplifier OPA0, an NMOS transistor M0, a current mirror, and a resistor R0, and the positive input terminal of the amplifier OPA0 is connected to a reference voltage VREF, so The negative input end of the amplifier OPA0 is grounded through the resistor R0, the negative input end of the amplifier OPA0 is connected to the source of the NMOS transistor M0, the gate of the NMOS transistor M0 is connected to the output end of the amplifier OPA0, and the NMOS transistor M0 The drain is connected to a current mirror, and the current mirror is connected to the power supply voltage VDD and the control circuit.
  9. 如权利要求8所述的升压电路，其特征在于，所述电流镜包括PMOS管MS0和PMOS管MS1，所述PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，所述PMOS管MS0的源极连接PMOS管MS1的源极和电源电压VDD，所述PMOS管MS1的漏极连接控制电路。The boost circuit according to claim 8, wherein the current mirror comprises a PMOS transistor MS0 and a PMOS transistor MS1, the drain of the PMOS transistor MS0 is connected to the gate and is connected to the drain of the NMOS transistor M0 and the PMOS transistor M0. The gate of the transistor MS1, the source of the PMOS transistor MS0 is connected to the source of the PMOS transistor MS1 and the power supply voltage VDD, and the drain of the PMOS transistor MS1 is connected to the control circuit.
  10. 一种放大器，其特征在于，包括如权利要求1～9任一项所述的升压电路。An amplifier, characterized by comprising the boosting circuit according to any one of claims 1-9.
  11. 一种降压电路，其特征在于，包括：A step-down circuit, characterized in that, comprising:
    开关管，连接地电压VSS和输出端VOUT；The switch tube is connected to the ground voltage VSS and the output terminal VOUT;
    电压电路，接收零温度系数电流，同时提供一比较电压VB；以及a voltage circuit, receiving a zero temperature coefficient current, and simultaneously providing a comparison voltage VB; and
    控制电路，连接于所述地电压VSS与电压电路之间且同时与开关管连接；当地电压VSS小于比较电压VB时，所述输出端VOUT输出比较电压VB，当地电压VSS大于比较电压VB时，所述控制电路通过控制端VGN控制开关管导通，所述输出端VOUT输出地电压VSS。The control circuit is connected between the ground voltage VSS and the voltage circuit and is connected to the switch tube at the same time; when the ground voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB, and when the ground voltage VSS is greater than the comparison voltage VB, The control circuit controls the conduction of the switch tube through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS.
  12. 如权利要求11所述的降压电路，其特征在于，所述开关管为NMOS管MN，所述NMOS管MN的源极连接地电压VSS，所述NMOS管MN的栅极连接控制端VGN，所述NMOS管MN的漏极连接输出端VOUT。The step-down circuit according to claim 11, wherein the switch tube is an NMOS tube MN, the source of the NMOS tube MN is connected to the ground voltage VSS, the gate of the NMOS tube MN is connected to the control terminal VGN, The drain of the NMOS transistor MN is connected to the output terminal VOUT.
  13. 如权利要求11所述的降压电路，其特征在于，所述电压电路包括NMOS管M3、NMOS管M4和电阻R1，所述NMOS管M3的源极连接电阻R1的一端且同时接收零温度系数电流，所述电阻R1的另一端连接NMOS管M4的源极，所述NMOS管M3的栅极连接输出端VOUT，所述NMOS管M4的栅极连接输入端VIN。The step-down circuit according to claim 11, wherein the voltage circuit comprises an NMOS transistor M3, an NMOS transistor M4, and a resistor R1, and the source of the NMOS transistor M3 is connected to one end of the resistor R1 and simultaneously receives a zero temperature coefficient The other end of the resistor R1 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the output terminal VOUT, and the gate of the NMOS transistor M4 is connected to the input terminal VIN.
  14. 如权利要求13所述的降压电路，其特征在于，所述比较电压VB＝VIN-IM4*R1，其中，VIN为输入端VIN输入的电压，IM4为流过电阻R1的零温度系数电流。The step-down circuit according to claim 13, wherein the comparison voltage VB=VIN-IM4*R1, wherein VIN is the voltage input from the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
  15. 如权利要求11所述的降压电路，其特征在于，所述控制电路包括电流镜、电流源I1、PMOS管M5和PMOS管M6，所述电流镜与地电压VSS和电压电路连接，所述PMOS管M5的漏极连接栅极以及电流源I1的一端和电流镜，所述PMOS管M5的源极连接电流源I1的另一端并连接电源电压VDD，所述PMOS管M6的栅极连接PMOS管M5的栅极，所述PMOS管M6的源极连接电源电压VDD，所述PMOS管M6的漏极连 接控制端VGN。The step-down circuit according to claim 11, wherein the control circuit comprises a current mirror, a current source I1, a PMOS transistor M5, and a PMOS transistor M6, the current mirror is connected to the ground voltage VSS and the voltage circuit, and the The drain of the PMOS transistor M5 is connected to the gate and one end of the current source I1 and the current mirror, the source of the PMOS transistor M5 is connected to the other end of the current source I1 and to the power supply voltage VDD, and the gate of the PMOS transistor M6 is connected to the PMOS The gate of the transistor M5, the source of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M6 is connected to the control terminal VGN.
  16. 如权利要求15所述的降压电路，其特征在于，所述电流镜包括NMOS管M1和NMOS管M2，所述NMOS管M1的源极连接NMOS管M2的源极并连接地电压VSS，所述NMOS管M1的栅极连接NMOS管M2的栅极，所述NMOS管M1的漏极连接PMOS管M5的漏极，所述NMOS管M2的漏极连接电压电路。The step-down circuit according to claim 15, wherein the current mirror comprises an NMOS transistor M1 and an NMOS transistor M2, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and connected to the ground voltage VSS, so The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2, the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M5, and the drain of the NMOS transistor M2 is connected to the voltage circuit.
  17. 如权利要求11所述的降压电路，其特征在于，所述降压电路还包括产生零温度系数电流的零温度系数电流电路，所述零温度系数电流电路连接于地电压VSS和控制电路之间。The step-down circuit according to claim 11, wherein the step-down circuit further comprises a zero-temperature-coefficient current circuit generating a zero-temperature-coefficient current, and the zero-temperature-coefficient current circuit is connected between the ground voltage VSS and the control circuit between.
  18. 如权利要求17所述的降压电路，其特征在于，所述零温度系数电流电路包括放大器OPA0、NMOS管M0、电阻R0、第一电流镜和第二电流镜，所述放大器OPA0的正极输入端连接基准电压VREF，所述放大器OPA0的负极输入端通过电阻R0接地，所述放大器OPA0的负极输入端与NMOS管M0的源极连接，所述NMOS管M0的栅极连接放大器OPA0的输出端，所述NMOS管M0的漏极连接第一电流镜，所述第一电流镜连接第二电流镜，所述第二电流镜连接地电压VSS和控制电路。The step-down circuit according to claim 17, wherein the zero temperature coefficient current circuit comprises an amplifier OPA0, an NMOS transistor M0, a resistor R0, a first current mirror and a second current mirror, and the positive input of the amplifier OPA0 connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS transistor M0, and the gate of the NMOS transistor M0 is connected to the output terminal of the amplifier OPA0 , the drain of the NMOS transistor M0 is connected to a first current mirror, the first current mirror is connected to a second current mirror, and the second current mirror is connected to a ground voltage VSS and a control circuit.
  19. 如权利要求18所述的降压电路，其特征在于，所述第一电流镜包括PMOS管MS0和PMOS管MS1，所述第二电流镜包括NMOS管MS2和NMOS管MS3，所述PMOS管MS0的漏极和栅极连接且连接NMOS管M0的漏极以及PMOS管MS1的栅极，所述PMOS管MS0的源极连接电源电压VDD，所述PMOS管MS1的源极连接电源电压VDD，所述PMOS管MS1的漏极连接NMOS管MS2的漏极和栅极以及NMOS管MS3的栅极，所述PMOS管MS2的源极接地，所述PMOS管MS3的漏极连接控制电路，所述PMOS管MS3的源极接地。The step-down circuit according to claim 18, wherein the first current mirror includes a PMOS transistor MS0 and a PMOS transistor MS1, the second current mirror includes an NMOS transistor MS2 and an NMOS transistor MS3, and the PMOS transistor MS0 The drain and gate of the NMOS transistor M0 and the gate of the PMOS transistor MS1 are connected, the source of the PMOS transistor MS0 is connected to the power supply voltage VDD, and the source of the PMOS transistor MS1 is connected to the power supply voltage VDD. The drain of the PMOS transistor MS1 is connected to the drain and gate of the NMOS transistor MS2 and the gate of the NMOS transistor MS3, the source of the PMOS transistor MS2 is grounded, the drain of the PMOS transistor MS3 is connected to the control circuit, and the PMOS The source of tube MS3 is grounded.
  20. 一种放大器，其特征在于，包括如权利要求11～19任一项所述的降压电路。An amplifier, characterized by comprising the step-down circuit according to any one of claims 11-19.
PCT/CN2022/139331 2021-12-16 2022-12-15 Booster circuit, buck circuit and amplifier WO2023109908A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202111546682.2A CN114221541A (en) 2021-12-16 2021-12-16 Voltage reduction circuit and amplifier
CN202111546682.2 2021-12-16
CN202111546653.6 2021-12-16
CN202111546653.6A CN114221540B (en) 2021-12-16 2021-12-16 Boost circuit and amplifier

Publications (1)

Publication Number Publication Date
WO2023109908A1 true WO2023109908A1 (en) 2023-06-22

Family

ID=86774880

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/139331 WO2023109908A1 (en) 2021-12-16 2022-12-15 Booster circuit, buck circuit and amplifier

Country Status (1)

Country Link
WO (1) WO2023109908A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080224676A1 (en) * 2004-01-21 2008-09-18 Ryotaro Kudo Voltage Clamp Circuit, a Switching Power Supply Device, a Semiconductor Integrated Circuit Device, and a Voltage Level Conversion Circuit
TW201336226A (en) * 2012-02-24 2013-09-01 Novatek Microelectronics Corp Multi power domain operational amplifier and voltage generator using the same
CN105186865A (en) * 2015-09-17 2015-12-23 成都米戈科技有限公司 Low power consumption boost circuit for electronic product
CN109392218A (en) * 2017-08-09 2019-02-26 富士电机株式会社 Dimming device and power-converting device
CN110427091A (en) * 2019-07-19 2019-11-08 昆山龙腾光电有限公司 Power supply circuit and display device
US20200112251A1 (en) * 2018-10-09 2020-04-09 Stmicroelectronics (Rousset) Sas Control of a power stage of a switched-mode power supply
CN114221541A (en) * 2021-12-16 2022-03-22 思瑞浦微电子科技(上海)有限责任公司 Voltage reduction circuit and amplifier
CN114221540A (en) * 2021-12-16 2022-03-22 思瑞浦微电子科技(上海)有限责任公司 Boost circuit and amplifier

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080224676A1 (en) * 2004-01-21 2008-09-18 Ryotaro Kudo Voltage Clamp Circuit, a Switching Power Supply Device, a Semiconductor Integrated Circuit Device, and a Voltage Level Conversion Circuit
TW201336226A (en) * 2012-02-24 2013-09-01 Novatek Microelectronics Corp Multi power domain operational amplifier and voltage generator using the same
CN105186865A (en) * 2015-09-17 2015-12-23 成都米戈科技有限公司 Low power consumption boost circuit for electronic product
CN109392218A (en) * 2017-08-09 2019-02-26 富士电机株式会社 Dimming device and power-converting device
US20200112251A1 (en) * 2018-10-09 2020-04-09 Stmicroelectronics (Rousset) Sas Control of a power stage of a switched-mode power supply
CN110427091A (en) * 2019-07-19 2019-11-08 昆山龙腾光电有限公司 Power supply circuit and display device
CN114221541A (en) * 2021-12-16 2022-03-22 思瑞浦微电子科技(上海)有限责任公司 Voltage reduction circuit and amplifier
CN114221540A (en) * 2021-12-16 2022-03-22 思瑞浦微电子科技(上海)有限责任公司 Boost circuit and amplifier

Similar Documents

Publication Publication Date Title
TWI447552B (en) Voltage regulator with adaptive miller compensation
TWI437403B (en) Voltage regulator
CN114221540B (en) Boost circuit and amplifier
WO2019104467A1 (en) Voltage regulator and power supply
JP6728335B2 (en) Multistage amplifier with cascode stage and DC bias regulator
US20150280558A1 (en) Integrated current replicator and method of operating the same
US8207787B2 (en) Low-voltage operation constant-voltage circuit
JP2018527821A (en) DC bias regulator for cascode amplifier
TWI794345B (en) Backflow prevention circuit and power supply circuit
CN114221541A (en) Voltage reduction circuit and amplifier
WO2023109908A1 (en) Booster circuit, buck circuit and amplifier
JP2005018783A (en) Current source for generating constant reference current
CN108345336B (en) Energy gap reference circuit
JP2012064009A (en) Voltage output circuit
US20050013029A1 (en) Voice coil motor power amplifier
JP2006079517A (en) Constant voltage power supply circuit
JP4479309B2 (en) Reference current generation circuit and reference voltage generation circuit
TW201809947A (en) Bandgap reference circuit
US10211839B2 (en) System and method of automatic power control system and bias current control circuit
US10148236B1 (en) Output stage of operational amplifier and method in the operational amplifier
JP2015022546A (en) Constant-current constant-voltage circuit
TWI827090B (en) Driving circuit and circuit system thereof
US11709516B2 (en) Power supply circuit
JP6837894B2 (en) Step-down circuit and semiconductor integrated circuit
JP7494556B2 (en) Stabilized Power Supply Circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22906653

Country of ref document: EP

Kind code of ref document: A1