CN107727925B - High-precision wide-range peak current sampling circuit - Google Patents
High-precision wide-range peak current sampling circuit Download PDFInfo
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- CN107727925B CN107727925B CN201711101616.8A CN201711101616A CN107727925B CN 107727925 B CN107727925 B CN 107727925B CN 201711101616 A CN201711101616 A CN 201711101616A CN 107727925 B CN107727925 B CN 107727925B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H02M1/0009—Devices or circuits for detecting current in a converter
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Abstract
A high-precision wide-range peak current sampling circuit is applied to a double-N-tube synchronous rectification type Buck converter and belongs to the technical field of power electronics. The circuit comprises a SenseFET sampling tube MNs, a pre-voltage reduction circuit, a clamping operational amplifier OP, an NMOS adjusting tube M1 and a sampling resistor R1, wherein the SenseFET sampling tube MNs clamps the source end potential Vx to a power switch node SW point through the clamping operational amplifier OP and the adjusting tube M1; the pre-voltage reduction circuit realizes the pre-voltage reduction function, and the voltage reduction size is adjustable through extra feedback control, so that the output of the pre-voltage reduction circuit is stabilized in the input range of the clamping operational amplifier, normal current sampling can be realized in a power supply which changes in a large range, and the sampling current is converted into sampling voltage through the sampling resistor R1. The invention can realize the peak current sampling with wide range and high precision, and simultaneously, the grid input operational amplifier structure improves the lower limit of the peak current sampling, expands the sampling current range and ensures the high current sampling precision under the wide voltage input range.
Description
Technical Field
The invention belongs to the technical field of power electronics, and relates to a high-precision wide-range peak current sampling circuit for a double-N-tube synchronous rectification type Buck converter.
Background
In the peak current mode Buck converter, the sampling precision of the peak current is high, a better loop control effect can be achieved, and the requirement on the sampling precision of inductive current information is higher and higher along with sampling of a plurality of new technologies such as floating gate voltage, floating gate width, transient lifting technology and the like.
The key of high-precision SenseFET current sampling is the voltage clamping precision of the source end of a SenseFET sampling tube, the higher the clamping precision is, the more accurate the mirror proportion of the SenseFET sampling tube and a power tube is, and the obtained sampling current is closer to the magnitude of inductive current with the same size proportion.
The input range of a general double-N-tube Buck converter is wide, and how to realize the clamping of a SenseFET sampling tube source end in the wide input range becomes one of the main problems for limiting the sampling range and the precision. The input range of the gate input clamping operational amplifier is generally narrow, and the requirement corresponding to the input range of the wide-range Buck converter cannot be met. In a general common-gate amplifier circuit, as shown in fig. 1, the source-end clamping of a sampling tube MNs is performed by a common-gate clamping op-amp, but the common-gate clamping op-amp draws current from an input end, that is, draws additional Ib current from Isense to supply to the common-gate clamping op-amp as its bias current, so that the current actually flowing through a sampling resistor is reduced by Ib compared with Isense, thereby reducing the sampling precision, and the sample current cannot even provide the bias current required by the common-gate amplifier stage at low inductive current, thereby causing the clamping op-amp to fail.
Disclosure of Invention
The problems to be solved by the invention are as follows: firstly, under a wide input range, the clamping effect of the source end of the traditional SenseFET sampling tube is deteriorated, and the sampling precision is reduced; secondly, when the load is light, the traditional common-gate input stage clamping operational amplifier fails, so that the light-load sampling effect is limited. Aiming at the problems, the invention provides a high-precision wide-range peak current sampling circuit which is applied to a double-N-tube Buck converter, the sampling circuit can be suitable for a wide input voltage range by utilizing a SenseFET sampling tube, a pre-voltage-reducing circuit and a clamping operational amplifier, and the current sampling range and precision are improved by adopting a gate input operational amplifier structure, so that the wide-range high-precision peak current sampling is realized.
The technical scheme of the invention is as follows:
a high-precision wide-range peak current sampling circuit applied to a double-N tube synchronous rectification type Buck converter comprises SenseFET sampling tubes MNs, a pre-step-down circuit, a clamping operational amplifier OP, an NMOS adjusting tube M1 and a sampling resistor R1,
the grid electrode of a SenseFET sampling tube MNs is connected with the grid electrode of the upper-end power tube of the double-N tube synchronous rectification type Buck converter, the drain electrode of the SenseFET sampling tube MNs is connected with a power supply PVDD, and the source electrode of the SenseFET sampling tube MNs is connected with the positive input end of the pre-voltage reduction circuit and the drain electrode of the NMOS adjusting tube M1;
the negative input end of the pre-step-down circuit is connected with a switch node SW of the double-N-tube synchronous rectification type Buck converter, and the positive and negative output ends of the pre-step-down circuit are respectively connected with the positive and negative input ends of a clamping operational amplifier OP;
the grid electrode of the adjusting tube M1 is connected with the output end of the clamping operational amplifier OP, and the source electrode of the adjusting tube M1 is used as the output end of the sampling circuit and is grounded after passing through the sampling resistor R1;
the pre-reducing circuit comprises a pre-reducing clamping operational amplifier OP _ P, a first input NMOS tube M2, a second input NMOS tube M3, a first current mirror NMOS tube M4 and a second current mirror NMOS tube M5,
the grid of the first input NMOS tube M2 is used as the negative input end of the pre-step-down circuit, the drain of the first input NMOS tube M2 is connected with the power supply PVDD, the source of the first input NMOS tube M2 is connected with the positive input end of the pre-step-down clamping operational amplifier OP _ P and the drain of the first current mirror NMOS tube M4 and is used as the negative output end of the pre-step-down circuit;
the grid electrode of the second input NMOS tube M3 is used as the positive input end of the pre-step-down circuit, the drain electrode of the second input NMOS tube M3 is connected with the power supply PVDD, and the source electrode of the second input NMOS tube M5 is connected with the drain electrode of the second current mirror NMOS tube M5 and is used as the positive output end of the pre-step-down circuit;
the negative input end of the pre-buck clamping operational amplifier OP _ P is connected with a fixed potential, the output end of the pre-buck clamping operational amplifier OP _ P is connected with the grids of the first current mirror NMOS transistor M4 and the second current mirror NMOS transistor M5, and the sources of the first current mirror NMOS transistor M4 and the second current mirror NMOS transistor M5 are grounded.
Specifically, the clamping operational amplifier OP and the pre-buck clamping operational amplifier OP _ P are clamping operational amplifiers with the same structure, and include a first PMOS transistor M6, a second PMOS transistor M7, a third PMOS transistor M10, a first NMOS transistor M8, a second NMOS transistor M9, a third NMOS transistor M11, a fourth NMOS transistor M12, a fifth NMOS transistor M13, a capacitor C1, and a current source,
the grid electrode of the first NMOS tube M8 is used as the negative input end of the clamping operational amplifier, the drain electrode of the first NMOS tube M6 is connected with the grid electrode and the drain electrode of the first PMOS tube M6 and the grid electrode of the second PMOS tube M7, and the source electrode of the first NMOS tube M8 is connected with the source electrode of the second NMOS tube M9 and the drain electrode of the fourth NMOS tube M12;
the grid electrode of the second NMOS tube M9 is used as the positive input end of the clamping operational amplifier, and the drain electrode of the second NMOS tube M9 is connected with the drain electrode of the second PMOS tube M7 and the grid electrode of the third PMOS tube M10;
the negative electrode of the current source is connected with a power supply voltage, and the positive electrode of the current source is connected with the grid electrode and the drain electrode of the third NMOS tube M11, the grid electrode of the fourth NMOS tube M12 and the grid electrode of the fifth NMOS tube M13;
the drain electrode of the third PMOS tube M10 is connected with the drain electrode of the fifth NMOS tube M13 and is used as the output end of the clamping operational amplifier, and the capacitor C1 is connected between the grid electrode and the drain electrode of the third PMOS tube M10;
the sources of the first PMOS transistor M6, the second PMOS transistor M7 and the third PMOS transistor M10 are connected with the power voltage, and the sources of the third NMOS transistor M11, the fourth NMOS transistor M12 and the fifth NMOS transistor M13 are grounded.
The invention has the beneficial effects that: the peak current sampling circuit provided by the invention clamps the voltage of the source end of the SenseFET sampling tube and the SW point of the power switch node, thereby obtaining the sampling current which is proportional to the current flowing through the upper tube, expanding the input voltage range and the load current range of the current sampling circuit and simultaneously ensuring the current sampling precision.
Drawings
Fig. 1 is a schematic diagram of a conventional common-gate clamp SenseFET current sampling structure.
Fig. 2 is a schematic diagram of an overall structure of a high-precision wide-range peak current sampling circuit provided by the present invention.
Fig. 3 is a schematic structural diagram of the pre-step-down circuit P _ LD and the clamping OP in the present invention.
FIG. 4 is a circuit diagram of one implementation of the clamping operational amplifier in the embodiment.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
Fig. 2 shows a high-precision wide-range peak current sampling circuit applied to a double-N-tube synchronous rectification Buck converter, which includes a SenseFET sampling tube MNs, a pre-step-down circuit P _ LD, a clamping operational amplifier OP, an NMOS adjusting tube M1, and a sampling resistor R1, where the sampling tube MNs clamps a source terminal potential Vx to a power switch node SW point through the clamping operational amplifier OP and the adjusting tube M1, so that the operating state of the MNs is completely the same as that of an upper-end power tube, and the magnitude of a current flowing through the sampling tube is equal to a multiple of a ratio of a current flowing through an upper tube, where the ratio is a width-length ratio of the MNs to the upper-end power tube. The grid electrode of the sampling tube MNs is connected with the grid end of the power tube at the upper end of the Buck conversion circuit, the drain end of the sampling tube MNs is connected with the power supply PVDD, and the source end Vx point is connected with the positive input end of the pre-step-down circuit P _ LD and the drain end of the adjusting tube M1; the negative input end of the pre-step-down circuit P _ LD is connected with a switch node SW point of the Buck converter, the positive output end and the negative output end of the pre-step-down circuit are respectively connected with the positive input and the negative input of a clamping operational amplifier OP, so that the error between the Vx point and the SW point is amplified, the output end Vy of the clamping operational amplifier OP is connected with the grid end of an adjusting tube M1, the size of sampling current is adjusted by adjusting the grid end of the adjusting tube M1, and the specific method for adjusting the sampling current: a source follower structure for inputting Vy to outputting Vcs is formed by a sampling tube MNs, an adjusting tube M1 and a sampling resistor R1, so that the change of Vy can change the voltage of Vcs, and the size of sampling current Isense is Vcs/R1, so that the size of sampling current is changed; the source end of the adjusting tube M1 is connected with the sampling resistor R1, so that the sampling current is converted into sampling voltage Vcs through the sampling resistor R1.
As shown in fig. 3, which is a schematic structural diagram of the pre-buck circuit P _ LD and the clamp OP in the present invention, the input of the pre-buck circuit P _ LD is stepped down by the common-drain follower of the first input NMOS transistor M2 and the second input NMOS transistor M3, which is mainly because the power supply voltage range is wide, but the input range of the high-precision clamp OP is fixed, so the input needs to be processed first. The drain follower is different from a general follower, mainly because the voltage drop of the general follower is fixed, and the general follower cannot adapt to a wide range of input voltage. The processing here is to adjust the bias current of the follower through the pre-step-down clamping operational amplifier OP _ P, so as to dynamically change the voltage drop, and because of the symmetry of the first current mirror NMOS transistor M4 and the second current mirror NMOS transistor M5, the voltage drop of the first input NMOS transistor M2 and the second input NMOS transistor M3 is the same under the same bias current, and thus only the Vd and Ve need to be clamped with high precision.
The source end Vx and the SW point of the SenseFET sampling tube are subjected to voltage reduction through the drain electrode follower in the pre-voltage reduction circuit P _ LD, meanwhile, the gain close to 1 time is ensured, and the pre-voltage reduction size is fixed in the input range of the high-precision clamping operational amplifier OP by adjusting the bias current of the drain electrode follower.
The pre-step-down circuit P _ LD includes a first input NMOS transistor M2 and a second input NMOS transistor M3 constituting an input NMOS pair transistor, a first current mirror NMOS transistor M4 and a second current mirror NMOS transistor M5 constituting a bias current mirror, and a pre-step-down clamp operational amplifier OP _ P. The gate end of the first input NMOS transistor M2 is the negative input end of the pre-step-down circuit P _ LD, the drain end of the first input NMOS transistor M2 is connected to the power supply PVDD, and the source end of the first input NMOS transistor M2 is connected to the positive input end of the pre-step-down clamping operational amplifier OP _ P and the drain end of the first current mirror NMOS transistor M4 to serve as the negative output end Vd point of the pre-step-down circuit P _ LD; the negative input end of the pre-step-down clamping operational amplifier OP _ P is connected with a fixed potential, and the output end of the pre-step-down clamping operational amplifier OP _ P is connected with the gate end of the first current mirror NMOS tube M4 and the gate end of the second current mirror NMOS tube M5, so that Vd point clamping is realized, wherein the fixed potential only needs to be within the common-mode input range of the clamping operational amplifier structure, and the specific size is determined by the actually adopted clamping operational amplifier structure and process; the gate end of the second input NMOS transistor M3 is the positive input end of the pre-step-down current P _ LD, the drain end of the second input NMOS transistor M3 is connected to the power supply PVDD, and the source end of the second input NMOS transistor M5 is connected to the drain end of the second input NMOS transistor M5 as the positive output end Ve point of the pre-step-down circuit P _ LD. Since the second current mirror NMOS transistor M5 is a mirror image of the first current mirror NMOS transistor M4, when Vd is clamped to Vb, the voltage difference between Ve and Vx is the same as the voltage difference between SW and Vd, thereby realizing the pre-step-down function. The pre-step-down circuit can work under different power input PVDD so that the clamping operational amplifier OP works under a stable direct current level and the performance of the clamping operational amplifier OP is guaranteed.
Fig. 4 is a circuit diagram for implementing the clamping operational amplifier in this embodiment, and it should be noted that there are various specific implementations of the clamping operational amplifier OP and the pre-buck clamping operational amplifier OP _ P, the clamping operational amplifier OP and the pre-buck clamping operational amplifier OP _ P may be clamping operational amplifiers with different structures, or may be in the same form, fig. 4 is only an implementation form, but no matter how the pre-buck clamping operational amplifier OP _ P and the clamping operational amplifier OP are designed, the invention should fall within the protection scope of the present invention.
The clamping operational amplifier OP and the pre-buck clamping operational amplifier OP _ P in the embodiment are clamping operational amplifiers with the same structure, and include a first PMOS transistor M6, a second PMOS transistor M7, a third PMOS transistor M10, a first NMOS transistor M8, a second NMOS transistor M9, a third NMOS transistor M11, a fourth NMOS transistor M12, a fifth NMOS transistor M13, a capacitor C1 and a current source, wherein a gate of the first NMOS transistor M8 is used as a negative input terminal of the clamping operational amplifier, a drain of the first NMOS transistor M6 is connected to a gate and a drain of the first PMOS transistor M6 and a gate of the second PMOS transistor M7, and a source of the first NMOS transistor M9 is connected to a source of the second NMOS transistor M9 and a drain of the fourth NMOS transistor M12; the grid electrode of the second NMOS tube M9 is used as the positive input end of the clamping operational amplifier, and the drain electrode of the second NMOS tube M9 is connected with the drain electrode of the second PMOS tube M7 and the grid electrode of the third PMOS tube M10; the negative electrode of the current source is connected with a power supply voltage, and the positive electrode of the current source is connected with the grid electrode and the drain electrode of the third NMOS tube M11, the grid electrode of the fourth NMOS tube M12 and the grid electrode of the fifth NMOS tube M13; the drain electrode of the third PMOS tube M10 is connected with the drain electrode of the fifth NMOS tube M13 and is used as the output end of the clamping operational amplifier, and the capacitor C1 is connected between the grid electrode and the drain electrode of the third PMOS tube M10; the sources of the first PMOS transistor M6, the second PMOS transistor M7 and the third PMOS transistor M10 are connected with the power voltage, and the sources of the third NMOS transistor M11, the fourth NMOS transistor M12 and the fifth NMOS transistor M13 are grounded.
The operation mode of the pre-step-down clamping operational amplifier OP _ P is that the Vd point of the positive input end of the pre-step-down clamping operational amplifier is compared with a fixed voltage Vb of the negative input end of the pre-step-down clamping operational amplifier to amplify so as to change the grid voltages of the first current mirror NMOS tube M4 and the second current mirror NMOS tube M5, thereby changing the bias currents Ids2 and Ids3 and further completing the clamping of the Vd point. Thus, when sampling is carried out, the SW potential changes but the Vd point keeps unchanged, the difference value of the Vd and Ve voltages is amplified through the clamping operational amplifier OP and then the Vx point voltage is regulated through the regulating tube M1, so that the Vx point voltage is equal to the SW point voltage, and current sampling is finished.
The invention can meet the requirement of high-precision peak current sampling in a wide input range, can normally complete the voltage clamping function no matter the power input voltage PVDD is so large as to realize current sampling due to the design of the pre-voltage reduction circuit, and expands the lower limit of the sampling current and ensures the sampling precision due to the adoption of the gate input operational amplifier clamping.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (2)
1. A high-precision wide-range peak current sampling circuit is characterized in that the circuit is applied to a double-N tube synchronous rectification type Buck converter and comprises SenseFET sampling tubes (MNs), a pre-voltage-reducing circuit, a clamping operational amplifier (OP), an NMOS adjusting tube (M1) and a sampling resistor (R1),
the grid electrode of a SenseFET sampling tube (MNs) is connected with the grid electrode of an upper end power tube of the double-N tube synchronous rectification type Buck converter, the drain electrode of the SenseFET sampling tube is connected with a power supply (PVDD), and the source electrode of the SenseFET sampling tube is connected with the positive input end of the pre-voltage reduction circuit and the drain electrode of the NMOS adjusting tube (M1);
the negative input end of the pre-step-down circuit is connected with a switch node (SW) of the double-N-tube synchronous rectification type Buck converter, and the positive and negative output ends of the pre-step-down circuit are respectively connected with the positive and negative input ends of a clamping operational amplifier (OP);
the grid electrode of the adjusting tube (M1) is connected with the output end of the clamping operational amplifier (OP), and the source electrode of the adjusting tube is used as the output end of the sampling circuit and is grounded after passing through the sampling resistor (R1);
the pre-buck circuit comprises a pre-buck clamping operational amplifier (OP _ P), a first input NMOS tube (M2), a second input NMOS tube (M3), a first current mirror NMOS tube (M4) and a second current mirror NMOS tube (M5),
the grid electrode of the first input NMOS tube (M2) is used as the negative input end of the pre-step-down circuit, the drain electrode of the first input NMOS tube is connected with the power supply (PVDD), and the source electrode of the first input NMOS tube is connected with the positive input end of the pre-step-down clamping operational amplifier (OP _ P) and the drain electrode of the first current mirror NMOS tube (M4) and is used as the negative output end of the pre-step-down circuit;
the grid electrode of a second input NMOS tube (M3) is used as a positive input end of the pre-step-down circuit, the drain electrode of the second input NMOS tube is connected with a power supply (PVDD), and the source electrode of the second input NMOS tube is connected with the drain electrode of a second current mirror NMOS tube (M5) and is used as a positive output end of the pre-step-down circuit;
the negative input end of the pre-buck clamping operational amplifier (OP _ P) is connected with a fixed potential, the output end of the pre-buck clamping operational amplifier is connected with the grids of the first current mirror NMOS tube (M4) and the second current mirror NMOS tube (M5), and the sources of the first current mirror NMOS tube (M4) and the second current mirror NMOS tube (M5) are grounded.
2. The high-precision wide-range peak current sampling circuit according to claim 1, wherein the clamp operational amplifier (OP) and the pre-buck clamp operational amplifier (OP _ P) are clamp operational amplifiers with the same structure, and comprise a first PMOS transistor (M6), a second PMOS transistor (M7), a third PMOS transistor (M10), a first NMOS transistor (M8), a second NMOS transistor (M9), a third NMOS transistor (M11), a fourth NMOS transistor (M12), a fifth NMOS transistor (M13), a capacitor (C1), and a current source,
the grid electrode of the first NMOS tube (M8) is used as the negative input end of the clamping operational amplifier, the drain electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube (M6) and the grid electrode of the second PMOS tube (M7), and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube (M9) and the drain electrode of the fourth NMOS tube (M12);
the grid electrode of the second NMOS tube (M9) is used as the positive input end of the clamping operational amplifier, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube (M7) and the grid electrode of the third PMOS tube (M10);
the negative pole of the current source is connected with a power supply voltage, and the positive pole of the current source is connected with the grid electrode and the drain electrode of the third NMOS tube (M11), the grid electrode of the fourth NMOS tube (M12) and the grid electrode of the fifth NMOS tube (M13);
the drain electrode of the third PMOS tube (M10) is connected with the drain electrode of the fifth NMOS tube (M13) and is used as the output end of the clamping operational amplifier, and the capacitor (C1) is connected between the grid electrode and the drain electrode of the third PMOS tube (M10);
the sources of the first PMOS tube (M6), the second PMOS tube (M7) and the third PMOS tube (M10) are connected with the power voltage, and the sources of the third NMOS tube (M11), the fourth NMOS tube (M12) and the fifth NMOS tube (M13) are grounded.
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