CN114220376A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN114220376A CN114220376A CN202111641199.2A CN202111641199A CN114220376A CN 114220376 A CN114220376 A CN 114220376A CN 202111641199 A CN202111641199 A CN 202111641199A CN 114220376 A CN114220376 A CN 114220376A
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- 239000010409 thin film Substances 0.000 claims description 300
- 239000003990 capacitor Substances 0.000 claims description 32
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- 238000005516 engineering process Methods 0.000 description 6
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- 238000012423 maintenance Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The application relates to a GOA circuit and a display panel; the circuit comprises a pull-up module, a pull-up control module, a pull-down maintaining module, an electricity storage module, a first pull-down module and a second pull-down module; the first end of the pull-up module is respectively connected with the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the power storage module, and the second end of the pull-up module is respectively connected with the second end of the power storage module and the first end of the first pull-down module; the second end of the pull-down maintaining module is connected with the second end of the first pull-down module, the third end of the pull-down maintaining module is connected with the first end of the second pull-down module, and the fourth end of the pull-down maintaining module is connected with the second end of the second pull-down module; the third end of second pull-down module connects the first end of pull-up control module, and the problem that the direct current passageway of high low level and cause the influence to circuit stability can be avoided producing at specific operating time to this application GOA circuit.
Description
Technical Field
The present application relates to a display driving technology field, and in particular, to a GOA circuit and a display panel.
Background
With the continuous development of display technology, the performance of display panels is also gradually improved, and the performance such as refresh rate, resolution, service life and the like of the display panels is continuously increased. Among them, the GOA (Gate on Array) circuit in the display panel has great advantages in cost and functionality compared with the COF Gate technology (Chip on film Gate), and thus is widely used. In order to achieve the accuracy of turning on the pixel by the gate scan signal, the GOA circuit of the conventional technology generally introduces an inverter to achieve the stability of the pull-down maintaining module in the non-signal output stage. However, the inverters in the conventional technology have a dc channel with high and low levels during a specific operation time, which may affect the stability of the GOA circuit.
Disclosure of Invention
Based on this, it is necessary to provide a GOA circuit and a display panel to solve the problem that the types of the conventional display devices are still not abundant enough to satisfy more usage scenarios.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a GOA circuit, which includes a pull-up module, a pull-up control module, a pull-down maintaining module, a power storage module, a first pull-down module, and a second pull-down module;
the first end of the pull-up module is respectively connected with the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the power storage module, and the second end of the pull-up module is respectively connected with the second end of the power storage module and the first end of the first pull-down module;
the second end of the pull-down maintaining module is connected with the second end of the first pull-down module, the third end of the pull-down maintaining module is connected with the first end of the second pull-down module, and the fourth end of the pull-down maintaining module is connected with the second end of the second pull-down module; the third end of the second pull-down module is connected with the first end of the upper pull-up control module.
Optionally, the GOA circuit further comprises a leakage prevention module; the first end of the electricity leakage prevention module is respectively connected with the first end of the upper pull-up module, the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the electricity storage module.
Optionally, the pull-up module includes a thin film transistor T1; a grid electrode of the thin film transistor T1 is respectively connected with a first end of the pull-up control module, a first end of the pull-down maintaining module and a first end of the electricity storage module, a source electrode is respectively connected with a second end of the electricity storage module and a first end of the first pull-down module, and a drain electrode is connected with a first clock signal; the source of the thin film transistor T1 is used as the output terminal of the current row gate output signal.
Optionally, the pull-up control module includes a thin film transistor T2 and a thin film transistor T3; the gate of the thin film transistor T2 and the gate of the thin film transistor T3 are connected to the drain of the thin film transistor T2; the source electrode of the thin film transistor T2 is connected with the drain electrode of the thin film transistor T3; the source electrode of the thin film transistor T3 is respectively connected with the gate electrode of the thin film transistor T1, the first end of the pull-down maintaining module and the first end of the electricity storage module; the drain electrode of the thin film transistor T2 is used as the input end of the last row of gate output signals; the source of the thin film transistor T2 and the drain of the thin film transistor T3 function together as a signal input terminal.
Optionally, the pull-down maintaining module includes a thin film transistor T4, a thin film transistor T5, a thin film transistor T6, a thin film transistor T7, a thin film transistor T8, and a capacitor C1;
the drain electrode of the thin film transistor T4 is respectively connected to the gate electrode of the thin film transistor T1, the source electrode of the thin film transistor T3 and the first end of the power storage module, and the source electrode is respectively connected to the drain electrode of the thin film transistor T5 and the first end of the second pull-down module;
the grid electrode of the thin film transistor T4 and the grid electrode of the thin film transistor T5 are respectively connected with the source electrode of the thin film transistor T6 and the drain electrode of the thin film transistor T7, and the source electrode of the thin film transistor T5 is connected with the second end of the second pull-down module; the source electrode of the thin film transistor T5 is used as the input end of the first off voltage; the source electrode of the thin film transistor T4 and the drain electrode of the thin film transistor T5 are commonly used as a signal input terminal;
the gate of the thin film transistor T6 is used as the input terminal of the second clock signal, and the drain is used as the input terminal of the start voltage; the source electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T5, the first end of the capacitor C1 and the source electrode of the thin film transistor T8;
the drain electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T6, the second end of the capacitor C1 and the drain electrode of the thin film transistor T8; the gate of the thin film transistor T7 is used as the input terminal of the signal; the gate of the tft T8 is connected to the input terminal of the row-connected gate output signal.
Optionally, the power storage module comprises a capacitor C2; the capacitor C2 has a first terminal connected to the source of the thin film transistor T1, the source of the thin film transistor T3 and the drain of the thin film transistor T4, and a second terminal connected to the source of the thin film transistor T1.
Optionally, the first pull-down module includes a thin film transistor T9; the drain of the thin film transistor T9 is connected to the source of the thin film transistor T1 and the second end of the capacitor C2, respectively, and the gate is connected to the gate of the thin film transistor T4, the gate of the thin film transistor T5, the source of the thin film transistor T6, the drain of the thin film transistor T7, the capacitor C1 and the drain of the thin film transistor T8, respectively; the source of the thin film transistor T9 serves as an input terminal for the second off voltage.
Optionally, the second pull-down module includes a thin film transistor T10 and a thin film transistor T11;
the drain electrode of the thin film transistor T10 is connected with the source electrode of the thin film transistor T3, and the source electrode is respectively connected with the drain electrode of the thin film transistor T11, the source electrode of the thin film transistor T4 and the drain electrode of the thin film transistor T5; the source electrode of the thin film transistor T11 is connected with the source electrode of the thin film transistor T5; the grid of the thin film transistor T10 and the grid of the thin film transistor T11 are used as the input end of the next row of grid output signals together; the source of the thin film transistor T11 serves as an input terminal for the first off voltage.
Optionally, the anticreeping module includes a thin film transistor T12; the grid and the drain of the thin film transistor T12 are respectively connected with the first end of the pull-up module, the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the power storage module; the source of the thin film transistor T12 serves as a signal input terminal.
In a second aspect, an embodiment of the present application provides a display panel including the GOA circuit as described above.
One of the above technical solutions has the following advantages and beneficial effects:
the GOA circuit provided in each embodiment of the present application includes a pull-up module, a pull-up control module, a pull-down maintenance module, an electricity storage module, a first pull-down module, and a second pull-down module, specifically, a first end of the pull-up module is respectively connected to a first end of the pull-up control module, a first end of the pull-down maintenance module, and a first end of the electricity storage module, and a second end of the pull-up module is respectively connected to a second end of the electricity storage module and a first end of the first pull-down module; the second end of the pull-down maintaining module is connected with the second end of the first pull-down module, the third end of the pull-down maintaining module is connected with the first end of the second pull-down module, and the fourth end of the pull-down maintaining module is connected with the second end of the second pull-down module; the third end of second pull-down module connects the first end of pull-up control module, and the problem that the direct current passageway of high low level and cause the influence to circuit stability can be avoided producing at specific operating time to this application GOA circuit.
Drawings
Fig. 1 is a schematic diagram of a first structure of a GOA circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic circuit diagram of a GOA circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a second structure of a GOA circuit according to an embodiment of the present disclosure.
Fig. 4 is a second circuit diagram of a GOA circuit according to an embodiment of the present disclosure.
Fig. 5 is an operation timing diagram of a GOA circuit according to the present application.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In order to solve the problem that the inverters in the conventional technology have high and low levels of dc channels in a specific operating time and affect the stability of the circuit, as shown in fig. 1, a GOA circuit 1 is provided, which includes a pull-up module 11, a pull-up control module 12, a pull-down maintaining module 13, an electric shock module 14, a first pull-down module 15, and a second pull-down module 16.
The connection relationship among the pull-up module 11, the pull-up control module 12, the pull-down maintaining module 13, the electric shock module 14, the first pull-down module 15 and the second pull-down module 16 is as follows: a first end of the pull-up module 11 is connected to a first end of the pull-up control module 12, a first end of the pull-down maintaining module 13, and a first end of the electric shock module 14, respectively, and a second end is connected to a second end of the electric shock module 14 and a first end of the first pull-down module 15, respectively. A second end of the pull-down maintaining module 13 is connected to a second end of the first pull-down module 15, a third end is connected to a first end of the second pull-down module 16, and a fourth end is connected to a second end of the second pull-down module 16; the third terminal of the second pull-down module 16 is connected to the first terminal of the pull-up control module 12.
It should be noted that there are many ways to implement the pull-up module 11, and for example, a pull-up module 11 is provided, as shown in fig. 2, which includes a thin film transistor T1. Specifically, the gate of the thin film transistor T1 is connected to the first terminal of the pull-up control module 12, the first terminal of the pull-down sustain module 13, and the first terminal of the contact module 14, the source is connected to the second terminal of the contact module 14 and the first terminal of the first pull-down module 15, and the drain is connected to the first clock signal (e.g., CK1 in fig. 2 and 4); the source of the thin film transistor T1 is used as the output terminal for the current row gate output signal (Cout n in fig. 2 and 4). In one example, the thin film transistor T1 is an N-type thin film transistor.
There are many ways to implement the pull-up control module 12, and for example, there is provided a pull-up control module 12, as shown in fig. 2, including a thin film transistor T2 and a thin film transistor T3. Specifically, the gate of the thin film transistor T2 and the gate of the thin film transistor T3 are connected to the drain of the thin film transistor T2; the source electrode of the thin film transistor T2 is connected with the drain electrode of the thin film transistor T3; the source of the thin film transistor T3 is connected to the gate of the thin film transistor T1, the first terminal of the pull-down sustain module 13 and the first terminal of the contact module 14, respectively; the drain of the thin film transistor T2 is used as the input terminal for the previous row of gate output signals (Cout [ n-1] in fig. 2 and 4); the source of the thin film transistor T2 and the drain of the thin film transistor T3 collectively serve as a signal input terminal (e.g., N [ N ] in FIGS. 2 and 4). In one example, the thin film transistor T2 and the thin film transistor T3 are N-type thin film transistors.
The pull-down maintaining module 13 may be implemented in many ways, and for example, a pull-down maintaining module 13 is provided, as shown in fig. 2, including a thin film transistor T4, a thin film transistor T5, a thin film transistor T6, a thin film transistor T7, a thin film transistor T8, and a capacitor C1. Specifically, the drain of the tft T4 is connected to the gate of the tft T1, the source of the tft T3 and the first end of the contact module 14, and the source is connected to the drain of the tft T5 and the first end of the second pull-down module 16; the gate of the thin film transistor T4 and the gate of the thin film transistor T5 are both connected to the source of the thin film transistor T6 and the drain of the thin film transistor T7, respectively, and the source of the thin film transistor T5 is connected to the second terminal of the second pull-down module 16; the source electrode of the thin film transistor T5 is used as the input end of the first off voltage; a gate electrode of the thin film transistor T6 serves as an input terminal of a second clock signal (e.g., CK2 in fig. 2 and 4), and a drain electrode serves as an input terminal of a start voltage (e.g., VGH in fig. 2 and 4); the source electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T5, the first end of the capacitor C1 and the source electrode of the thin film transistor T8; the drain electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T6, the second end of the capacitor C1 and the drain electrode of the thin film transistor T8; the gate of the thin film transistor T7 is used as the input terminal of the signal; the gate of the tft T8 is connected to the input terminal of the row-connected gate output signal. In one example, the thin film transistors T4, T5, T6, T7, and T8 are N-type thin film transistors.
The implementation of the shock module 14 is various, and for example, a shock module 14 is provided, as shown in fig. 2, including a capacitor C2. Specifically, the capacitor C2 has a first terminal connected to the source of the thin film transistor T1, the source of the thin film transistor T3, and the drain of the thin film transistor T4, and a second terminal connected to the source of the thin film transistor T1.
The first pull-down module 15 may be implemented in many ways, and for example, a first pull-down module 15 is provided, as shown in fig. 2, including a thin film transistor T9. Specifically, the drain of the thin film transistor T9 is connected to the source of the thin film transistor T1 and the second end of the capacitor C2, and the gate is connected to the gate of the thin film transistor T4, the gate of the thin film transistor T5, the source of the thin film transistor T6, the drain of the thin film transistor T7, the capacitor C1, and the drain of the thin film transistor T8; the source of the thin film transistor T9 serves as an input terminal for the second off voltage. In one example, the thin film transistor T9 is an N-type thin film transistor.
The second pull-down module 16 may be implemented in many ways, and for example, a second pull-down module 16 is provided, as shown in fig. 2, including a thin film transistor T10 and a thin film transistor T11. Specifically, the drain of the thin film transistor T10 is connected to the source of the thin film transistor T3, and the source is connected to the drain of the thin film transistor T11, the source of the thin film transistor T4 and the drain of the thin film transistor T5, respectively; the source electrode of the thin film transistor T11 is connected with the source electrode of the thin film transistor T5; the gate of the thin film transistor T10 and the gate of the thin film transistor T11 are used together as the input terminal of the next row of gate output signals (Cout [ n +1] in fig. 2 and 4); the source of the thin film transistor T11 serves as an input terminal for a first off voltage (e.g., VGL1 in fig. 2 and 4). In one example, the thin film transistor T10 and the thin film transistor T11 are N-type thin film transistors.
To include circuit leakage, in one example, as shown in fig. 3, the GOA circuit 1 further includes an anti-leakage module 17; the first end of the anti-creeping module 17 is connected to the first end of the upper pull module 11, the first end of the upper pull control module 12, the first end of the lower pull maintaining module 13 and the first end of the electric shock module 14, respectively.
It should be noted that there are many ways to implement the anti-creeping module 17, and for example, an anti-creeping module 17 is provided, as shown in fig. 4, which includes a thin film transistor T12. Specifically, the gate and the drain of the thin film transistor T12 are respectively connected to the first end of the pull-up module 11, the first end of the pull-up control module 12, the first end of the pull-down maintaining module 13, and the first end of the contact module 14; the source of the thin film transistor T12 serves as a signal input terminal. In one example, the thin film transistor T12 is an N-type thin film transistor.
In order to make the structure and operation principle of the pixel circuit 1 more clear, a specific embodiment is provided for explanation.
As shown in fig. 4, a GOA circuit 1 includes a thin film transistor T1, a thin film transistor T2, a thin film transistor T3, a thin film transistor T4, a thin film transistor T5, a thin film transistor T6, a thin film transistor T7, a thin film transistor T8, a thin film transistor T9, a thin film transistor T10, a thin film transistor T11, a thin film transistor T12, a capacitor C1, and a capacitor C2.
A gate of the thin film transistor T1 is connected to a source of the thin film transistor T3, a drain of the thin film transistor T4, a gate and a drain of the thin film transistor T12, and a first end of the capacitor C2, respectively, a source of the thin film transistor T1 is connected to a second end of the capacitor C2 and a drain of the thin film transistor T9, respectively, and a drain of the thin film transistor T1 is connected to a first clock signal; the source of the thin film transistor T1 is used as the output terminal of the current row gate output signal.
The gate of the thin film transistor T2 and the gate of the thin film transistor T3 are connected to the drain of the thin film transistor T2; the source electrode of the thin film transistor T2 is connected with the drain electrode of the thin film transistor T3; the source electrode of the thin film transistor T3 is connected with the gate electrode of the thin film transistor T1; the drain electrode of the thin film transistor T2 is used as the input end of the last row of gate output signals; the source of the thin film transistor T2 and the drain of the thin film transistor T3 function together as a signal input terminal.
The drain of the thin film transistor T4 is connected to the gate of the thin film transistor T1, the source of the thin film transistor T3, and the first terminal of the capacitor C2, respectively, and the source is connected to the drain of the thin film transistor T5, the source of the thin film transistor T10, and the drain of the thin film transistor T11, respectively.
The gate of the thin film transistor T4 and the gate of the thin film transistor T5 are both connected to the source of the thin film transistor T6 and the drain of the thin film transistor T7, respectively, and the source of the thin film transistor T5 is connected to the source of the thin film transistor T11; the source of the thin film transistor T5 serves as an input terminal for the first off voltage. The source of the thin film transistor T4 and the drain of the thin film transistor T5 function together as a signal input terminal.
The gate of the thin film transistor T6 is used as the input terminal of the second clock signal, and the drain is used as the input terminal of the start voltage; a source of the thin film transistor T7 is connected to the source of the thin film transistor T5, the first terminal of the capacitor C1 and the source of the thin film transistor T8, respectively.
The drain electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T6, the second end of the capacitor C1 and the drain electrode of the thin film transistor T8; the gate of the thin film transistor T7 is used as the input terminal of the signal; the gate of the tft T8 is connected to the input terminal of the row-connected gate output signal.
The drain of the thin film transistor T9 is connected to the source of the thin film transistor T1 and the second end of the capacitor C2, respectively, and the gate is connected to the gate of the thin film transistor T4, the gate of the thin film transistor T5, the source of the thin film transistor T6, the drain of the thin film transistor T7, the capacitor C1 and the drain of the thin film transistor T8, respectively; the source of the thin film transistor T9 serves as an input terminal for a second off voltage (e.g., VGL2 in fig. 2 and 4).
The drain electrode of the thin film transistor T10 is connected with the source electrode of the thin film transistor T3, and the source electrode is respectively connected with the drain electrode of the thin film transistor T11, the source electrode of the thin film transistor T4 and the drain electrode of the thin film transistor T5; the source electrode of the thin film transistor T11 is connected with the source electrode of the thin film transistor T5; the grid of the thin film transistor T10 and the grid of the thin film transistor T11 are used as the input end of the next row of grid output signals together; the source of the thin film transistor T11 serves as an input terminal for the first off voltage.
A gate and a drain of the thin film transistor T12 are respectively connected to the first terminal of the pull-up module 11, the first terminal of the pull-up control module 12, the first terminal of the pull-down maintaining module 13, and the first terminal of the contact module 14; the source of the thin film transistor T12 serves as a signal input terminal.
In conjunction with the operation sequence shown in fig. 5, the GOA circuit 1 of the present invention includes four stages: in the first phase, the second clock signal (CK 2 in fig. 2 and 4) is at high level, the thin film transistor T6 is turned on, the QB point (shown in fig. 2 and 4) is maintained at high level, and the thin film transistor T9 is continuously turned off; in the second stage, the second clock signal is at a low potential, the thin film transistor T6 is turned off, the output signal of the previous row gate is at a high level, the thin film transistor T8 is turned on, QB is pulled down to a first off voltage, the thin film transistor T2 and the thin film transistor T3 are turned on at the same time, the Q point (as shown in fig. 2 and 4) is written into a high level, the thin film transistor T5 is turned on, and the thin film transistor T12 is turned on to charge the N point high, thereby preventing the Q point from generating a leakage phenomenon due to pull-up control and pull-down module; in the third stage, the first clock signal is at a high level, the Q point is further increased due to the coupling effect of the capacitor C2, and the thin film transistor T1 outputs a high potential; in the fourth phase, the next row gate output signal is high, pulling the point Q low, and since the second clock signal is high, turning on the thin film transistor T6 and storing charge by the capacitor C1, the high level of QB is maintained.
In the working process, because the thin film transistor T6 and the thin film transistor T7 do not have the moment of being simultaneously turned on, the direct current path of the turn-on voltage and the turn-off voltage is avoided, and the circuit burning process can be effectively improved. The on voltage refers to an on voltage of the thin film transistor, and the off voltage refers to an off voltage of the thin film transistor.
The GOA circuit 1 includes a pull-up module 11, a pull-up control module 12, a pull-down maintenance module 13, an electric shock module 14, a first pull-down module 15, and a second pull-down module 16, specifically, a first end of the pull-up module 11 is respectively connected to a first end of the pull-up control module 12, a first end of the pull-down maintenance module 13, and a first end of the electric shock module 14, and a second end of the pull-up module 11 is respectively connected to a second end of the electric shock module 14 and a first end of the first pull-down module 15; a second end of the pull-down maintaining module 13 is connected to a second end of the first pull-down module 15, a third end is connected to a first end of the second pull-down module 16, and a fourth end is connected to a second end of the second pull-down module 16; the third end of the second pull-down module 16 is connected to the first end of the pull-up control module 12, and the GOA circuit 1 of the present application can avoid the problem of influence on the circuit stability caused by the production of a high-low level dc channel in a specific working time.
Applying the above-mentioned GOA circuit 1 of the present application to a display panel, a display panel is provided, which comprises the above-mentioned GOA circuit 1.
It should be noted that the GOA circuit 1 in this embodiment is the same as that in the embodiments of the GOA circuit 1 of this application, and please refer to the embodiments of the GOA circuit 1 of this application for details, which will not be described herein again.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A GOA circuit is characterized by comprising a pull-up module, a pull-up control module, a pull-down maintaining module, an electricity storage module, a first pull-down module and a second pull-down module;
the first end of the pull-up module is respectively connected with the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the power storage module, and the second end of the pull-up module is respectively connected with the second end of the power storage module and the first end of the first pull-down module;
the second end of the pull-down maintaining module is connected with the second end of the first pull-down module, the third end of the pull-down maintaining module is connected with the first end of the second pull-down module, and the fourth end of the pull-down maintaining module is connected with the second end of the second pull-down module; and the third end of the second pull-down module is connected with the first end of the pull-up control module.
2. The GOA circuit of claim 1, further comprising a leakage prevention module;
the first end of the electricity leakage prevention module is respectively connected with the first end of the pull-up module, the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the electricity storage module.
3. A GOA circuit according to claim 1 or 2, characterized in that the pull-up module comprises a thin film transistor T1;
a gate of the thin film transistor T1 is connected to a first end of the pull-up control module, a first end of the pull-down sustain module, and a first end of the power storage module, a source is connected to a second end of the power storage module and a first end of the first pull-down module, and a drain is connected to a first clock signal; the source of the thin film transistor T1 is used as the output terminal of the current row gate output signal.
4. The GOA circuit of claim 3, wherein the pull-up control module comprises a thin film transistor T2 and a thin film transistor T3;
the gate electrode of the thin film transistor T2 and the gate electrode of the thin film transistor T3 are connected to the drain electrode of the thin film transistor T2; the source electrode of the thin film transistor T2 is connected with the drain electrode of the thin film transistor T3; the source electrode of the thin film transistor T3 is respectively connected with the gate electrode of the thin film transistor T1, the first end of the pull-down maintaining module and the first end of the power storage module; the drain electrode of the thin film transistor T2 is used as the input end of the last row of grid output signals; the source of the thin film transistor T2 and the drain of the thin film transistor T3 collectively serve as a signal input terminal.
5. The GOA circuit of claim 4, wherein the pull-down maintaining module comprises a thin film transistor T4, a thin film transistor T5, a thin film transistor T6, a thin film transistor T7, a thin film transistor T8 and a capacitor C1;
the drain electrode of the thin film transistor T4 is respectively connected to the gate electrode of the thin film transistor T1, the source electrode of the thin film transistor T3 and the first end of the power storage module, and the source electrode is respectively connected to the drain electrode of the thin film transistor T5 and the first end of the second pull-down module;
the gate of the thin film transistor T4 and the gate of the thin film transistor T5 are both connected to the source of the thin film transistor T6 and the drain of the thin film transistor T7, respectively, and the source of the thin film transistor T5 is connected to the second end of the second pull-down module; the source electrode of the thin film transistor T5 is used as the input end of a first closing voltage; the source of the thin film transistor T4 and the drain of the thin film transistor T5 collectively serve as a signal input terminal.
The grid electrode of the thin film transistor T6 is used as the input end of a second clock signal, and the drain electrode is used as the input end of starting voltage; the source electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T5, the first end of the capacitor C1 and the source electrode of the thin film transistor T8;
the drain electrode of the thin film transistor T7 is respectively connected with the source electrode of the thin film transistor T6, the second end of the capacitor C1 and the drain electrode of the thin film transistor T8; the grid electrode of the thin film transistor T7 is used as the input end of a signal; the gate of the thin film transistor T8 is connected to the input end of the output signal of the upper row of gates.
6. The GOA circuit of claim 5, wherein the power storage module comprises a capacitor C2;
the capacitor C2 has a first end connected to the source of the thin film transistor T1, the source of the thin film transistor T3 and the drain of the thin film transistor T4, and a second end connected to the source of the thin film transistor T1.
7. The GOA circuit of claim 6, wherein the first pull-down module comprises a thin film transistor T9;
the drain of the thin film transistor T9 is connected to the source of the thin film transistor T1 and the second end of the capacitor C2, and the gate is connected to the gate of the thin film transistor T4, the gate of the thin film transistor T5, the source of the thin film transistor T6, the drain of the thin film transistor T7, the capacitor C1 and the drain of the thin film transistor T8; the source of the thin film transistor T9 serves as an input terminal for a second off voltage.
8. The GOA circuit of any one of claims 7, wherein the second pull-down module comprises a thin film transistor T10 and a thin film transistor T11;
the drain electrode of the thin film transistor T10 is connected with the source electrode of the thin film transistor T3, and the source electrode is respectively connected with the drain electrode of the thin film transistor T11, the source electrode of the thin film transistor T4 and the drain electrode of the thin film transistor T5; the source electrode of the thin film transistor T11 is connected with the source electrode of the thin film transistor T5; the grid electrode of the thin film transistor T10 and the grid electrode of the thin film transistor T11 are used as the input end of the next row of grid electrode output signals together; the source of the thin film transistor T11 serves as an input terminal for a first off voltage.
9. The GOA circuit according to any one of claims 2 to 8, wherein the anti-leakage module comprises a thin film transistor T12;
the grid electrode and the drain electrode of the thin film transistor T12 are respectively connected with the first end of the pull-up module, the first end of the pull-up control module, the first end of the pull-down maintaining module and the first end of the power storage module; the source of the thin film transistor T12 serves as a signal input terminal.
10. A display panel comprising a GOA circuit according to any one of claims 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160164514A1 (en) * | 2014-12-08 | 2016-06-09 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Scan driving circuit |
| CN106782365A (en) * | 2016-12-15 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and driving method, display device |
| CN106898290A (en) * | 2017-04-21 | 2017-06-27 | 深圳市华星光电技术有限公司 | Scan drive circuit |
| CN111179811A (en) * | 2020-03-12 | 2020-05-19 | 武汉华星光电半导体显示技术有限公司 | Shifting register unit, grid driving circuit and display panel |
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2021
- 2021-12-29 CN CN202111641199.2A patent/CN114220376B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160164514A1 (en) * | 2014-12-08 | 2016-06-09 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Scan driving circuit |
| CN106782365A (en) * | 2016-12-15 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and driving method, display device |
| CN106898290A (en) * | 2017-04-21 | 2017-06-27 | 深圳市华星光电技术有限公司 | Scan drive circuit |
| CN111179811A (en) * | 2020-03-12 | 2020-05-19 | 武汉华星光电半导体显示技术有限公司 | Shifting register unit, grid driving circuit and display panel |
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