CN111326097B

CN111326097B - GOA circuit and display panel

Info

Publication number: CN111326097B
Application number: CN202010266714.2A
Authority: CN
Inventors: 陶健
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-04-07
Filing date: 2020-04-07
Publication date: 2021-12-03
Anticipated expiration: 2040-04-07
Also published as: CN111326097A

Abstract

The embodiment of the application provides a GOA circuit and a display panel, in which a tenth transistor T10 is added to a pull-up module and an eleventh transistor T11 is added to a pull-down module of each stage of GOA unit, a drain of the tenth transistor T1 and a drain of the eleventh transistor T11 are both electrically connected to a stage pass terminal cs (n), and a stage pass terminal cs (n) signal is used as a stage pass signal of the next stage of GOA unit. Compared with the output end G (N) signal, the load of the stage transmission end CS (N) signal is extremely small, so that although the output end G (N) signal is distorted, the output waveform of the stage transmission end CS (N) signal is not distorted basically, the stage transmission end CS (N) signal replaces the output end G (N) signal to be used as the stage transmission signal of the next-stage GOA unit, the charging of the first node Qb and the pull-up node Qa of the next-stage GOA unit is not influenced, and the stability of the GOA circuit cascade is improved.

Description

GOA circuit and display panel

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

The goa (gate Driver On array) technology integrates a gate driving circuit of a display panel On a glass substrate to form a scanning drive for the display panel. The GOA technology can reduce binding (binding) procedures of an external IC, can reduce product cost, and is more suitable for manufacturing narrow-frame or frameless display products.

The conventional GOA circuit comprises a plurality of cascaded GOA units, wherein each GOA unit correspondingly drives one level of horizontal scanning lines. Each GOA unit mainly comprises a pull-up circuit, a pull-up control circuit, a pull-down circuit and a pull-down maintaining circuit. The pull-up circuit is mainly responsible for outputting a clock signal as a grid signal, namely a Gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit and is generally connected with a Gate signal transmitted by the previous GOA unit; the pull-down circuit is responsible for pulling down the Gate signal to a low potential at the first time, namely closing the Gate signal; the pull-down maintaining circuit is responsible for maintaining the Gate signal and the Gate signal (commonly referred to as the Q-point) of the pull-up circuit in an off state.

Fig. 1 is a diagram of a conventional GOA circuit, in which the Gate signal of the GOA units of the upper and lower stages is a Gate signal, fig. 2 is an ideal timing diagram of a conventional GOA circuit, fig. 3 is a simulated timing diagram of a conventional GOA circuit, and referring to fig. 1, 2 and 3, it can be seen that the waveform is distorted due to the Gate signal being connected to the load, for example, the waveforms in fig. 3 of the node Qa and the node Qb at t1 and t2 are both reduced in amplitude compared to the waveforms in fig. 2, the distortion is more obvious the larger the load is, which results in insufficient opening of the first transistor NT1 or NT2 of the next-stage GOA unit, causing insufficient charging of the node Qa and the node Qb, thereby causing insufficient opening of NT3, the Gate signal Gate (N +1) of the next-stage GOA unit is distorted, and Gate (N +1) affects the opening of NT1 of the next-stage GOA unit, and the number of cascades is increased, the distortions may be superimposed one level by one level, which may cause display abnormality of the display panel.

Therefore, it is necessary to design a new GOA circuit to solve the above display abnormality problem caused by Gate signal distortion.

Disclosure of Invention

In order to solve the problem of display abnormality of a current GOA circuit due to Gate signal distortion, an embodiment of the present application provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units, and each of the GOA units includes: the scanning circuit comprises a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, an anti-creeping module 500, a voltage stabilizing module 600 and a signal control module 700.

The forward and reverse scanning module 100 includes a first transistor T1 and a second transistor T2, wherein a gate of the first transistor T1 is connected to a stage transfer terminal CS (N-1) of an upper-level GOA unit, a source is connected to a forward scanning signal U2D, and a drain is electrically connected to a first node Qb; the gate of the second transistor T2 is connected to the stage pass terminal CS (N +1) of the next GOA unit, the source is connected to the reverse scan signal D2U, and the drain is electrically connected to the first node Qb.

The Reset module 200 includes a seventh transistor T7, wherein the seventh transistor T7 has a gate and a source connected to a Reset signal Reset, and a drain electrically connected to the second node P.

The pull-up module 300 includes a third transistor T3 and a tenth transistor T10, wherein gates of the third transistor T3 and the tenth transistor T10 are both electrically connected to a pull-up node Qa, sources of the third transistor T3 and the tenth transistor T10 are both connected to an nth clock signal ck (N), a drain of the third transistor T3 is electrically connected to an output terminal g (N), and a drain of the tenth transistor T10 is electrically connected to a stage transmission terminal cs (N).

The pull-down module 400 includes a fourth transistor T4, an eleventh transistor T11, and a ninth transistor T9, wherein gates of the fourth transistor T4, the eleventh transistor T11, and the ninth transistor T9 are all electrically connected to the second node P, sources of the fourth transistor T4, the eleventh transistor T11, and the ninth transistor T9 are all connected to a first potential, a drain of the fourth transistor T4 is electrically connected to the output terminal g (n), a drain of the eleventh transistor T11 is electrically connected to the stage terminal cs (n), and a drain of the ninth transistor T9 is electrically connected to the first node Qb.

The anti-leakage module 500 includes a twelfth transistor T12, wherein the gate of the twelfth transistor T12 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the pull-up node Qa.

The voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; one end of the second capacitor C2 is electrically connected to the second node P, and the other end is connected to the first potential.

The signal control module 700 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is electrically connected to the second node P; the gate of the sixth transistor T6 is connected to the (N +1) th clock signal CK (N +1), the source is connected to the second potential, and the drain is electrically connected to the second node P.

In some embodiments, the GOA circuit has a reset phase and a normal display phase.

In the Reset phase, the Reset signal Reset provides a pulse signal of the second potential to control the seventh transistor T7 to be turned on so that the second node P is the second potential, and the second node P controls the fourth transistor T4, the eleventh transistor T11 and the tenth transistor T10 to be turned on so that the output terminal g (n), the stage pass terminal cs (n), the first node Qb and the pull-up node Qa are the first potential.

The normal display phase includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t 3.

In the pre-charge sub-phase T1, providing the second level to the pass terminal CS (N-1) of the upper GOA cell or the pass terminal CS (N +1) of the lower GOA cell turns on the first transistor T1 or the second transistor T2, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged, and simultaneously turns on the third transistor T3, the tenth transistor T10 and the fifth transistor T5; the fifth transistor T5 is turned on to convert the second node P into the first potential, so that the fourth transistor T4, the eleventh transistor T11 and the ninth transistor T9 are turned off.

At the output sub-stage T2, the pass terminal CS (N-1) of the upper GOA unit and the pass terminal CS (N +1) of the lower GOA unit provide a first level to turn off the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on to keep the first node Qb at the second potential, and the pull-up node Qa is switched from the second potential to a bootstrap potential; meanwhile, the nth clock signal ck (N) provides the second potential, and is output as the output terminal g (N) signal through the third transistor T3, and is output as the stage transmission terminal cs (N) signal through the tenth transistor T10.

In the pull-down sub-phase T3, the stage pass terminal CS (N-1) of the upper GOA cell or the stage pass terminal CS (N +1) of the lower GOA cell provides the second potential to turn on the first transistor T1 or the second transistor T2, the forward scan signal U2D or the reverse scan signal D2U provides the first potential to the first node Qb and the pull-up node Qa, and the N +1 clock signal CK (N +1) turns on the sixth transistor T6 to convert the second node P into the second potential and the second capacitor C2 is charged, and the second node P turns on the fourth transistor T4, the eleventh transistor T11 and the ninth transistor T9 to convert the output terminal g (N), the stage pass terminal CS (N), the first node Qb and the pull-up node Qa into the first potential.

Thereafter, the first capacitor C1 maintains the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 turned off, the second capacitor C2 maintains the second node P at the second potential to keep the fourth transistor T4 turned on, and the output terminal g (n) and the stage transfer terminal cs (n) maintain the first potential.

In some embodiments, one of the forward scan signal U2D and the reverse scan signal D2U is high and the other is low; during forward scanning, the stage pass terminal CS (N-1) of the upper GOA unit controls the first transistor T1 to be turned on, and the gate of the first transistor T1 of the first GOA unit is connected to the start signal STV; in the reverse scan, the stage pass terminal CS (N +1) of the lower GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the last GOA unit is connected to the start signal STV.

In some embodiments, each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.

In the Reset phase, the Reset signal Reset provides a single high-level pulse signal to make the second node P high, and the first node Qb, the pull-up node Qa, the forward scan signal U2D, the reverse scan signal D2U, the nth clock signal CK (N), the N +1 th clock signal CK (N +1), the output terminal g (N), the level pass terminal CS (N-1) of the upper GOA unit, and the level pass terminal CS (N +1) of the lower GOA unit are all low;

in the pre-charge sub-stage t1 of the normal display stage, the forward scan signal U2D is a constant voltage high voltage VGH and the reverse scan signal D2U is a constant voltage low voltage VGL during forward scan, the forward scan signal U2D is a constant voltage low voltage VGL and the reverse scan signal D2U is a constant voltage high voltage VGH during reverse scan, the second node P, the nth clock signal CK (N), the N +1 clock signal CK (N +1), the output terminal g (N), the level transfer terminal CS (N), and the level transfer terminal CS (N +1) of the next GOA unit are all low voltages, and the level transfer terminal CS (N-1) of the previous GOA unit, the first node Qb, and the pull-up node Qa are all high voltages.

In the output sub-stage t2 of the normal display stage, the second node P, the N +1 th clock signal CK (N +1), the level transfer terminal CS (N-1) of the upper GOA unit, and the level transfer terminal CS (N +1) of the lower GOA unit are all low potentials, the first node Qb, the pull-up node Qa, the nth clock signal CK (N), the output terminal g (N), and the level transfer terminal CS (N) are all high potentials, and the pull-up node Qa is raised to the bootstrap potential by the constant voltage high potential VGH. In the pull-down sub-stage t3 of the normal display stage, the first node Qb, the pull-up node Qa, the nth clock signal CK (N), the output terminal g (N), the level transfer terminal CS (N), and the level transfer terminal CS (N-1) of the upper GOA unit are all low potentials, and the second node P, the N +1 th clock signal CK (N +1), and the level transfer terminal CS (N +1) of the lower GOA unit are all high potentials.

In some embodiments, the GOA circuit further includes an output control module 800, wherein the output control module 800 includes an eighth transistor T8, a gate of the eighth transistor T8 is connected to the global control signal GAS, a source of the eighth transistor T8 is connected to the first potential, and a drain of the eighth transistor T8 is electrically connected to the output terminal g (n).

In some embodiments, the GOA circuitry further includes a touch scan phase after the normal display phase; in the touch scanning stage, the global control signal GAS controls the output ends g (n) of all the levels of the GOA units to be converted into a first potential.

In some embodiments, each transistor in the GOA circuit is an N-type thin film transistor, and the global control signal GAS is at a low potential in the reset phase and the normal display phase, and at a high potential in the touch scan phase.

In some embodiments, each clock signal is a periodic pulse signal in the reset phase and the normal display phase; in the touch scanning stage, each clock signal is a pulse signal with the frequency synchronous with that of the touch scanning signal.

In some embodiments, the GOA circuit includes a first clock signal CK1 and a second clock signal CK 2; when the nth clock signal CK (N) is the first clock signal CK1, the (N +1) th clock signal CK (N +1) is CK 2; in the reset phase and the normal display phase, the first clock signal CK1 and the second clock signal CK2 have the same period, and a pulse signal of a previous clock signal ends while a pulse signal of a next clock signal is generated.

The embodiment of the present application further provides a display panel, which includes the GOA circuit as described above.

In the GOA circuit provided in the embodiments of the present invention, a tenth transistor T10 is added to the pull-up module of each of the GOA units, an eleventh transistor T11 is added to the pull-down module, the drain of the tenth transistor T1 and the drain of the eleventh transistor T11 are both electrically connected to the stage pass terminal cs (n), and the signal of the stage pass terminal cs (n) is used as the stage pass signal of the next GOA unit. Compared with the output end G (N) signal, the load of the stage transmission end CS (N) signal is extremely small, so that although the output end G (N) signal is distorted, the output waveform of the stage transmission end CS (N) signal is not distorted basically, the stage transmission end CS (N) signal replaces the output end G (N) signal to be used as the stage transmission signal of the next-stage GOA unit, the charging of the first node Qb and the pull-up node Qa of the next-stage GOA unit is not influenced, and the stability of the GOA circuit cascade is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional GOA circuit;

FIG. 2 is an ideal timing diagram of a GOA circuit of the prior art;

FIG. 3 is a simulated timing diagram of a GOA circuit according to the prior art;

FIG. 4 is a schematic diagram of a GOA circuit according to an embodiment of the present invention;

FIG. 5 is an ideal timing diagram of a GOA circuit according to an embodiment of the present invention;

FIG. 6 is a simulated timing diagram of a GOA circuit according to an embodiment of the present invention;

fig. 7 is a simulation comparison diagram of the pull-up node Qa in the GOA circuit of the prior art and the GOA circuit according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 4, fig. 4 is a diagram of a GOA circuit according to an embodiment of the present invention, where the GOA circuit includes cascaded multiple levels of GOA units, each level of GOA unit includes: the scanning circuit comprises a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, an anti-creeping module 500, a voltage stabilizing module 600 and a signal control module 700.

The forward-reverse scanning module 100 includes a first transistor T1 and a second transistor T2, a gate of the first transistor T1 is connected to a stage transfer terminal CS (N-1) of the upper-level GOA unit, a source is connected to a forward scanning signal U2D, and a drain is electrically connected to a first node Qb; the gate of the second transistor T2 is connected to the stage pass terminal CS (N +1) of the next GOA unit, the source is connected to the reverse scan signal D2U, and the drain is electrically connected to the first node Qb.

The Reset module 200 includes a seventh transistor T7, a gate and a source of the seventh transistor T7 both receive a Reset signal Reset, and a drain of the seventh transistor T7 is electrically connected to the second node P.

The pull-up module 300 includes a third transistor T3 and a tenth transistor T10, gates of the third transistor T3 and the tenth transistor T10 are both electrically connected to the pull-up node Qa, sources of the third transistor T3 and the tenth transistor T10 are both connected to the nth clock signal ck (N), a drain of the third transistor T3 is electrically connected to the output terminal g (N), and a drain of the tenth transistor T10 is electrically connected to the stage transmission terminal cs (N).

The pull-down module 400 includes a fourth transistor T4, an eleventh transistor T11, and a ninth transistor T9, gates of the fourth transistor T4, the eleventh transistor T11, and the ninth transistor T9 are all electrically connected to the second node P, sources of the fourth transistor T4, the eleventh transistor T11, and the ninth transistor T9 are all connected to the first potential, a drain of the fourth transistor T4 is electrically connected to the output terminal g (n), a drain of the eleventh transistor T11 is electrically connected to the stage transmission terminal cs (n), and a drain of the ninth transistor T9 is electrically connected to the first node Qb.

The anti-leakage module 500 includes a twelfth transistor T12, a gate of the twelfth transistor T12 is connected to the second potential, a source is electrically connected to the first node Qb, and a drain is electrically connected to the pull-up node Qa.

The voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to a first potential; one end of the second capacitor C2 is electrically connected to the second node P, and the other end is connected to the first potential.

The working process of the GOA circuit sequentially comprises a reset stage and a normal display stage.

In the Reset phase, the Reset signal Reset provides a pulse signal of a single second potential to control the seventh transistor T7 to be turned on and make the second node P be the second potential, and the second node P controls the fourth transistor T4, the eleventh transistor T11 and the tenth transistor T10 to be turned on and make the output terminal g (n), the stage transfer terminal cs (n), the first node Qb and the pull-up node Qa be the first potential.

In the precharge sub-stage T1, the stage pass terminal CS (N-1) of the upper GOA cell or the stage pass terminal CS (N +1) of the lower GOA cell provides the second level to turn on the first transistor T1 or the second transistor T2, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged, and at the same time, the third transistor T3, the tenth transistor T10 and the fifth transistor T5 are turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential, so that the fourth transistor T4, the eleventh transistor T11 and the ninth transistor T9 are turned off.

In the output sub-phase T2, the first transistor T1 or the second transistor T2 is turned off by providing the first voltage to the stage pass terminal CS (N-1) of the upper GOA unit or the stage pass terminal CS (N +1) of the lower GOA unit, the first transistor T1 or the second transistor T2 is turned off, the third transistor T3 is turned on to keep the first node Qb at the second voltage, and the pull-up node Qa is switched from the second voltage to the bootstrap voltage, wherein the first capacitor C1 can stabilize the first node Qb; meanwhile, the nth clock signal ck (N) provides the second potential, and is output as an output terminal g (N) signal through the third transistor T3, and is output as a stage transmission terminal cs (N) signal through the tenth transistor T10.

In the pull-down sub-phase T3, the stage pass terminal CS (N-1) of the upper GOA cell or the stage pass terminal CS (N +1) of the lower GOA cell provides the second potential to turn on the first transistor T1 or the second transistor T2, the forward scan signal U2D or the reverse scan signal D2U provides the first potential to the first node Qb and the pull-up node Qa, and the N +1 clock signal CK (N +1) turns on the sixth transistor T6 to convert the second node P to the second potential and charge the second capacitor C2, and the second node P turns on the fourth transistor T4, the eleventh transistor T11 and the ninth transistor T9 to convert the output terminal g (N), the stage pass terminal CS (N), the first node Qb and the pull-up node Qa to the first potential.

It should be noted that one of the forward direction scan signal U2D and the reverse direction scan signal D2U is high, and the other is low; during forward scanning, the stage pass terminal CS (N-1) of the upper GOA unit controls the first transistor T1 to turn on, and the gate of the first transistor T1 of the first GOA unit is connected to the start signal STV (not shown in fig. 5 and 6); in the reverse scan, the stage pass terminal CS (N +1) of the lower GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the last GOA unit is connected to the start signal STV.

Fig. 5 is an ideal timing diagram of the GOA circuit according to the embodiment of the present invention, fig. 6 is a simulated timing diagram of the GOA circuit according to the embodiment of the present invention, and fig. 5 and fig. 6 correspond to the case where each transistor in the GOA circuit is an N-type thin film transistor, the first potential is the constant voltage low potential VGL, and the second potential is the constant voltage high potential VGH.

The forward scan signal U2D is a constant voltage high voltage VGH and the reverse scan signal D2U is a constant voltage low voltage VGL during forward scan, the forward scan signal U2D is a constant voltage low voltage VGL and the reverse scan signal D2U is a constant voltage high voltage VGH (not shown in fig. 5 and 6) during reverse scan, and the forward scan is taken as an example in the embodiment of the present invention.

With reference to fig. 4, 5 and 6, the working flow of the GOA circuit includes a reset phase and a normal display phase, which are described in detail below.

In the Reset stage, the Reset signal Reset controls the seventh transistor T7 to be turned on earlier than the pulse signal providing a single high potential of the other control signals, so that the second node P is at a high potential, and the second node P controls the fourth transistor T4, the eleventh transistor T11 and the tenth transistor T10 to be turned on, so that the output terminal g (n), the stage transfer terminal cs (n), the first node Qb and the pull-up node Qa are pre-pulled low, so that the initial potentials of the output terminal g (n) and the stage transfer terminal cs (n) are at the constant voltage low potential VGL. Then the Reset signal Reset is set low and the seventh transistor T7 is turned off, waiting for the normal display phase to come.

The normal display phase further includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t 3.

In the pre-charge sub-stage t 1: in forward scanning, the level transfer terminal CS (N-1) of the upper GOA unit provides a high level to turn on the first transistor T1, so that the first node Qb and the pull-up node Qa are pulled up to a constant voltage high potential VGH, at which time the first capacitor C1 is charged, and the third transistor T3, the tenth transistor T10 and the fifth transistor T5 are turned on; the fifth transistor T5 has the second node P pulled down to the constant voltage low potential VHL, thereby turning off the fourth transistor T4, the eleventh transistor T11 and the ninth transistor T9.

In the output sub-stage T2, the nth clock signal CKN is high, the third transistor T3 outputs the nth clock signal ck (N) as the output terminal g (N), and the tenth transistor T10 outputs the nth clock signal ck (N) as the stage terminal cs (N). At this time, the stage transfer terminal CS (N-1) of the upper GOA unit and the stage transfer terminal CS (N +1) of the lower GOA unit are both low, the first transistor T1 and the second transistor T2 are both turned off, the third transistor T3 is turned on, the first node Qb and the pull-up node Qa have no leakage path and thus remain high, and the pull-up node Qa is pulled higher due to the bootstrap effect and raised to a higher bootstrap potential by the constant voltage high potential VGH because the third transistor T3 and the tenth transistor T10 have parasitic capacitances and the output terminal g (N) signal and the stage transfer terminal CS (N) signal are high.

In order to prevent the high potential of the pull-up node Qa from being reversely sunk to the first node Qb when the pull-up node Qa is bootstrapped to the high potential, the anti-leakage block 500 is disposed between the first node Qb and the pull-up node Qa, the anti-leakage block 500 includes a twelfth transistor T12, a gate of the twelfth transistor T12 is connected to a constant voltage high potential VGH to keep the twelfth transistor T12 in an on state, and when the first node Qb is a constant voltage high potential VGH, the twelfth transistor T12 is equivalent to a diode which is turned on in a direction of the pull-up node Qa from the first node Qb, and prevents the potential of the pull-up node Qa from being reversely sunk to the first node Qb when the high potential of the pull-up node Qa is higher than the high potential of the first node Qb, thereby maintaining the high potential bootstrapped by the pull-up node Qa.

In the pull-down sub-stage T3, the stage transfer terminal CS (N +1) of the lower GOA unit provides a high voltage to turn on the first transistor T1 or the second transistor T2, the reverse scan signal D2U provides a low voltage to the first node Qb and the pull-up node Qa, and the N +1 th clock signal CK (N +1) provides a high voltage to turn on the sixth transistor T6 to pull up the second node P to a constant voltage high voltage VGH, at which time, the second capacitor C2 is charged, and the second node P turns on the fourth transistor T4, the eleventh transistor T11, and the ninth transistor T9, so that the output terminal g (N), the stage transfer terminal CS (N), the first node Qb, and the pull-up node Qa are pulled down to a constant voltage low voltage VGL.

Thereafter, the first capacitor C1 maintains the first node Qb and the pull-up node Qa at the constant voltage low potential VGL to keep the third transistor T3 turned off, the second capacitor C2 maintains the second node P at the constant voltage high potential VGH to keep the fourth transistor T4 turned on, and the output terminal g (n) and the stage transfer terminal cs (n) maintain the constant voltage low potential VGL.

In the GOA circuit provided in the embodiments of the present invention, the tenth transistor T10 is added in the pull-up module of each stage of the GOA unit, the eleventh transistor T11 is added in the pull-down module, and the drain of the tenth transistor T1 and the drain of the eleventh transistor T11 are both electrically connected to the stage pass terminal cs (n), because the signal load of the stage pass terminal cs (n) is very small compared to the signal of the output terminal g (n), as shown in fig. 6, although the signal of the output terminal g (n) is distorted, the output waveform of the signal of the stage pass terminal cs (n) is not distorted, so that the charging of the first node Qb and the pull-up node Qa of the next stage of the GOA unit is not affected by using the signal of the stage pass terminal cs (n) instead of the signal of the output terminal g (n) as the stage pass signal of the next stage of the GOA unit, thereby improving the stability of the cascade.

For example, after two stages of GOA units are cascaded, the original output waveforms (the waveforms of the pull-up node Qa in fig. 3) and the current output waveforms (the waveforms of the pull-up node Qa in fig. 6) of the pull-up node Qa of the next stage of GOA unit in the pre-charge sub-stage t1 and the output sub-stage t2 are compared to obtain fig. 7, that is, fig. 7 is a simulation comparison diagram of the pull-up node Qa in the GOA circuit of the prior art and the GOA circuit of the embodiment of the present invention, where in two dotted circles, a dotted curve is the original output waveform of the pull-up node Qa, and a real curve is the current output waveform of the pull-up node Qa.

As can be seen from fig. 7, the amplitudes of the current output waveforms of the pull-up node Qa in the pre-charge sub-stage t1 and the output sub-stage t2 are both higher than the original output waveform, so that the GOA circuit provided by the embodiment of the present invention can charge the first node Qb and the pull-up node Qa of the GOA unit more fully, has less distortion, and improves the stability of the cascade.

Referring to fig. 4, the GOA circuit further includes an output control module 800, where the output control module 800 includes an eighth transistor T8, a gate of the eighth transistor T8 is connected to the global control signal GAS, a source is connected to the first potential, and a drain is electrically connected to the output terminal g (n).

Furthermore, the GOA circuit further comprises a touch scanning stage after the normal display stage; in the touch scanning stage, the global control signal GAS controls the output terminals g (n) of All the levels of GOA units to be converted into a first potential, which is an All gate off function, and the function is to turn off the output terminals g (n) of All the levels of GOA units when the touch scanning stage arrives, so as to stop cascading, thereby preventing interference between the scan driving signal and the touch signal.

It can be understood that, if each transistor in the GOA circuit is an N-type thin film transistor, that is, the eighth transistor T8 is an N-type thin film transistor, the global control signal GAS is at a low potential in the reset stage and the normal display stage, and at a high potential in the touch scan stage.

It should be noted that, in the reset stage and the normal display stage, each clock signal is a periodic pulse signal; in the touch scanning stage, each clock signal is a pulse signal with the frequency synchronous with that of the touch scanning signal.

It should be further noted that the GOA circuit includes a first clock signal CK1 and a second clock signal CK 2; when the nth clock signal CK (N) is the first clock signal CK1, the (N +1) th clock signal CK (N +1) is CK 2; in the reset phase and the normal display phase, the first clock signal CK1 and the second clock signal CK2 have the same period, and the pulse signal of the previous clock signal ends while the pulse signal of the next clock signal is generated.

Embodiments of the present invention further provide a display panel, where the display panel includes the GOA circuit as described above, and the display panel has the same structure and beneficial effects as the GOA circuit provided in the foregoing embodiments. Since the foregoing embodiments have described the structure and beneficial effects of the GOA circuit in detail, no further description is provided herein.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A GOA circuit comprising a plurality of cascaded GOA units, each of said GOA units comprising: the device comprises a positive and negative scanning module (100), a reset module (200), a pull-up module (300), a pull-down module (400), an anti-creeping module (500), a voltage stabilizing module (600) and a signal control module (700);

the positive and negative scanning module (100) comprises a first transistor (T1) and a second transistor (T2), wherein the gate of the first transistor (T1) is connected to the stage pass end (CS (N-1)) of the upper GOA unit, the source is connected to the positive scanning signal (U2D), and the drain is electrically connected to the first node (Qb); the gate of the second transistor (T2) is connected to the stage pass terminal (CS (N +1)) of the GOA unit of the next stage, the source is connected to the reverse scanning signal (D2U), and the drain is electrically connected to the first node (Qb);

the Reset module (200) comprises a seventh transistor (T7), wherein the gate and the source of the seventh transistor (T7) are both connected to a Reset signal (Reset), and the drain is electrically connected to the second node (P);

the pull-up module (300) comprises a third transistor (T3) and a tenth transistor (T10), wherein the gates of the third transistor (T3) and the tenth transistor (T10) are both electrically connected to a pull-up node (Qa), the sources of the third transistor (T3) and the tenth transistor (T10) are both connected to an nth clock signal (ck (N)), the drain of the third transistor (T3) is electrically connected to an output terminal (g (N)), and the drain of the tenth transistor (T10) is electrically connected to a stage transmission terminal (cs (N));

the pull-down module (400) comprises a fourth transistor (T4), an eleventh transistor (T11) and a ninth transistor (T9), wherein gates of the fourth transistor (T4), the eleventh transistor (T11) and the ninth transistor (T9) are all electrically connected to the second node (P), sources of the fourth transistor (T4), the eleventh transistor (T11) and the ninth transistor (T9) are all connected to a first potential, a drain of the fourth transistor (T4) is electrically connected to the output terminal (g (n)), a drain of the eleventh transistor (T11) is electrically connected to the stage pass terminal (cs n)), and a ninth drain of the fourth transistor (T9) is electrically connected to the first node (Qb);

the electricity leakage prevention module (500) comprises a twelfth transistor (T12), wherein the gate of the twelfth transistor (T12) is connected to a second potential, the source is electrically connected to the first node (Qb), and the drain is electrically connected to the pull-up node (Qa);

the voltage stabilizing module (600) comprises a first capacitor (C1) and a second capacitor (C2), wherein one end of the first capacitor (C1) is electrically connected with the first node (Qb), and the other end is connected with the first potential; one end of the second capacitor (C2) is electrically connected with the second node (P), and the other end is connected to the first potential;

the signal control module (700) comprises a fifth transistor (T5) and a sixth transistor (T6), wherein the gate of the fifth transistor (T5) is electrically connected to the first node (Qb), the source is connected to the first potential, and the drain is electrically connected to the second node (P); the gate of the sixth transistor (T6) is connected to the (N +1) th clock signal (CK (N +1)), the source is connected to the second potential, and the drain is electrically connected to the second node (P);

the GOA circuit is provided with a reset phase and a normal display phase;

in the Reset phase, the Reset signal (Reset) provides a pulse signal of the single second potential to control the seventh transistor (T7) to be turned on to make the second node (P) the second potential, the second node (P) controls the fourth transistor (T4), the eleventh transistor (T11) and the tenth transistor (T10) to be turned on to make the output terminal (g (n), the stage transfer terminal (cs (n)) and the first node (Qb) and the pull-up node (Qa) the first potential;

the normal display phase comprises a pre-charge sub-phase (t1), an output sub-phase (t2), and a pull-down sub-phase (t 3);

during the pre-charge sub-phase (T1), providing a second level at the pass terminal (CS (N-1)) of the upper GOA cell or the pass terminal (CS (N +1)) of the lower GOA cell turns on the first transistor (T1) or the second transistor (T2) such that the first node (Qb) and the pull-up node (Qa) are converted to a second potential and the first capacitor (C1) is charged, while turning on the third transistor (T3), the tenth transistor (T10), and the fifth transistor (T5); the fifth transistor (T5) is turned on to convert the second node (P) to the first potential, so that the fourth transistor (T4), the eleventh transistor (T11) and the ninth transistor (T9) are turned off;

at the output sub-stage (T2), providing a first level at the pass terminal (CS (N-1)) of the upper GOA cell and the pass terminal (CS (N +1)) of the lower GOA cell to turn off the first transistor (T1) and the second transistor (T2), turn off the first transistor (T1) and the second transistor (T2), turn on the third transistor (T3) to keep the first node (Qb) at the second potential, and switch the pull-up node (Qa) from the second potential to a bootstrap potential; meanwhile, the nth clock signal (ck (N)) provides the second potential, and is output as the output terminal (g (N)) signal through the third transistor (T3) and the stage transfer terminal (cs (N)) signal through the tenth transistor (T10);

in the pull-down sub-stage (T3), the stage pass terminal (CS (N-1)) of the upper GOA cell or the stage pass terminal (CS (N +1)) of the lower GOA cell provides a second potential to turn on the first transistor (T1) or the second transistor (T2), the forward scan signal (U2D) or the reverse scan signal (D2U) provides a first potential to the first node (Qb) and the pull-up node (Qa), and the (N +1) th clock signal (CK (N +1)) turns on the sixth transistor (T6) to convert the second node (P) to a second potential and the second capacitor (C2) is charged, the second node (P) turns on the fourth transistor (T4), the eleventh transistor (T11), and the ninth transistor (T9) to convert the output terminal (g (n)), the stage transfer terminal (cs (n)), the first node (Qb), and the pull-up node (Qa) into a first potential;

thereafter, the first capacitor (C1) maintains the first node (Qb) and the pull-up node (Qa) at a first potential to keep the third transistor (T3) turned off, the second capacitor (C2) maintains the second node (P) at a second potential to keep the fourth transistor (T4) turned on, and the output terminal (g (n)) and the stage transfer terminal (cs (n)) maintain the first potential.

2. The GOA circuit of claim 1, wherein one of the forward direction scan signal (U2D) and the reverse direction scan signal (D2U) is high and the other is low;

the stage pass terminal (CS (N-1)) of the upper GOA unit controls the first transistor (T1) to be turned on during forward scanning, and the gate of the first transistor (T1) of the first GOA unit is connected with a starting Signal (STV);

during the backward scan, the stage pass terminal (CS (N +1)) of the lower GOA unit controls the second transistor (T2) to be turned on, and the gate of the second transistor (T2) of the last GOA unit is connected to the start Signal (STV).

3. The GOA circuit of claim 1, wherein each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential (VGL), and the second potential is a constant voltage high potential (VGH);

in the Reset phase, the Reset signal (Reset) provides a single high-level pulse signal to make the second node (P) high, and the first node (Qb), the pull-up node (Qa), the forward scan signal (U2D), the reverse scan signal (D2U), the nth clock signal (CK (N)), the N +1 th clock signal (CK (N +1)), the output terminal (g (N)), the stage pass terminal (CS (N)) and the stage pass terminal (CS (N-1)) of the upper GOA unit and the lower GOA unit are all low;

in the pre-charge sub-stage (t1) of the normal display stage, the forward scan signal (U2D) is a constant voltage high potential (VGH) and the reverse scan signal (D2U) is a constant voltage low potential (VGL) during forward scan, the forward scan signal (U2D) is a constant voltage low potential (VGL) and the reverse scan signal (D2U) is a constant voltage high potential (VGH) during reverse scan, the second node (P), the Nth clock signal (CK (N)), the (N +1) th clock signal (CK (N +1)), the output terminal (G (N)), the stage pass terminal (CS (N)) and the stage pass terminal (CS (N +1)) of the lower GOA unit are all low-level, a level pass terminal (CS (N-1)), the first node (Qb) and the pull-up node (Qa) of the upper GOA unit are all high potential;

in the output sub-stage (t2) of the normal display stage, the second node (P), the N +1 th clock signal (CK (N +1)), the stage transfer terminal (CS (N-1)) of the upper GOA unit, and the stage transfer terminal (CS (N +1)) of the lower GOA unit are all low potentials, the first node (Qb), the pull-up node (Qa), the nth clock signal (CK (N)), the output terminal (g (N)), and the stage transfer terminal (CS (N)) are all high potentials, and the pull-up node (Qa) is raised to the bootstrap potential by the constant high potential (VGH);

in the pull-down sub-stage (t3) of the normal display stage, the first node (Qb), the pull-up node (Qa), the nth clock signal (CK (N)), the output terminal (g (N)), the stage transfer terminal (CS (N)) and the stage transfer terminal (CS (N-1)) of the upper GOA unit are all low potentials, and the second node (P), the N +1 th clock signal (CK (N +1)) and the stage transfer terminal (CS (N +1)) of the lower GOA unit are all high potentials.

4. A GOA circuit in accordance with claim 1, further comprising an output control module (800), said output control module (800) comprising an eighth transistor (T8), said eighth transistor (T8) having a gate connected to a global control signal (GAS), a source connected to said first potential, and a drain electrically connected to said output (g (n)).

5. The GOA circuit of claim 4, wherein the GOA circuit further comprises a touch scan stage after the normal display stage;

in the touch scanning stage, the global control signal (GAS) controls the output terminals (g (n)) of all the levels of the GOA units to be converted into a first potential.

6. The GOA circuit of claim 5, wherein each transistor in the GOA circuit is an N-type thin film transistor, and wherein the global control signal (GAS) is at a low potential in the reset stage and the normal display stage and at a high potential in the touch scan stage.

7. The GOA circuit of claim 5, wherein each clock signal is a periodic pulse signal during the reset phase and the normal display phase; in the touch scanning stage, each clock signal is a pulse signal with the frequency synchronous with that of the touch scanning signal.

8. The GOA circuit of claim 7, wherein the GOA circuit comprises a first clock signal (CK1) and a second clock signal (CK 2); when the nth clock signal (CK (N)) is the first clock signal (CK1), the (N +1) th clock signal (CK (N +1)) is (CK 2); in the reset phase and the normal display phase, the first clock signal (CK1) and the second clock signal (CK2) have the same period, and a pulse signal of a previous clock signal ends while a pulse signal of a next clock signal is generated.

9. A display panel comprising a GOA circuit according to any one of claims 1-8.