CN114204797A - Continuous mode bridgeless power factor correction control circuit - Google Patents

Continuous mode bridgeless power factor correction control circuit Download PDF

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Publication number
CN114204797A
CN114204797A CN202111530874.4A CN202111530874A CN114204797A CN 114204797 A CN114204797 A CN 114204797A CN 202111530874 A CN202111530874 A CN 202111530874A CN 114204797 A CN114204797 A CN 114204797A
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gate
signal
input
switching tube
resistor
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CN114204797B (en
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毛昭祺
王纪周
柯乃泉
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Hangzhou Upowertek Power Supply Co ltd
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Hangzhou Upowertek Power Supply Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4216—Arrangements for improving power factor of AC input operating from a three-phase input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention relates to a bridge-free power factor correction control circuit in a continuous mode, which comprises an input side power grid, an inductor, a first switch tube, a second switch tube, a first diode, a second diode, a first filter capacitor, an integral capacitor, a third filter capacitor, a first resistor, a second resistor, a mirror current source and a control circuit, wherein the input side power grid is connected with the inductor; the first switch tube and the second switch tube are conducted complementarily; an auxiliary winding of the inductor is connected with the integrating capacitor, the mirror current source and the first resistor to form a first loop; the control circuit is respectively connected with the input side power grid, the first loop, the first switch tube, the second resistor and the third filter capacitor, so that the input current of the input side power grid is changed along with the voltage of the input side power grid, and the power factor correction function is realized. The method and the device have the advantages of reducing the sampling difficulty of the circuit, being simple in circuit implementation and low in cost.

Description

Continuous mode bridgeless power factor correction control circuit
Technical Field
The invention relates to the technical field of circuits, in particular to a continuous mode bridgeless power factor correction control circuit.
Background
In order to improve the conversion efficiency, the bridgeless PFC circuit has been designed and is becoming a hot point of research. Compared with the traditional PFC circuit, the bridgeless PFC circuit omits a rectifier bridge at the front end, reduces the on-state loss of a diode and improves the conversion efficiency. Fig. 1 is a schematic circuit diagram of a conventional bridgeless PFC circuit, which is provided with two switching tubes S1 and S2 and two freewheeling diodes D1 and D2, and controls the current of an inductor L1 to make the waveform of the input current of the bridgeless PFC circuit follow the waveform of the input voltage, thereby achieving the purpose of power factor correction.
However, such a bridgeless PFC circuit has problems in that: when the circuit works in a constant-frequency continuous mode PFC, not only an inductive current signal needs to be isolated and sampled, but also a differential sampling circuit needs to be isolated, for example, a Hall element or a sampling control circuit comprising an isolated power supply and isolated signal transmission module is adopted, so that the circuit is complex to realize and high in cost.
In summary, a continuous mode bridgeless power factor correction control circuit capable of significantly reducing circuit implementation difficulty and reducing cost is needed.
Disclosure of Invention
The present invention addresses the above-identified problems in the prior art by providing a continuous mode bridgeless power factor correction control circuit.
In order to realize the purpose of the invention, the invention adopts the following technical scheme: a continuous mode bridgeless power factor correction control circuit comprises an input side power grid, an inductor, a first switch tube, a second switch tube, a first diode, a second diode, a first filter capacitor, an integral capacitor, a third filter capacitor, a first resistor, a second resistor, a mirror current source and a control circuit; the first switch tube and the second switch tube are conducted in a complementary mode; the auxiliary winding of the inductor is connected with the integrating capacitor, the mirror current source and the first resistor to form a first loop;
when the voltage of the input side power grid is in a positive half cycle, the second switching tube is used as a main switching tube, and the first switching tube is used as a follow current tube; if the second switching tube is conducted, current flows through the main winding of the inductor, the second switching tube and the second diode from the L end of the input side power grid in sequence and then returns to the N end of the input side power grid; if the second switching tube is turned off, current sequentially flows through the main winding of the inductor, the first switching tube or the body diode of the first switching tube, the third filter capacitor, the second resistor and the second diode from the L end of the input side power grid and then returns to the N end of the input side power grid;
when the voltage of the input side power grid is in a negative half cycle, the first switching tube is used as a switching tube, and the second switching tube is used as a follow current tube; if the first switch tube is conducted, current flows through the first diode, the first switch tube and the main winding of the first inductor from the N end of the input side power grid in sequence and then returns to the L end of the input side power grid; if the first switch tube is turned off, current flows through the first diode, the third filter capacitor, the second resistor, the second switch tube or the body diode of the second switch tube and the main winding of the inductor from the N end of the input side power grid in sequence and then returns to the L end of the input side power grid;
the control circuit is respectively connected with the input side power grid, the first loop, the first switch tube, the second resistor and the third filter capacitor, so that the input current of the input side power grid is changed along with the voltage of the input side power grid, and a power factor correction function is realized;
the circuit operates in a fixed frequency continuous mode.
The working principle and the beneficial effects are as follows: 1. compared with the prior art, this application can come voltage-controlled mirror current source through the auxiliary winding of inductance to this can be with integral capacitance's integral signal characterization for inductive current, so as to regard as control circuit's sampling signal, thereby greatly make things convenient for control circuit to control each switch tube and realize the power factor correction, and this scheme can greatly be convenient for keep apart sampling current moreover, need keep apart differential sampling circuit than prior art, and the circuit is simpler, realizes the degree of difficulty lower, and the cost is lower.
Further, in the first loop, a first end of the auxiliary winding of the inductor is connected to a first end of the first resistor and a first end of the integrating capacitor, a second end of the auxiliary winding of the inductor is connected to the mirror current source, the mirror current source is connected to a second end of the first resistor and a second end of the integrating capacitor, so that the variation of the voltage of the integrating capacitor in unit time can reflect the current of the real-time inductor in real time, and the control circuit collects the current and controls the on-off of each switching tube according to the current to realize the power factor correction function.
Furthermore, the control circuit comprises an operational amplifier, a divider, an absolute value taking circuit, an adder, a correction compensation circuit, a second comparator, an RS trigger, a driving gating circuit, a first comparator and a NOT gate;
the inverting end of the operational amplifier is connected with the voltage signal of the third filter capacitor, the non-inverting end of the operational amplifier is connected with the reference voltage signal, and the output end of the operational amplifier is connected with the input end of the divider;
the other input end of the divider is connected with the output end of the absolute value taking circuit, and the output end of the divider is connected with the input end of the adder;
the voltage signal of the integrating capacitor is input to the input end of the absolute value taking circuit, and the absolute value is taken and then output to the divider;
the other input end of the adder is connected with the output end of the correction compensation circuit, and the output end of the adder is connected with the inverting end of the second comparator;
the input end of the correction compensation circuit is connected with the voltage signal of the second resistor and is also respectively connected with the first comparator and the output end of the NOT gate, and the output end of the correction compensation circuit outputs the corrected voltage signal to the adder;
the non-inverting end of the second comparator is connected with the periodic sawtooth wave, and the output end of the second comparator is connected with the input end of the RS trigger;
two output ends of the RS trigger are both connected with the driving gating circuit;
the input end of the driving gating circuit is also connected with the output end of the NOT gate and the output end of the first comparator, and the output ends of the driving gating circuit are respectively connected with the first switching tube and the second switching tube;
and the non-inverting end of the first comparator is connected to the voltage difference value between the voltage of the L end and the voltage of the N end of the input side power grid, and the inverting end of the first comparator is grounded.
Furthermore, a reference voltage signal is accessed to the non-inverting terminal of the operational amplifier, and the amplitude of the periodic sawtooth wave is accessed to the non-inverting terminal of the second comparator.
Furthermore, the driving gating circuit comprises a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate and a second OR gate;
the input end of the first AND gate is respectively connected with a GON signal of the RS trigger and an output signal of the NOT gate, and the output end of the first AND gate is connected with the input end of the first OR gate;
the input end of the second AND gate is respectively connected with the NGON signal of the RS trigger and the output signal of the first comparator, and the output end of the second AND gate is connected with the other input end of the first OR gate;
the output end of the first OR gate is connected with the first switch tube;
the input end of the third AND gate is respectively connected with the output signal of the first comparator and the GON signal of the RS trigger, and the output end of the third AND gate is connected with the input end of the second OR gate;
the input end of the fourth AND gate is respectively connected with the NGON signal of the RS trigger and the output signal of the NOT gate, and the output end of the fourth AND gate is connected with the other input end of the second OR gate;
and the output end of the second OR gate is connected with the second switch tube.
Further, when the input side power grid is located in the positive half cycle, the output signal of the first comparator is at a high level, the output signal of the not gate is at a low level, the third and gate outputs a GON signal, the fourth and gate outputs a low level signal, the second or gate outputs a GON signal to the second switching tube, the second and gate outputs an NGON signal, the first and gate outputs a low level signal, and the first or gate outputs an NGON signal to the first switching tube.
Further, when the input side power grid is located in the negative half cycle, the output signal of the first comparator is at a low level, the output signal of the not gate is at a high level, the third and gate outputs a low level signal, the fourth and gate outputs an NGON signal, the second or gate outputs an NGON signal to the second switching tube, the first and gate outputs a GON signal, the second and gate outputs a low level signal, and the first or gate outputs a GON signal to the first switching tube.
Furthermore, the correction compensation circuit comprises a fourth resistor, a fifth resistor, a fourth switching tube, a fifth switching tube, a sixth switching tube, a subtractor and a PI integrator;
the first end of the fourth resistor is connected with the second resistor, and the second end of the fourth resistor is connected with the in-phase end of the subtracter and the first end of the fifth switching tube;
the first end of the fifth resistor is connected with the second resistor, and the second end of the fifth resistor is connected with the inverting end of the subtracter and the first end of the fourth switching tube;
the second end of the fourth switching tube is grounded, and the third end of the fourth switching tube is connected to an output signal of the first comparator;
the second end of the fifth switching tube is grounded, and the third end of the fifth switching tube is connected to an output signal of the NOT gate;
the output end of the subtracter is connected with the input end of the PI integrator;
the output end of the PI integrator is connected with the first end of the sixth switching tube;
and the second end of the sixth switching tube is connected with the input end of the adder, and the third end of the sixth switching tube is connected with the output signal of the first comparator.
Further, when the input side power grid is located in a positive half cycle, the fourth switching tube and the sixth switching tube are connected, the fifth switching tube is disconnected, the inverting end of the subtracter is grounded, and the output end of the subtracter outputs signals to the input end of the adder through the PI integrator.
Further, when the input side power grid is located in the negative half cycle, the fourth switching tube and the sixth switching tube are cut off, the fifth switching tube is connected, the same-phase end of the subtracter is grounded, the sixth switching tube is disconnected, and an input signal of the input end of the adder is zero.
Drawings
Fig. 1 is a prior art bridgeless PFC circuit;
FIG. 2 is a circuit diagram of the present invention;
FIG. 3 is a schematic diagram of the control circuit of the present invention;
FIG. 4 is a schematic diagram of the drive gate circuit of FIG. 3;
FIG. 5 is a schematic diagram of the connection of the correction compensation circuit of FIG. 4 to a portion of the circuit of FIG. 3;
FIG. 6 is a graph of the waveforms of the various components of the circuit over time when the input side grid is in the positive half cycle;
fig. 7 is a graph of the waveforms of the components of the circuit over time when the input side grid is in the negative half cycle.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, the above terms should not be construed as limiting the present invention.
As shown in fig. 1, the existing bridgeless PFC circuit includes an input-side power grid LN, an inductor L1, a first switch tube S1, a second switch tube S2, a first diode D1, a second diode D2, a first filter capacitor CX1, a second filter capacitor Co, and an isolation differential current sampling circuit, and omits a control circuit, and the specific connection manner is as shown in fig. 1.
The present application therefore proposes the following embodiments to solve the above problems:
in the case of the example 1, the following examples are given,
as shown in fig. 2, the continuous mode bridgeless power factor correction control circuit includes an input side grid LN, an inductor L1, a first switch tube S1, a second switch tube S2, a first diode D1, a second diode D2, a first filter capacitor CX1, an integrating capacitor C1, a third filter capacitor Co, a first resistor Rcs1, a second resistor Rcs2, a Mirror current source Mirror, and a control circuit, wherein the circuit operates in a constant frequency continuous mode (CCM).
In the present embodiment, the first switch tube S1 and the second switch tube S2 are power switch tubes and are conducted complementarily. An auxiliary winding of the inductor L1 is connected to the integrating capacitor C1, the Mirror current source Mirror and the second resistor Rcs2 to form a first loop.
Specifically, in the first loop, a first end of an auxiliary winding of the inductor L1 is connected to a first end of a first resistor Rcs1 and a first end of an integrating capacitor C1, a second end of the auxiliary winding of the inductor L1 is connected to a Mirror current source Mirror, and the Mirror current source Mirror is connected to a second end of the first resistor Rcs1 and a second end of the integrating capacitor C1, so that the variation of the voltage of the integrating capacitor C1 in unit time can reflect the current of the real-time inductor L1 in real time, and the control circuit collects current to control the on-off of each switching tube according to the current to realize the power factor correction function.
When the input-side grid LN voltage is in the positive half-cycle, i.e. VL>VNThe second switch tube S2 is the main switch tube, the first switchTube S1 acts as a flow-through tube.
When the second switch tube S2 is turned on, current flows from the terminal L through the inductor L1, the second switch tube S2, and the second diode D2 back to the terminal N;
when the second switch tube S2 is turned off, a current flows from the L terminal through the inductor L1, the first switch tube S1 or the body diode of the first switch tube S1, the third filter capacitor Co, the second resistor Rcs2, and the second diode D2 to the N terminal.
When the input-side grid LN voltage is in the negative half cycle, i.e. VL<VNThe first switch tube S1 is the main switch tube, and the second switch tube S2 is the follow current tube.
When the first switch tube S1 is turned on, current flows from the N terminal through the first diode D1, the first switch tube S1, and the inductor L1 returns to the L terminal;
when the first switch tube S1 is turned off, current flows from the N terminal through the first diode D1, the third filter capacitor Co, the second resistor Rcs2, the second switch tube S2 or the body diode of the second switch tube S2, and the inductor L1 returns to the L terminal.
Let the voltage across the main winding of the inductor L1 be VLLxAccording to the following formula:
VLLxΔ T — L1 Δ I, where Δ T is a time variation and Δ I is a current variation, and the ratio of the Mirror current source Mirror in this application is 1: 1, which can be derived from the circuit relationship, whose output current ImirComprises the following steps:
Imir＝VLLxv (n × Rcs 1); wherein, Rcs1 is the resistance value of the first resistor Rcs1, n is the turn ratio of the main winding and the auxiliary winding of the inductor L1, and the output current ImirWhen the integrating capacitor C1 is charged and discharged, the voltage variation of the integrating capacitor C1 in Δ T time is:
Figure BDA0003411458610000081
where n is the turn ratio of the main winding and the auxiliary winding of the inductor L1, and the resistance value of the first resistor Rcs1 and the capacitance of the integrating capacitor C1 are both constants, so Δ Vcs can reflect the current variation of the PFC inductor L1. Vcs may reflect the current of inductor L1 in real time if the initial amount of capacitance of integrating capacitor C1 is ignored or deemed zero. Vcs may be used as the inductor L1 current signal for power factor correction control for continuous mode PFC.
In the case of the example 2, the following examples are given,
as shown in fig. 3, the control circuit includes a third resistor Rfb, a first comparator Comp1, a second comparator Comp2, an operational amplifier Op1, a first capacitor Cfb, a not gate NON1, an absolute value taking circuit, a divider, an adder, an RS flip-flop RS1, a driving gating circuit, and a correction compensation circuit;
the inverting terminal of the operational amplifier Op1 is connected to the voltage signal Vo of the third filter capacitor Co, and the non-inverting terminal is connected to the reference voltage signal VrefThe output end of the divider is connected with the input end of the divider;
the other input end of the divider is connected with the output end of the absolute value taking circuit, and the output end of the divider is connected with the input end of the adder;
the voltage signal Vcs of the integrating capacitor C1 is input to the input end of the absolute value taking circuit, and is output to the divider after the absolute value is taken;
the other input end of the adder is connected with the output end of the correction compensation circuit to obtain the corrected and compensated Vc signal, and the output end of the adder is connected with the inverting end of the second comparator Comp2 to output the Vp signal;
the input end of the correction compensation circuit is connected with a voltage signal V of a second resistor Rcs2cs2The outputs of the first comparator Comp1 and NON1 are connected to obtain PLNSum of signals NLNThe output end of the signal output device outputs the corrected Vc signal to the adder;
the non-inverting terminal of the second comparator Comp2 is connected to the periodic sawtooth wave Vct, and the output terminal is connected to the R terminal of the RS flip-flop RS1, wherein the reference voltage signal VrefThe amplitude of the periodic sawtooth wave Vct is shown, wherein the periodic sawtooth wave Vct is from a common triangular wave generator with reset on the market;
two output terminals (G terminal and)
Figure BDA0003411458610000105
End) are allA driving gating circuit is connected, wherein the G end outputs GON signals,
Figure BDA0003411458610000104
the end outputs an NGON signal, the end S is connected with a Tset signal, the Tset signal is a periodic signal and corresponds to a Vct signal, and the Tset signal is generated when the switching period is finished so as to start a new switching period;
the input end of the driving gating circuit is also connected with the output end of the NON1 and the output end of the first comparator Comp1, and is respectively connected with the GON signal, the NGON signal and the P signalLNSignal and NLNThe output end of the signal output end is respectively connected with the first switch tube S1 and the second switch tube S2, and a Vgs1 signal and a Vgs2 signal are output;
the non-inverting terminal of the first comparator Comp1 is connected to the voltage difference between the L terminal and the N terminal of the input side grid LN, the inverting terminal is grounded, and the output terminal is PLNA signal;
according to the control circuit in FIG. 3, according to the formula Vin*Don＝(Vo-Vin)*DoffIt can be shown that D is the time when the circuit is operating continuouslyon+ D off1, then Doff＝Vin/Vo(ii) a Wherein, VinRepresented as a sine wave of the input-side grid LN, DonIndicating the on-duty of the main switching tube, DoffIndicating the on-duty of the follow current tube, VoRepresents the voltage of the third filter capacitor Co;
whereas according to figures 3 and 6 and 7,
Figure BDA0003411458610000101
wherein VrefAmplitude of periodic sawtooth wave Vct, VcompIs the output signal of the operational amplifier Op 1.
Thus continuing to derive:
Figure BDA0003411458610000102
then the input current IinComprises the following steps:
Figure BDA0003411458610000103
wherein, VinIs a sine wave of the input-side grid LN, IL1_avgIs the average current of an inductor L1, n is the turn ratio of a main winding and an auxiliary winding of the inductor L1, Rcs1 is the resistance value of a first resistor Rcs1, C1 is the capacitance of an integrating capacitor, Vcs is a signal obtained by sampling a sampling resistor Rcs1, and V is the average current of the inductor L1CompThe signal is the output signal, V, of the operational amplifier Op1CompThe signal varies with load and its value is basically stable in power frequency period, so that the input current Iin(equal to average current of inductor) follows input side grid LN voltage VinAnd further realize the power factor correction function.
In the case of the example 3, the following examples are given,
as shown in fig. 4, the driving gate circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first OR gate OR1, AND a second OR gate OR 2;
the input end of the first AND gate AND1 is respectively connected to the GON signal of the RS flip-flop RS1 AND the output signal of the not gate NON1, AND the output end of the first AND gate AND1 is connected to the input end of the first OR gate OR 1;
the input end of the second AND gate AND2 is respectively connected to the NGON signal of the RS flip-flop RS1 AND the output signal of the first comparator Comp1, AND the output end of the second AND gate AND2 is connected to the other input end of the first OR gate OR 1;
the output end of the first OR gate OR1 is connected with a first switch tube S1;
the input end of the third AND gate AND3 is respectively connected to the output signal of the first comparator Comp1 AND the GON signal of the RS flip-flop RS1, AND the output end of the third AND gate AND3 is connected to the input end of the second OR gate OR 2;
the input end of the fourth AND gate AND4 is respectively connected to the NGON signal of the RS flip-flop RS1 AND the output signal of the not gate NON1, AND the output end of the fourth AND gate AND4 is connected to the other input end of the second OR gate OR 2;
the output end of the second OR gate OR2 is connected with the second switch tube S2;
the control logic is as follows:
when the input side isWhen the grid LN is in the positive half-cycle, when VL>VNWhen, VLN>0, output signal P of the first comparator Comp1LNAt high level, the output signal N of NON1LNIs low. Third AND gate AND3 output GONSignal, fourth AND gate AND4 outputs low level signal, second OR gate OR2 outputs GONThe signal to Vgs2, second switch tube S2. Second AND gate AND2 output NGONThe first AND gate AND1 outputs a low level signal. The first OR gate OR1 outputs NGONThe signal is to Vgs1, i.e. the first switch tube S1.
When the input-side network LN is in the negative half-cycle, when VL<VNWhen, VLN<0, output signal P of the first comparator Comp1LNAt low level, the output signal N of NON1LNIs high. The third AND gate AND3 outputs a low level signal, AND the fourth AND gate AND4 outputs NGONSignal, second OR gate OR2 output NGONThe signal to Vgs2, second switch tube S2. First AND gate AND1 output GONSignal, second AND gate AND2 outputs low level signal, first OR gate OR1 outputs GONThe signal is to Vgs1, i.e. the first switch tube S1.
Corresponding to V when the input side network LN is in the positive half cycleL>VNVgs1 is connected to NGONSignal, Vgs2 connection GONA signal; when the input-side grid LN is at the negative half cycle, VL<VNVgs1 connection GONSignal, Vgs2 is connected to NGONA signal.
In the case of the example 4, the following examples are given,
referring to fig. 5, the correction compensation circuit includes a fourth resistor R1, a fifth resistor R2, a fourth switch tube S4, a fifth switch tube S5, a sixth switch tube S6, a subtractor and a PI integrator;
a first end of the fourth resistor R1 is connected to the second resistor Rcs2, and a second end is connected to the non-inverting end of the subtractor and the first end of the fifth switching tube S5;
a first end of the fifth resistor R2 is connected with the second resistor Rcs2, and a second end is connected with the inverting end of the subtracter and the first end of the fourth switching tube S4;
second of fourth switch tube S4The end is grounded, and the third end is connected to the output signal P of the first comparator Comp1LN；
The second end of the fifth switch tube S5 is grounded, and the third end is connected with the output signal N of the NON1LN；
The output end of the subtracter is connected with the input end of the PI integrator;
the output end of the PI integrator is connected with the first end of a sixth switching tube S6 and outputs a Vc signal;
the second terminal of the sixth switching tube S6 is connected to the input terminal of the adder, and the third terminal is connected to the output signal P of the first comparator Comp1LN。
The control logic is as follows:
a second resistor Rcs2 samples the current during freewheeling, V when the input-side grid LN is in the positive half-cycleL>VNThe fourth switching tube S4 and the sixth switching tube S6 are switched on, the fifth switching tube S5 is switched off, and the in-phase end of the subtracter is connected with Vcs2The output end of the subtracter outputs signals to the input end of the adder through the PI integrator;
when the input-side grid LN is in the negative half-cycle, VL<VNThe fourth switch tube S4 and the sixth switch tube S6 are cut off, the fifth switch tube S5 is conducted, the in-phase end of the subtracter is grounded, and the reverse-phase end of the subtracter is connected with Vcs2The sixth switching tube S6 is turned off, and the input signal at the input end of the adder is zero.
Therefore, the non-inverting terminal of the subtracter represents the positive half-cycle average follow current of the input side power grid LN, and the inverting terminal of the subtracter represents the negative half-cycle average follow current of the input side power grid LN.
If the average follow current of the positive half cycle is larger than that of the negative half cycle, the subtracter outputs a positive value, and outputs a positive value signal to the input end of the adder through the PI integrator, so that the Vgs2 driving duty ratio of the positive half cycle is reduced, the average follow current of the positive half cycle is further reduced, negative feedback is formed, and the average follow current of the positive half cycle and the negative half cycle is equal.
If the average follow current of the positive half cycle is smaller than that of the negative half cycle, the subtracter outputs a negative value, and outputs a negative value signal to the input end of the adder through the PI integrator, so that the driving duty ratio of Vgs2 of the positive half cycle is increased, the average current of the positive half cycle is increased, negative feedback is formed, and the average follow current of the positive half cycle and the negative half cycle is equal.
Therefore, the negative feedback introduced by the correction compensation circuit can counteract the problem of asymmetry of the initial value of the integrating capacitor C1 or the linearity of the Mirror current source Miror, so that the power factor correction effect of the circuit is further improved.
In summary, in the present application, the auxiliary winding voltage-controlled Mirror current source Mirror of the inductor L1 forms an integrated signal on the capacitance integration C1 to characterize the current of the inductor L1, so as to form an isolation current sampling scheme.
The present invention is not described in detail in the prior art, and therefore, the present invention is not described in detail.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Although the use of the term in the present text is used more often, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.
The present invention is not limited to the above-mentioned preferred embodiments, and any other products in various forms can be obtained by anyone in the light of the present invention, but any changes in the shape or structure thereof, which have the same or similar technical solutions as the present application, fall within the protection scope of the present invention.

Claims (10)

1. A continuous mode bridgeless power factor correction control circuit is characterized by comprising an input side power grid, an inductor, a first switch tube, a second switch tube, a first diode, a second diode, a first filter capacitor, an integrating capacitor, a third filter capacitor, a first resistor, a second resistor, a mirror current source and a control circuit; the first switch tube and the second switch tube are conducted in a complementary mode; the auxiliary winding of the inductor is connected with the integrating capacitor, the mirror current source and the first resistor to form a first loop;
when the voltage of the input side power grid is in a positive half cycle, the second switching tube is used as a main switching tube, and the first switching tube is used as a follow current tube; if the second switching tube is conducted, current flows through the main winding of the inductor, the second switching tube and the second diode from the L end of the input side power grid in sequence and then returns to the N end of the input side power grid; if the second switching tube is turned off, current sequentially flows through the main winding of the inductor, the first switching tube or the body diode of the first switching tube, the third filter capacitor, the second resistor and the second diode from the L end of the input side power grid and then returns to the N end of the input side power grid;
when the voltage of the input side power grid is in a negative half cycle, the first switching tube is used as a switching tube, and the second switching tube is used as a follow current tube; if the first switch tube is conducted, current flows through the first diode, the first switch tube and the main winding of the first inductor from the N end of the input side power grid in sequence and then returns to the L end of the input side power grid; if the first switch tube is turned off, current flows through the first diode, the third filter capacitor, the second resistor, the second switch tube or the body diode of the second switch tube and the main winding of the inductor from the N end of the input side power grid in sequence and then returns to the L end of the input side power grid;
the control circuit is respectively connected with the input side power grid, the first loop, the first switch tube, the second resistor and the third filter capacitor, so that the input current of the input side power grid is changed along with the voltage of the input side power grid, and a power factor correction function is realized;
the circuit operates in a fixed frequency continuous mode.
2. The continuous-mode bridgeless power factor correction control circuit according to claim 1, wherein in the first loop, a first end of an auxiliary winding of the inductor is connected to a first end of the first resistor and a first end of the integrating capacitor, respectively, a second end of the auxiliary winding of the inductor is connected to the mirror current source, and the mirror current source is connected to a second end of the first resistor and a second end of the integrating capacitor, respectively, so that a variation of a voltage of the integrating capacitor in unit time can reflect a real-time current of the inductor in real time, and the control circuit collects and controls on and off of each switching tube according to the current to realize a power factor correction function.
3. The continuous mode bridgeless power factor correction control circuit of claim 1 or2, wherein the control circuit comprises an operational amplifier, a divider, an absolute value taking circuit, an adder, a correction compensation circuit, a second comparator, an RS trigger, a driving gating circuit, a first comparator and a NOT gate;
the inverting end of the operational amplifier is connected with the voltage signal of the third filter capacitor, the non-inverting end of the operational amplifier is connected with the reference voltage signal, and the output end of the operational amplifier is connected with the input end of the divider;
the other input end of the divider is connected with the output end of the absolute value taking circuit, and the output end of the divider is connected with the input end of the adder;
the voltage signal of the integrating capacitor is input to the input end of the absolute value taking circuit, and the absolute value is taken and then output to the divider;
the other input end of the adder is connected with the output end of the correction compensation circuit, and the output end of the adder is connected with the inverting end of the second comparator;
the input end of the correction compensation circuit is connected with the voltage signal of the second resistor and is also respectively connected with the first comparator and the output end of the NOT gate, and the output end of the correction compensation circuit outputs the corrected voltage signal to the adder;
the non-inverting end of the second comparator is connected with the periodic sawtooth wave, and the output end of the second comparator is connected with the input end of the RS trigger;
two output ends of the RS trigger are both connected with the driving gating circuit;
the input end of the driving gating circuit is also connected with the output end of the NOT gate and the output end of the first comparator, and the output ends of the driving gating circuit are respectively connected with the first switching tube and the second switching tube;
and the non-inverting end of the first comparator is connected to the voltage difference value between the voltage of the L end and the voltage of the N end of the input side power grid, and the inverting end of the first comparator is grounded.
4. The continuous mode bridgeless power factor correction control circuit of claim 3, wherein a non-inverting terminal access reference voltage signal of said operational amplifier is an amplitude of an inverting terminal access periodic sawtooth wave of said second comparator.
5. The continuous mode bridgeless power factor correction control circuit of claim 3, wherein said driving gating circuit comprises a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate and a second OR gate;
the input end of the first AND gate is respectively connected with a GON signal of the RS trigger and an output signal of the NOT gate, and the output end of the first AND gate is connected with the input end of the first OR gate;
the input end of the second AND gate is respectively connected with the NGON signal of the RS trigger and the output signal of the first comparator, and the output end of the second AND gate is connected with the other input end of the first OR gate;
the output end of the first OR gate is connected with the first switch tube;
the input end of the third AND gate is respectively connected with the output signal of the first comparator and the GON signal of the RS trigger, and the output end of the third AND gate is connected with the input end of the second OR gate;
the input end of the fourth AND gate is respectively connected with the NGON signal of the RS trigger and the output signal of the NOT gate, and the output end of the fourth AND gate is connected with the other input end of the second OR gate;
and the output end of the second OR gate is connected with the second switch tube.
6. The continuous mode bridgeless power factor correction control circuit of claim 5, wherein when said input side grid is in positive half cycle, the output signal of said first comparator is high, the output signal of said not gate is low, said third and gate outputs GON signal, said fourth and gate outputs low level signal, said second or gate outputs GON signal to said second switch tube, said second and gate outputs NGON signal, said first and gate outputs low level signal, said first or gate outputs NGON signal to said first switch tube.
7. The continuous mode bridgeless power factor correction control circuit of claim 6, wherein when said input side grid is in negative half cycle, the output signal of said first comparator is low, the output signal of said not gate is high, said third and gate outputs low level signal, said fourth and gate outputs NGON signal, said second or gate outputs NGON signal to said second switch tube, said first and gate outputs GON signal, said second and gate outputs low level signal, said first or gate outputs GON signal to said first switch tube.
8. The continuous-mode bridgeless power factor correction control circuit of claim 3, wherein the correction compensation circuit comprises a fourth resistor, a fifth resistor, a fourth switch tube, a fifth switch tube, a sixth switch tube, a subtractor and a PI integrator;
the first end of the fourth resistor is connected with the second resistor, and the second end of the fourth resistor is connected with the in-phase end of the subtracter and the first end of the fifth switching tube;
the first end of the fifth resistor is connected with the second resistor, and the second end of the fifth resistor is connected with the inverting end of the subtracter and the first end of the fourth switching tube;
the second end of the fourth switching tube is grounded, and the third end of the fourth switching tube is connected to an output signal of the first comparator;
the second end of the fifth switching tube is grounded, and the third end of the fifth switching tube is connected to an output signal of the NOT gate;
the output end of the subtracter is connected with the input end of the PI integrator;
the output end of the PI integrator is connected with the first end of the sixth switching tube;
and the second end of the sixth switching tube is connected with the input end of the adder, and the third end of the sixth switching tube is connected with the output signal of the first comparator.
9. The continuous-mode bridgeless power factor correction control circuit of claim 8, wherein when said input side grid is in positive half cycle, said fourth switch tube and said sixth switch tube are turned on, said fifth switch tube is turned off, said subtractor inverting terminal is grounded, and said subtractor output terminal outputs signal to said adder input terminal through said PI integrator.
10. The continuous-mode bridgeless power factor correction control circuit of claim 9, wherein when said input side grid is in a negative half cycle, said fourth switching tube and said sixth switching tube are turned off, said fifth switching tube is turned on, said non-inverting terminal of said subtractor is grounded, said sixth switching tube is turned off, and an input signal at an input terminal of said adder is zero.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009049599A1 (en) * 2009-10-16 2011-04-21 Minebea Co., Ltd. Power factor correction circuit for use in power supply unit, has secondary winding connected with measuring resistor at which voltage signal proportional to transmitted current is tappable
CN102130581A (en) * 2011-03-30 2011-07-20 浙江工业大学 BOOST PFC circuit based on nonlinear average current control
CN102843025A (en) * 2012-08-06 2012-12-26 台达电子工业股份有限公司 Control circuit, control method, and power supply system for power factor correction (PFC) circuit
CN106602876A (en) * 2017-01-20 2017-04-26 北京集创北方科技股份有限公司 Current detection circuit and power conversion device
CN111044772A (en) * 2019-12-31 2020-04-21 广州金升阳科技有限公司 Current sampling circuit and control method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009049599A1 (en) * 2009-10-16 2011-04-21 Minebea Co., Ltd. Power factor correction circuit for use in power supply unit, has secondary winding connected with measuring resistor at which voltage signal proportional to transmitted current is tappable
CN102130581A (en) * 2011-03-30 2011-07-20 浙江工业大学 BOOST PFC circuit based on nonlinear average current control
CN102843025A (en) * 2012-08-06 2012-12-26 台达电子工业股份有限公司 Control circuit, control method, and power supply system for power factor correction (PFC) circuit
CN106602876A (en) * 2017-01-20 2017-04-26 北京集创北方科技股份有限公司 Current detection circuit and power conversion device
CN111044772A (en) * 2019-12-31 2020-04-21 广州金升阳科技有限公司 Current sampling circuit and control method

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