CN2554861Y - AC/DC switch converter with high-efficient and low no-loud loss - Google Patents
AC/DC switch converter with high-efficient and low no-loud loss Download PDFInfo
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- CN2554861Y CN2554861Y CN 01271888 CN01271888U CN2554861Y CN 2554861 Y CN2554861 Y CN 2554861Y CN 01271888 CN01271888 CN 01271888 CN 01271888 U CN01271888 U CN 01271888U CN 2554861 Y CN2554861 Y CN 2554861Y
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Abstract
The utility model relates to an A C / D C switching transducer, which comprises a rectifier circuit, a filter circuit, a B O O S T switching transducer which adopts a critical guide-communication type control, a null voltage dissymmetrical half-bridge transducer which adopts a constant frequency P W M type control, and a current detecting circuit which comprises a stagnant-return voltage comparator, etc. When the direct-current output of the null voltage dissymmetrical half-bridge transducer is lower than a certain predetermined value, the B O O S T switching transducer runs at a lower frequency discontinuous-current way, the null voltage dissymmetrical half-bridge transducer runs at a switching frequency which is much lower than the full load, and has a dead time which is much longer than the full load. In addition, the maximum duty ratio as the null voltage dissymmetrical half-bridge transducer runs actually can reach 50 percent. The utility model has the characteristics that efficiency is high, the idling input power is low, and the cost is low.
Description
Affiliated technical field
The utility model belongs to AC/DC switch converter technical field, is used for that AC power is transformed into constant DC and presses, and can be used for power supply products such as AC adapter.
Background technology
AC adapter is widely used in mobile electronic product.All the time, high power density is the major requirement of AC adapter, and this mainly realizes by the efficient that improves its AC/DC switch converter.On the other hand, the alternating current input power supplying of AC adapter usually is not cut off during owing to zero load, and the ac input power when therefore reducing its zero load helps saving electric energy.
When the power output of AC adapter during, select two-stage AC/DC switch converter usually greater than 60W.The first order is used for power factor correction (PFC), provides a galvanic current to press to the second level simultaneously.The second level is the DC to DC converter of band isolating transformer.Fig. 1 shows the circuit diagram of higher, a present widely used two-stage AC/DC switch converter of efficient.The first order is the BOOST power factor corrector, runs on critical conduction mode (Critical Conduction).The second level is no-voltage asymmetrical half-bridge (ZVS AHB) pwm converter, adopts the constant frequency PWM control mode operation.By reasonably design, its fully loaded minimum efficiency can be greater than 87% in wide region AC-input voltage (90-264V) is used.But this two-stage AC-dc converter has the following disadvantages: (1) BOOST power factor corrector is owing to adopt the critical conduction mode to control, and the switching frequency of circuit is the highest when zero load, thereby causes the no-load loss of main circuit and control circuit bigger.(2) in the control circuit of no-voltage asymmetrical half-bridge converter, duty ratio Ds is defined as the ratio of power switch Q3 ON time and switch periods Ts, and D is defined as the duty ratio of the output modulating pulse Vpwm of PWM controller.Because the PWM controller has a minimum output modulating pulse width restriction (it is delicate to be generally 0.5-0.8) usually, then duty ratio D has a minimum value restriction.And duty ratio Ds diminishes along with the decline of no-voltage asymmetrical half-bridge converter output DC stream Io thereupon.In case duty ratio Ds less than duty ratio D, will cause the vibration of circuit.In order to solve the underloading oscillation problem that the no-voltage asymmetrical half-bridge converter exists, the output at this converter increases a dummy load usually, but causes its no-load loss to increase.(3) maximum duty cycle in no-voltage asymmetrical half-bridge converter when operation is 50%, and therefore selecting maximum output duty cycle in control circuit usually is 50% PWM controller (as UC3845).Because there is discharge time in the external timing capacitors of PWM controller such as UC3845, so the maximum duty cycle of Vpwm is less than 50%.On the other hand, in order to prevent power switch pipe Q3 and Q4 conducting simultaneously, in control circuit, must increase the dead band time setting circuit.Tradition dead band time setting circuit is provided with two time of delays, can realize by simple delay circuit each time of delay, also can realize by same delay circuit two time of delays.Fig. 2 A shows the schematic diagram of traditional RCD dead band time setting circuit and power switch driver circuit, numbering 17 is represented first delay circuit among the figure, numbering 18 is represented second delay circuit, the time constant R11*C11 of resistance capacitance charge-discharge circuit and R12*C12 be respectively applied for regulate first time of delay T1d and second time of delay T2d, Fig. 2 B is the input and output voltage waveform of Fig. 2 A, wherein output waveform Vgs (Q3) and input waveform Vpwm homophase, output waveform Vgs (Q4) is anti-phase with input waveform Vpwm.From Fig. 2 B as seen, the rising edge of Vpwm and trailing edge are synchronous with the trailing edge of the trailing edge of Vgs (Q4) and Vgs (Q3) respectively, the rising edge of Vgs (Q3) postpones a Dead Time T1d than the trailing edge of Vgs (Q4), the rising edge of Vgs (Q4) postpones a Dead Time T2d than the trailing edge of Vgs (Q3), if establish T1d=T2d=Td, the duty ratio Ds=D-Td/Ts of Vgs (Q3) then, thereby the maximum duty cycle when further having reduced no-voltage asymmetrical half-bridge converter actual motion.When switching frequency was 100KHz, the maximum of duty ratio Ds was about 42%-45%.For the adjusting of satisfying VD Vo and requirement such as hold time, the stable state duty ratio of full load no-voltage asymmetrical half-bridge converter can only be arranged on about 30%-35%, cause the output inductor amount to increase and power switch pipe loss increase, reduced the efficient of converter.
Numbering 1 expression bridge rectifier among Fig. 1 and Fig. 2 A, numbering 2 expression filter circuit C1, numbering 3 expression BOOST switch converters, numbering 4 expression no-voltage asymmetrical half-bridge converters, numbering 5 expression active power factor control circuits, numbering 6 expression no-voltage asymmetrical half-bridge converter control circuits, by the PWM controller that is numbered 7, be numbered 8 power switch driver circuit, be numbered 9 dead band time setting circuit composition, letter C 2, C5, Co represents capacitor, L1, Lo represents filter inductor, D1, D2, D3, D11, D12 represents diode, Q1, Q3, Q4 represents switching power tube, and TR represents isolating transformer, and Ro represents load, Vi represents AC-input voltage, and Vo and Io represent no-voltage asymmetrical half-bridge converter (4) output dc voltage and output DC stream respectively.
Summary of the invention
Therefore the purpose of this utility model is to realize addressing the above problem with lower cost and better simply circuit, thereby the AC/DC switch converter of a kind of high efficiency, low unloaded ac input power is provided.
According to a kind of AC/DC switch converter of the present utility model, comprise a rectification circuit; A filter circuit; A BOOST switch converters; A no-voltage asymmetrical half-bridge converter; In described no-voltage asymmetrical half-bridge converter, the elementary windings in series of electric capacity and isolating transformer also forms resonant circuit with described elementary winding inductance, to realize the zero voltage switch of described no-voltage asymmetrical half-bridge converter; An active power factor control circuit, employing critical conduction mode (CriticalConduction) is controlled described BOOST switch converters, is used to improve the power factor of ac input end and regulates described BOOST switch converters output DC be depressed into a certain stationary value; A no-voltage asymmetrical half-bridge converter control circuit, adopt the constant frequency mode to control described no-voltage asymmetrical half-bridge converter, described no-voltage asymmetrical half-bridge converter control circuit is by a PWM controller, a power switch driver circuit, dead band time setting circuit is formed, and described PWM controller is that the output pulse-modulated signal of D is adjusted described no-voltage asymmetrical half-bridge converter VD to a certain stationary value in order to produce duty ratio; Described power switch driver circuit produces the opposite pulse drive signal of a pair of phase place to drive two power switchs of described no-voltage asymmetrical half-bridge converter; Described dead band time setting circuit is in order to produce certain Dead Time between described pulse drive signal, common conducting with two power switchs preventing described no-voltage asymmetrical half-bridge converter, it is characterized in that, described AC-dc converter also comprises: a current detection circuit is used to produce the voltage response signal that detects described no-voltage asymmetrical half-bridge converter output DC rheologyization; A described BOOST switch converters operational mode change-over circuit, when described no-voltage asymmetrical half-bridge converter output DC stream was lower than a certain predetermined value, described BOOST switch converters ran on the lower discontinuous current mode (DCM) of frequency; A described no-voltage asymmetrical half-bridge converter switching frequency control circuit, when described no-voltage asymmetrical half-bridge converter output DC stream was lower than a certain predetermined value, described no-voltage asymmetrical half-bridge converter ran on than fully loaded lower switching frequency.
In addition, described current detection circuit can be a hysteresis voltage comparator, and with reflecting the input signal of the output voltage error amplifier of described no-voltage asymmetrical half-bridge converter output dc voltage variation in the described PWM controller, to detect the variation of described no-voltage asymmetrical half-bridge converter output DC stream as an input of described hysteresis voltage comparator.In order to realize the zero voltage switch of described no-voltage asymmetrical half-bridge converter in underloading with when unloaded, described dead band time setting circuit can also comprise a dead-time control circuit, when described no-voltage asymmetrical half-bridge converter output DC stream was lower than a certain predetermined value, described Dead Time ran on the Dead Time of full load greater than described no-voltage asymmetrical half-bridge converter.
In order to raise the efficiency, can further comprise a dead band time setting circuit that comprises three time of delays according to a kind of AC/DC switch converter of the present utility model, the maximum duty cycle when improving described no-voltage asymmetrical half-bridge converter actual motion.
Description of drawings
Fig. 1 is two-stage AC/DC switch converter circuit figure.
Fig. 2 A is the schematic diagram of traditional RCD dead band time setting circuit and power switch driver circuit.
Fig. 2 B is the input and output voltage waveform of Fig. 2 A.
Fig. 3 is the principle sketch of explanation AC/DC switch converter embodiment of the present utility model.
Fig. 4 is the basic circuit diagram of an embodiment of BOOST switch converters operational mode change-over circuit in the key diagram 3.
Fig. 5 is the basic circuit diagram of an embodiment of no-voltage asymmetrical half-bridge converter switching frequency control circuit in the key diagram 3.
Fig. 6 is the basic circuit diagram of an embodiment of current detection circuit in the key diagram 3.
Fig. 7 A is RCD dead band time setting circuit and the power switch driver circuit basic circuit diagram that contains dead-time control circuit.
Fig. 7 B is the input and output voltage waveform of Fig. 7 A.
Fig. 8 A is the dead band time setting circuit and the power switch driver circuit theory diagram of maximum duty cycle when being used to improve no-voltage asymmetrical half-bridge converter actual motion.
Fig. 8 B is the input and output voltage waveform of Fig. 8 A.
Embodiment
Describe embodiment of the present utility model in detail below in conjunction with accompanying drawing.
Fig. 3 is the principle sketch of explanation AC/DC switch converter embodiment of the present utility model.The bridge rectifier that numbering 1 is made up of four diodes in Fig. 3, numbering 2 is filter circuit C1, numbering 3 is BOOST switch converters, numbering 4 is no-voltage asymmetrical half-bridge converters, numbering 5 is active power factor control circuits, numbering 6 is no-voltage asymmetrical half-bridge converter control circuits, by the PWM controller that is numbered 7, be numbered 8 power switch driver circuit, be numbered 9 dead band time setting circuit composition, letter C 2, C5, Co represents capacitor, L1, Lo represents filter inductor, D1, D2, D3 represents diode, Q1, Q3, Q4 represents switching power tube, and TR represents isolating transformer, and Ro represents load, Vi represents AC-input voltage, and Vo and Io represent no-voltage asymmetrical half-bridge converter (4) output dc voltage and output DC stream respectively.
BOOST switch converters (3) generally has three kinds of operational modes among Fig. 3: continuous current mode (CCM), discontinuous current mode (DCM) and critical conduction mode (Critical Conduction).The critical conduction mode obtains higher efficient owing to can realize good soft switch performance, so active power factor control circuit (5) selects the critical conduction mode to control.The bigger deficiency of BOOST switch converters (3) loss has comprised a BOOST switch converters (3) operational mode change-over circuit (11) among Fig. 3 when overcoming zero load.When BOOST switch converters (3) runs on underloading and zero load, active power factor control circuit (5) adopts the discontinuous current mode to control, and switching frequency can be reduced to below the 20KHz, thereby reduces the loss of BOOST switch converters (3) and active power factor control circuit (5).The integrated power Power Factor Controller that active power factor control circuit (5) generally can select the critical conduction mode to control, when the integrated power Power Factor Controller contains switching frequency clamp (FC) function, can utilize the switching frequency clamp function to realize the mutual conversion of critical conduction mode and discontinuous current mode easily.Fig. 4 shows the basic circuit diagram of (11) embodiment of above-mentioned two kinds of operational mode change-over circuits, FC is a switching frequency clamp end among the figure, Vr1 is a direct-flow steady voltage, Vdet is for detecting the voltage response signal of no-voltage asymmetrical half-bridge converter (4) output DC rheologyization, in order to the break-make of control switch pipe Q2.When BOOST switch converters (3) Q2 conducting when running on heavy duty, the time constant of switching frequency clamp circuit is C3*R1*R2/ (R1+R2), provide switching power tube Q1 a minimum turn-off time at the AC-input voltage instantaneous value near zero the time, be generally several delicately, be used to improve the power factor of ac input end and reduce electromagnetic interference (EMI) to tens microseconds.When BOOST switch converters (3) runs on underloading and zero load, Q2 disconnects, and the time constant of switching frequency clamp circuit is C3*R1, because R1 is much larger than R2, can make BOOST switch converters (3) run on the lower discontinuous current mode of frequency, reduce its no-load loss.Experimental results show that for wide AC-input voltage scope, VD Vdc to be the BOOST switch converters of 380V, when running on switching frequency when unloaded and being the discontinuous current mode of 20KHz, when running on the critical conduction mode, reduces its ac input end input power ratio about 0.3W.
No-voltage asymmetrical half-bridge converter (4) runs on the constant frequency PWM mode among Fig. 3, and its switching frequency is determined by PWM controller (7).It is 50% integrated PWM controller that PWM controller (7) can be selected maximum output duty cycle, and frequency of its output pulse-modulated signal Vpwm is by external timing resistance and the decision of external timing capacitor, and it is above to obtain high power density to be generally 100KHz.Reduce no-load loss simultaneously in order to solve the instability problem that no-voltage asymmetrical half-bridge converter (4) exists in underloading with when unloaded, comprised a switching frequency control circuit (12) among Fig. 3.When no-voltage asymmetrical half-bridge converter (4) ran on underloading and zero load, its switching frequency can be reduced to below the 30KHz, thereby the duty ratio of minimizing Vpwm is to keep the stable of output dc voltage Vo and to reduce its no-load loss.Fig. 5 shows the basic circuit diagram of (12) embodiment of no-voltage asymmetrical half-bridge converter switching frequency control circuit, Rt/Ct is external timing resistance and external timing capacitor input among the figure, Vr2 is a direct-flow steady voltage, Vdet is for detecting the voltage response signal of no-voltage asymmetrical half-bridge converter (4) output DC rheologyization, and R4 is greater than R5.When no-voltage asymmetrical half-bridge converter (4) when running on heavy duty, switching tube Q5 conducting, the time constant of timing circuit is C6*R4*R5/ (R4+R5); Q5 disconnects when no-voltage asymmetrical half-bridge converter (4) runs on underloading and zero load, the time constant of timing circuit is C6*R4, time constant during greater than heavy duty, thus littler duty ratio can be obtained, keep the stable of output dc voltage Vo and reduce no-load loss.
In order to obtain voltage response signal Vdet among Fig. 4 and Fig. 5, need the testing circuit of an output DC stream Io.Current transformer testing circuit or sample resistance testing circuit circuit complexity commonly used, cost is higher.The utility model proposes a simple current detection circuit, an one embodiment is shown in Fig. 6.EA is an error amplifier circuit among Fig. 6, PWM is a pulse width modulator, R6, R7 is an output dc voltage Vo sample resistance, current detection circuit is made of hysteresis voltage comparator (10), by the output voltage of error amplifier in the PWM controller (7) input signal as (10) inputs of hysteresis voltage comparator, in order to detect the variation of output DC stream Io, Vr3 is a direct-flow steady voltage, resistance R 8, R9, R10 constitutes the hysteretic characteristic of comparator, test point electric current when making test point electric current when output DC stream Io is ascending to be changed greater than descending variation of output DC stream Io, thus vibration caused when avoiding no-voltage asymmetrical half-bridge converter (4) between underloading and heavy duty, to change.
No-voltage asymmetrical half-bridge converter (4) runs on underloading and isolates the electric current of the former limit of transformer TR winding when unloaded very little, for the zero voltage switch that realizes Q3, Q4 to reduce loss, need longer Dead Time Td.Because generally by the time constant decision of resistance capacitance charge-discharge circuit in the delay circuit, the resistance value during by change underloading and zero load can change Dead Time Td to Dead Time Td easily.Fig. 7 A shows a RCD dead band time setting circuit (9) that contains dead-time control circuit (16).Its input and output voltage waveform is shown in Fig. 7 B, underloading and when unloaded switch S 1, S2 disconnect S1, S2 closure during heavy duty, thereby the Dead Time when making underloading and the Dead Time when unloaded greater than heavy duty.
No-voltage asymmetrical half-bridge converter (4) thus the too small problem that lowers efficiency of fully loaded stable state duty ratio that exists can solve by are set in the dead band time setting circuit (9) three time of delays.Fig. 8 A shows novel dead band time setting circuit and the power switch driver circuit theory diagram with three time of delays, Fig. 8 B is the input and output voltage oscillogram of Fig. 8 A, wherein delay circuit A is used to produce T1d time of delay, delay circuit B is used to produce T2d time of delay, delay circuit C is used to produce T3d time of delay, and delay circuit A, delay circuit B, delay circuit C also can merge into one or two delay circuits.As seen from the figure, T3d time of delay that increases newly is the time of the trailing edge of Vgs (Q3) than the trailing edge delay of Vpwm.By adjusting T3d, the maximum duty cycle during no-voltage asymmetrical half-bridge converter (4) operation can bring up to 50%, its fully loaded stable state duty ratio can be designed about 40%, thereby improve its efficient.
Indulge the above, the utility model provides the AC/DC switch converter of a kind of high efficiency, low no-load loss, applicable to power supply products such as AC adapter.Experimental results show that for wide AC-input voltage scope, the power output AC adapter greater than 60W, use the AC/DC switch converter that the utility model provides, can make fully loaded minimum efficiency greater than 89%, unloaded ac input end input power is less than 1W.
Claims (7)
1. the low no-load loss AC/DC switch converter of high efficiency comprises a rectification circuit (1); A filter circuit (2); A BOOST switch converters (3); A no-voltage asymmetrical half-bridge converter (4); An active power factor control circuit (5), employing critical conduction mode (Critical Conduction) is controlled BOOST switch converters (3), is used to improve the power factor of ac input end and regulates BOOST switch converters (3) output DC be depressed into a certain stationary value; A no-voltage asymmetrical half-bridge converter control circuit (6), by a PWM controller (7), a power switch driver circuit (8), a dead band time setting circuit (9) is formed, wherein PWM controller (7) is depressed into a certain stationary value in order to produce constant frequency output pulse-modulated signal adjustment no-voltage asymmetrical half-bridge converter (4) output DC, power switch driver circuit (8) produces the opposite pulse drive signal of a pair of phase place to drive two power switchs of no-voltage asymmetrical half-bridge converter (4), one of them pulse drive signal and described output pulse-modulated signal homophase, another pulse drive signal and described output pulse-modulated signal are anti-phase, dead band time setting circuit (9) comprises one or more delay circuits, the time of delay that described delay circuit produces is in order to producing certain Dead Time between described pulse drive signal, with the common conducting of two power switchs preventing described no-voltage asymmetrical half-bridge converter (4); In no-voltage asymmetrical half-bridge converter (4), the elementary windings in series of electric capacity and isolating transformer also forms resonant circuit with described elementary winding inductance, to realize the zero voltage switch of no-voltage asymmetrical half-bridge converter (4), it is characterized in that, the low no-load loss AC/DC switch converter of described high efficiency also comprises: a current detection circuit (10) is used for producing the voltage response signal that detects described no-voltage asymmetrical half-bridge converter (4) output DC rheologyization; A BOOST switch converters (3) operational mode change-over circuit (11), when described no-voltage asymmetrical half-bridge converter (4) output DC stream was lower than a certain predetermined value, BOOST switch converters (3) ran on the lower discontinuous current mode (DCM) of frequency; A no-voltage asymmetrical half-bridge converter (4) switching frequency control circuit (12), when described no-voltage asymmetrical half-bridge converter (4) output DC stream was lower than a certain predetermined value, no-voltage asymmetrical half-bridge converter (4) ran on than fully loaded lower switching frequency.
2. high efficiency according to claim 1 is hanged down no-load loss AC/DC switch converter, it is characterized in that: active power factor control circuit (5) is for containing the active power factor integrated manipulator of switching frequency clamp circuit (FC), in the external circuits of described switching frequency clamp circuit, contain BOOST switch converters operational mode change-over circuit (11), comprise: a resistance, an electric capacity, it is in parallel after a gate-controlled switch (13) is connected with another resistance with described resistance, gate-controlled switch (13) disconnects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is lower than a certain predetermined value, and connects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is higher than a certain predetermined value.
3. high efficiency according to claim 1 is hanged down no-load loss AC/DC switch converter, it is characterized in that: the oscillator of PWM controller (7) contains outer meeting resistance electric capacity timing circuit, determine the switching frequency of described output pulse-modulated signal, contain no-voltage asymmetrical half-bridge converter switching frequency control circuit (12) in the described outer meeting resistance electric capacity timing circuit, comprise: a timing resistor, a timing capacitor, it is in parallel after a gate-controlled switch (14) is connected with another timing resistor with described timing resistor, described gate-controlled switch (14) disconnects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is lower than a certain predetermined value, and connects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is higher than a certain predetermined value.
4. high efficiency according to claim 1 is hanged down no-load loss AC/DC switch converter, it is characterized in that: current detection circuit (10) is a hysteresis voltage comparator, and the input signal of the output voltage error amplifier of no-voltage asymmetrical half-bridge converter (4) output dc voltage variation as an input of hysteresis voltage comparator will be reflected in the PWM controller (7), to detect the variation of no-voltage asymmetrical half-bridge converter (4) output DC stream, another input end signal of described hysteresis voltage comparator is that a direct current burning voltage is as reference signal, the output of described hysteresis voltage comparator produces switch controlling signal and is used to control opening and turn-offing of gate-controlled switch (13) and gate-controlled switch (14), the test point electric current the when hysteretic characteristic of described hysteresis voltage comparator should make the test point electric current when described no-voltage asymmetrical half-bridge converter (4) output DC stream is ascending to be changed change greater than described no-voltage asymmetrical half-bridge converter (4) output DC stream is descending.
5. high efficiency according to claim 1 is hanged down no-load loss AC/DC switch converter, it is characterized in that: dead band time setting circuit (9) also comprises a dead-time control circuit (16), when described no-voltage asymmetrical half-bridge converter (4) output DC stream was lower than a certain predetermined value, described Dead Time ran on the described Dead Time of full load greater than no-voltage asymmetrical half-bridge converter (4).
6. high efficiency according to claim 5 is hanged down no-load loss AC/DC switch converter, it is characterized in that: dead band time setting circuit (9) contains a charging resistor, the delay circuit that charging capacitor constitutes, in order to produce described Dead Time, at described charging resistor two ends dead-time control circuit (16) in parallel, comprise: a gate-controlled switch (20) is connected with another charging resistor, gate-controlled switch (20) disconnects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is lower than a certain predetermined value, and connects when described no-voltage asymmetrical half-bridge converter (4) output DC stream is higher than a certain predetermined value.
7. high efficiency according to claim 1 is hanged down no-load loss AC/DC switch converter, it is characterized in that: the delay circuit that dead band time setting circuit (9) is comprised is provided with three time of delays, make the trailing edge of the rising edge of described output pulse-modulated signal and described another pulse drive signal synchronous, the rising edge of a described pulse drive signal postpones a Dead Time than the trailing edge of described another pulse drive signal, the trailing edge of a described pulse drive signal postpones another Dead Time than the trailing edge of described output pulse-modulated signal, and the rising edge of described another pulse drive signal is than three Dead Times of trailing edge delay control of a described pulse drive signal.
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2001
- 2001-12-05 CN CN 01271888 patent/CN2554861Y/en not_active Expired - Fee Related
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