CN101383592B - Power amplifier and method for reducing common mode noise thereof - Google Patents

Abstract

A power amplifier comprises a sum and difference modulation module, a differential delay control module and an output stage module. The sum and difference modulation module integrates and quantizes an error of the differential mode input signal and the output signal and generates a first average signal and a second average signal. The differential time delay control module further comprises a first time delay control module and a second time delay control module, wherein the first time delay control module and the second time delay control module respectively receive the first average signal and the second average signal, and carry out logic processing on the first average signal and the second average signal to generate a first signal and a second signal corresponding to the first average signal and a third signal and a fourth signal corresponding to the second average signal. The differential time delay control module determines the time delay between the first signal and the second signal and the time delay between the third signal and the fourth signal according to the first control signal and the second control signal respectively. The output stage module is controlled by the first signal, the second signal, the third signal and the fourth signal to generate an output signal to drive a load.

Description

Power amplifier and reduce the method for its common-mode noise

Technical field

The present invention relates to a kind of power amplifier, and particularly relate to the power amplifier of stagnant the fixing time (dead time) between a kind of signal of dynamic adjustment internal control commutation circuit running, to reduce the common-mode noise (common noise) of power amplifier.

Background technology

Power amplifier (power amplifier) is being played the part of considerable role in integrated circuit (IC) design, it is applied in transmitter and receiver, the genuine stereo system equipment of high pass (high-fidelity stereo equipment), microcomputer and other electronic equipment of radio communication, television broadcasting widely.The function of power amplifier is for increasing signal energy, to drive load or next stage circuit.Therefore, the quality of power amplifier can be inquired into from its power gain, and wherein power gain is the ratio of power output and input power.

Power gain is big more, represents that the amplifying power of this power amplifier is good more.When input signal hour, its power gain curve of general power amplifier all has the good linearity.And when input signal was too big, output signal was no longer amplified with linearity curve, caused power gain to descend, and this phenomenon is referred to as gain compression.Hence one can see that, and along with input signal increases, if the late more generation of gain compression represents that then the linearity of this power amplifier is preferable, it is undistorted to keep output signal.

Power amplifier is looked its application and multiple classification is arranged, and mainly contains category-A, category-B, AB class, C class and D class etc.For instance, the Audio Signal Processing in hand-hold type and wheeled apparatus, the D power-like amplifier is used widely because of the advantage with high power conversion efficiency (greater than 90%).And some D power-like amplifier can use pulse-width modulator to produce continuous impulse, and these pulse durations change with audio frequency signal amplitude, with the running of commutation circuit in the control D power-like amplifier.Yet on the product of having relatively high expectations for signal distortion, the performance of D power-like amplifier is but good so not as the AB power-like amplifier.

Therefore, in order to improve the problem of D class A amplifier A output signal nonlinear distortion, just the someone proposes a kind of long-pendingization and poor (sigma-delta) D power-like amplifier, its signal distortion can be low than the AB power-like amplifier, and the characteristics that also keep D power-like amplifier high power conversion efficiency make long-pendingization and difference D power-like amplifier that very big competitive advantage be arranged on market.Yet long-pendingization and difference D power-like amplifier have a fatal shortcoming.When input signal arrives certain degree greatly, usually be about half of reference level, the full harmonic noise of long-pendingization and difference D power-like amplifier is than (total harmonic distortion plus noise, THD+N) the rapid change of meeting is big, wherein, full harmonic noise is than the distortion harmonic power and the summation of noise and the ratio of power output that produce for equipment itself.

In association area, No. 6924757 patent case of United States Patent (USP) notification number proposes a kind of D class that is applied to amplifies, and can reduce the long-pendingization sigma-delta modulator (" sigma delta modulator with reducing switching rate for use in class D amplification ") of switching rate.This piece patent is to utilize the input signal amplitude detector to judge the amplitude size of input signal, selects the interval size of magnetic hysteresis (hysteresis) of quantizer by a question blank (look-up table).When long-pendingization sigma-delta modulator when input signal becomes big, the magnetic hysteresis interval of quantizer is just bigger, and when input signal amplitude hour, the magnetic hysteresis interval of quantizer dwindles, to improve the stability and the signal noise ratio of signal.

Because quantizer has a magnetic hysteresis interval, make the average clock of long-pendingization sigma-delta modulator to descend, with the energy loss of the commutation circuit that alleviates D power-like amplifier (output stage), and the performance of the full harmonic noise ratio of lifting output signal.But this piece patent must be detected the amplitude of input signal in advance, selects suitable magnetic hysteresis interval by question blank again, and becomes the magnetic hysteresis control signal by circuit conversion.Therefore, the complexity of circuit system and consumed power can increase greatly, realize with respect to circuit also need expending bigger cost.

Summary of the invention

Example of the present invention provides a kind of power amplifier, and it has multiple advantages such as high power conversion efficiency, the low signal distortion factor and low full harmonic noise compare.

Example of the present invention provides a kind of method that reduces the common-mode noise of power amplifier in addition, and it is by stagnant the fixing time between the signal of adjusting power amplifier internal control commutation circuit, to reduce the common-mode noise and the full harmonic noise ratio of power amplifier.

Example of the present invention proposes a kind of power amplifier.This power amplifier comprises and differs from modulation module, differential control module and output level module when stagnant.Receive differential mode input signal with the difference modulation module,, and produce first average signal and second average signal in order to the error of integration and quantification differential mode input signal and output signal.Differential when stagnant control module couple and differ from modulation module, produce first signal and secondary signal, and produce the 3rd signal and the 4th signal corresponding to second average signal corresponding to first average signal.This differential when stagnant control module comprise control module when first control module and second when stagnating stagnates.First control module when stagnating determines stagnant the fixing time between this first signal and this secondary signal according to first control signal, this first control module when stagnating comprises: first NOR gate, receive this secondary signal and this anti-phase first average signal, and produce the 5th signal; Second NOR gate receives this first average signal and this anti-phase first signal, and produces the 6th signal; First delay cell couples this first NOR gate, receives the 5th signal, and it is controlled by this first control signal and postpones the 5th signal, and produces this first signal; And second delay cell, couple this second NOR gate, receive the 6th signal, it is controlled by this first control signal and postpones the 6th signal, and produces this secondary signal.This second control module when stagnating determines stagnant the fixing time between the 3rd signal and the 4th signal according to second control signal, this second control module when stagnating comprises: the 3rd NOR gate, receive the 4th signal and this anti-phase second average signal, and produce the 7th signal; Four nor gate receives this second average signal and the 3rd anti-phase signal, and produces the 8th signal; The 3rd delay cell couples the 3rd NOR gate, receives the 7th signal, and it is controlled by this second control signal and postpones the 7th signal, and produces the 3rd signal; And the 4th delay cell, couple this four nor gate, receive the 8th signal, it is controlled by this second control signal and postpones the 8th signal, and produces the 4th signal.Output level module couples differential control module when stagnant, and it is controlled by first signal, secondary signal, the 3rd signal and the 4th signal and produces output signal to drive load.

Example of the present invention proposes a kind of method that reduces the common-mode noise of power amplifier in addition.At first, receive differential mode input signal, and with the error intergal and the quantification of differential mode input signal and output signal, to produce first average signal, second average signal.Then, produce first signal and secondary signal corresponding to first average signal through logical process, wherein, determine stagnant fixing time between first signal and secondary signal according to first control signal, this step comprises: this secondary signal and anti-phase first average signal are carried out the NOR gate computing to produce the 5th signal; This first average signal and anti-phase this first signal are carried out the NOR gate computing to produce the 6th signal; Postpone the 5th signal according to this first control signal, to produce this first signal; And postpone the 6th signal according to this first control signal, to produce this secondary signal.Then, produce the 3rd signal and the 4th signal corresponding to second average signal through logical process, wherein, according to second control signal and determine the 3rd signal and the stagnant of the 4th signal to fix time, this step comprises: the 4th signal and anti-phase this second average signal are carried out the NOR gate computing to produce the 7th signal; This second average signal and anti-phase the 3rd signal are carried out the NOR gate computing to produce the 8th signal; Postpone the 7th signal according to this second control signal, to produce the 3rd signal; And postpone the 8th signal according to this second control signal, to produce the 4th signal.And according to first signal, secondary signal, the 3rd signal and the 4th signal, control this power amplifier and produce output signal to drive load.

Example of the present invention adopts and the difference modulation module provides Circuits System one loop response, uses and improves the signal stabilization degree.And, utilize differential when stagnant control module adjust stagnant fixing time between the signal of output level module internal control commutation circuit running, use the error that is caused because of the technology variation on the balanced differential path, and reduce common-mode noise.

For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Fig. 1 shows the schematic diagram of the power amplifier of one embodiment of the invention.

Fig. 2 shows the schematic diagram of output level module among embodiment of the invention Fig. 1.

Fig. 3 shows the schematic diagram that stagnates and fix time.

Fig. 4 shows among embodiment of the invention Fig. 1 and the circuit diagram of poor modulation module.

Fig. 5 A shows among the embodiment of the invention Fig. 1 schematic diagram of first control module when stagnating.

Fig. 5 B shows the sequential chart of embodiment of the invention Fig. 5 A.

Fig. 6 shows the flow chart of method of common-mode noise of the reduction power amplifier of one embodiment of the invention.

The reference numeral explanation

Vip, Vin: differential mode input signal

Vop, Von: output signal

Vep, Ven: differential mode error signal

M1-M2: the first-the second average signal

S1-S6: first-Di six signals

CON1-CON2: the first-the second control signal

T1-T4: first-Di four transistors

REF1-REF2: the first-the second reference signal

VDD: system voltage

GND: earthed voltage

OR1-OR2: the first-the second NOR gate

INV1-INV5: first-Di five inverters

INV6-INV8: inverter

R1-R4: first-Di four resistance

SW1-SW2: first-second switch

C1-C2: the first-the second electric capacity

A, B, C, D: node

100: power amplifier

110: and the difference modulation module

111: adder unit

112: circuit filtering unit

113: quantifying unit

114: continuous time integrator

115: the discrete time integrator

116: adder

117-118: the first-the second comparator

119: logical circuit

Control module when stagnating at 120: the first

Control module when stagnating at 130: the second

121-122: the first-the second delay cell

123-124: the first-the second buffer cell

140: output level module

150: load

160: differential control module when stagnant

301: stagnate and fix time.

Embodiment

Fig. 1 shows the schematic diagram of the power amplifier of one embodiment of the invention.Please refer to Fig. 1, power amplifier 100 comprises and differs from modulation module 110, differential control module 160 and output level module 140 when stagnant.Receive differential mode input signal Vip, Vin with difference modulation module 110, and respectively with the error of differential mode input signal Vip and output signal Vop, and the error of differential mode input signal Vin and output signal Von carries out integration and quantification, to produce first and second average signal M1, M2.In present embodiment and the difference modulation module 110 comprise adder unit 111, circuit filtering unit 112 and quantifying unit 113.

Differential when stagnant control module 160 comprise control module 120,130 when first and second is stagnant.First control module 120 when stagnating couples and differs from modulation module 110, and its first average signal M1 that will receive produces the first signal S1 and secondary signal S2 after logical process.Wherein, first control module 120 when stagnating determines stagnant fixing time (deadtime) between the first signal S1 and secondary signal S2 according to the first control signal CON1.In like manner, second control module 130 when stagnating couples and differs from modulation module 110, its second average signal M2 that will receive produces the 3rd signal S3 and the 4th signal S4 after logical process, and its foundation second control signal CON2 determines stagnant the fixing time between the 3rd signal S3 and the 4th signal S4.Output level module 140 for example is a D class A amplifier A circuit, and it is controlled by first-Di, four signal S1-S4 and produces output signal Von, Vop, to drive load 150.

Narrate the circuit running of present embodiment for convenience, the structure of output level module 140 is described earlier at this.Fig. 2 shows the schematic diagram of output level module 140 among embodiment of the invention Fig. 1.Please refer to Fig. 2, output level module 140 comprises first-Di, four transistor T 1-T4, and wherein, the first and the 3rd transistor T 1, T3 are the P transistor npn npn, and the second and the 4th transistor T 2, T4 are the N transistor npn npn.The grid of the first transistor T1 receives the first signal S1, its first source/drain electrode coupling system voltage VDD, and the grid of transistor seconds T2 receives secondary signal S2, and its first and second source/drain electrode couples second source/drain electrode and the earthed voltage GND of the first transistor T1 respectively.The grid of the 3rd transistor T 3 receives the 3rd signal S3, its first source/drain electrode couples first source/drain electrode of the first transistor T1, and the grid of the 4th transistor T 4 receives the 4th signal S4, and its first and second source/drain electrode couples second source/drain electrode of the 3rd transistor T 3 and second source/drain electrode of transistor seconds T2 respectively.Second source/drain electrode of the first and the 3rd transistor T 1, T3 produces output signal Vop, Von respectively in the output level module 140, to drive load 150.

With first and second transistor T 1, T2, the two is controlled by the first signal S1 and secondary signal S2 respectively and whether determines conducting.For fear of first and second transistor T 1, T2 conducting simultaneously, cause output signal Vop instability, thereby need control stagnant the fixing time (dead time) between the first signal S1 and secondary signal S2 effectively.Fig. 3 shows the schematic diagram that stagnates and fix time.Please refer to Fig. 3, stagnate fix time 301 for first and second signal S1, S2 control respectively first and second transistor T 1, not conducting of T2 during.But in like manner also inference to the three and the 4th signal S3, S4.

In addition, output signal Vop, Von might be logic high because of the control of first-Di, four signal S1-S4 is improper simultaneously also, perhaps be logic low simultaneously, the sense of current of this expression output signal Vop, the two driving load 150 of Von is simultaneous.In brief, therefore common-mode noise also can become big, and reduces power amplifier in the performance of full harmonic noise ratio.Therefore, present embodiment is just at the stability that promotes output signal Vop, Von, and improves power amplifier and improve in the performance of full harmonic noise ratio.

Below just be described in detail and differ from the circuit running of modulation module 110.Can be considered as a kind of A/D conversion circuit with difference modulation module 110, output signal Vop, Von that it produces with reference to output level module 140 are respectively with noise remove unnecessary among input signal Vip, the Vin, complete to keep primary signal.Fig. 4 shows among embodiment of the invention Fig. 1 and the circuit diagram of poor modulation module 110.Please refer to Fig. 4 and differ from modulation module 110 and comprise adder unit 111, circuit filtering unit 112 and quantifying unit 113.Adder unit 111 calculates the difference between input signal Vip and output signal Vop respectively, and the difference between input signal Vin and output signal Von.

Circuit filtering unit 112 couples adder unit 111, and it is made up of continuous time integrator 114, discrete time integrator 115 and adder 116.Circuit filtering unit 112 provides power amplifier 100 1 loop responses, its difference between input signal Vip and output signal Vop that adds up, and the difference between input signal Vin and output signal Von, after Filtering Processing, produce differential mode error signal Vep, Ven.Quantifying unit 113 couples circuit filtering unit 112, and its level according to reference signal REF quantizes differential mode error signal Vep, Ven.

In this hypothesis quantifying unit 113 is the quantizer of three level formulas, and it comprises first and second comparator 117,118 and logical circuit 119.First and second comparator 117,118 receives differential mode error signal Vep, Ven, and first and second comparator 117,118 quantizes differential mode error signal Vep, Ven according to the level difference (REF1-REF2) of the first reference signal REF1 and the second reference signal REF2 and the level difference (REF2-REF1) of the second reference signal REF2 and the first reference signal REF1 respectively.And logical circuit 119 receives the signal of first and second comparator 117,118 outputs, produces first and second average signal M1, M2 through logical process.

For instance, the dynamic model formula of being on duty error signal Vep, Ven when system voltage VDD is interval with (REF1-REF2) level, first and second average signal M1, M2 be respectively logic high (for example: 1) and logic low (for example: 0).The dynamic model formula of being on duty error signal Vep, Ven are when (REF1-REF2) is interval with level (REF2-REF1), and first and second average signal M1, M2 (for example: 0) are all logic low.In addition, the dynamic model formula of being on duty error signal Vep, Ven between (REF2-REF1) and negative system voltage (when level VDD) is interval, first and second average signal M1, M2 be respectively logic low (for example: 0) and logic high (for example: 1).

Though the quantifying unit 113 of present embodiment so is not limited to this scope for the quantizer with three level formulas (1.5) is an example, this area has knows that usually the knowledgeable can adjust the quantization level of quantifying unit 113 according to this, for example: 1 quantifying unit.But 1.5 quantifying unit 113 can the quantifying unit than 1 provide higher signal stabilization degree in the present embodiment.

Next, be described in detail first and second control module 120,130 formed when stagnant differential stagnant the time control module 160 the circuit running.Fig. 5 A shows among the embodiment of the invention Fig. 1 schematic diagram of first control module 120 when stagnating.Please refer to Fig. 5 A, control module 120 is the example explanation when this stagnates with first, and it comprises first and second NOR gate OR1, OR2, first and second delay cell 121,122 and first and second buffer cell 123,124.The first NOR gate OR1 receives anti-phase first average signal M1 (it is that the first average signal M1 produces through inverter INV7) and secondary signal S2, and produces the 5th signal S5.The second NOR gate OR2 receives first average signal M1 (it is that the first average signal M1 produces through inverter INV7, INV8) and the anti-phase first signal S1 (it is that the first signal S1 produces through inverter INV6), and produces the 6th signal S6.

First delay cell 121 couples the first NOR gate OR1, it is controlled by the first control signal CON1 and delay control five signal S5, to produce the first signal S1, and second delay cell 122 couples the second NOR gate OR2, it also is controlled by the first control signal CON1 and delay control six signal S6, to produce secondary signal S2.In addition, first and second buffer cell 123,124 couples first and second delay cell 121,122 respectively, to improve the intensity of signal transmission.

First delay cell 121 comprises first-Di, three inverter INV1-INV3, first and second resistance R 1, R2, first switch SW 1 and first capacitor C 1.The input of the first inverter INV1 receives the 5th signal S5.First and second end of first resistance R 1 couples the output of the first inverter INV1 and first end of second resistance R 2 respectively.First and second end of first capacitor C 1 couples second end and the earthed voltage GND of second resistance R 2 respectively.Two ends of first switch SW 1 couple first and second end (parallel form) of first resistance R 1 respectively, and it is controlled by the first control signal CON1 and determines whether conducting.The input of the second inverter INV2 and output couple second end of second resistance R 2 and the input of the 3rd inverter INV3 respectively, and the output of the 3rd inverter INV3 produces the first signal S1 via first buffer cell 123.

Second delay cell 122 comprises the 4th and the 5th inverter INV4, INV5, the 3rd and the 4th resistance R 3, R4, second switch SW2 and second capacitor C 2.The input of the 4th inverter INV4 receives the 6th signal S6.First and second end of the 3rd resistance R 3 couples the output of the 4th inverter INV4 and first end of the 4th resistance R 4 respectively.First and second end of second capacitor C 2 couples second end and the earthed voltage GND of the 4th resistance R 4 respectively.Two ends of second switch SW2 couple first and second end (parallel form) of the 3rd resistance R 3 respectively, and it is controlled by the first control signal CON1 and determines whether conducting.The input of the 5th inverter INV5 couples second end of the 4th resistance R 4, and its output produces secondary signal S2 via second buffer cell 124.

Fig. 5 B shows the sequential chart of embodiment of the invention Fig. 5 A.For making the reader can know the variation of understanding between each signal, in Fig. 5 A, add ingress A, B, C, D, it is respectively the first average signal M1, the first signal S1, secondary signal S2 and output signal Vop.Please refer to Fig. 5 A and Fig. 5 B, first and second switch SW 1, SW2 are controlled by the first control signal CON1 and determine whether conducting, when first and second switch SW 1, SW2 conducting, the the 5th and the 6th signal S5, S6 time of delay can be shorter, and then it is also shorter that stagnant between first and second signal S1, S2 fixed time.Otherwise when first and second switch SW 1, not conducting of SW2, the 5th and the 6th signal S5, S6 are longer time of delay, and then it is also longer that stagnant between first and second signal S1, S2 fixed time.

Thus, 120 couples first average signal M1 of first control module when stagnating carry out producing after the logical process first and second signal S1, the S2 corresponding to the first average signal M1, and first control module 120 when stagnating can determine stagnant the fixing time between first and second signal S1, S2 according to the first control signal CON1.The structure of second control module 130 when stagnating is first control module 120 when stagnant also as among Fig. 5 A, it carries out producing after the logical process the 3rd and the 4th signal S3, S4 corresponding to the second average signal M2 to the second average signal M2, and second control module 130 when stagnating determines stagnant the fixing time between the 3rd and the 4th signal S3, S4 according to the second control signal CON2.

In addition, narration (embodiment Fig. 2) as above-mentioned output level module 140, if first-Di, four signal S1-S4 because of control the improper output signal Vop that output level module 140 is produced, when the Von logic level is identical, just probably can cause common-mode noise to become big, and then reduce the performance of full harmonic noise ratio.Therefore, at this hypothesis present embodiment first and second control signal CON1, CON2 is respectively and differ from first and second average signal M1, the M2 that modulation module 110 is produced.

Because present embodiment is for adopting 1.5 quantifying unit 113, so the collocation of first and second average signal M1, M2 has three kinds of logic states, be respectively (M1=1, M2=0), (M1=0, M2=0) and (M1=0, M2=1).Control module 120,130 independent runnings out of the ordinary when stagnant from first and second, stagnant fixing time between control module 120 was produced when first average signal M1 control first stagnated first and second signal S1, S2, and stagnant the fixing time between second average signal M2 control second control module 130 is produced when stagnating the 3rd and the 4th signal S3, S4.And for first and second when stagnant control module 120,130 operate simultaneously, the logic state difference that first and second average signal M1, M2 are arranged in pairs or groups, also can adjust the time that output signal Vop, Von change its logic level, and then improve the problem of common-mode noise in the past.

Though first and second control signal of above-mentioned hypothesis CON1, CON2 are respectively first and second average signal M1, M2, so are not limited thereto scope, the outside control signal that is provided also is provided for first and second control signal CON1, CON2.By above-mentioned several embodiment, can reduce following method flow at this.Fig. 6 shows the flow chart of method of common-mode noise of the reduction power amplifier of one embodiment of the invention.Please refer to Fig. 6, at first, receive differential mode input signal Vip, Vin (step S601).As implement the narration of illustration 4, with differential mode input signal Vip, Vin respectively with error intergal and the quantification of output signal Vop, Von, to produce first and second average signal M1, M2 (step S602).

And as implement the narration of illustration 5A, produce the first signal S1 and secondary signal S2 through logical process, and generation is corresponding to the 3rd signal S3 and the 4th signal S4 (step S603) of the second average signal M2 corresponding to the first average signal M1.Wherein, stagnant between the first signal S1 and secondary signal S2 fixed time to being controlled by the first control signal CON1, and stagnant the fixing time to being controlled by the second control signal CON2 between the 3rd signal S3 and the 4th signal S4.At last, as implementing the narration of illustration 2, according to first-Di, four signal S1-S4, control power amplifiers produces output signal Vop, Von, to drive load (step S604).

In sum, present embodiment utilization and difference modulation module 110 provide Circuits System one loop response, and between first and second signal S1, the S2 of control module 120,130 is formed when utilizing first and second stagnant when differential stagnant control module 160 adjusts output level module 140 inner control commutation circuits running and stagnant the fixing time between the 3rd and the 4th signal S3, S4, use the error that is produced because of the technology variation on the balanced differential path, and the common-mode noise of reduction power amplifier, and then the performance that improves full harmonic noise ratio.On circuit was realized, control module 120,130 was the circuit that simple logic module constituted when first and second was stagnant, and its circuit complexity and power consumption are also less.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.

Claims (16)

1. A power amplifier, characterized in that comprising: The sum-difference modulation module receives the differential mode input signal, and is used to integrate and quantize the error between the differential mode input signal and the output signal, and generate a first average signal and a second average signal; a differential time delay control module, coupled to the sum-difference modulation module, generating a first signal and a second signal corresponding to the first average signal, and generating a third signal and a fourth signal corresponding to the second average signal, The differential hysteresis control module includes: The first delay control module, the first delay control module determines the delay time between the first signal and the second signal according to the first control signal, the first delay control module includes: a first NOR gate, receiving the second signal and the inverted first average signal, and generating a fifth signal; The second NOR gate receives the first average signal and the inverted first signal, and generates a sixth signal; a first delay unit, coupled to the first NOR gate, receives the fifth signal, delays the fifth signal under the control of the first control signal, and generates the first signal; and a second delay unit, coupled to the second NOR gate, receives the sixth signal, delays the sixth signal under the control of the first control signal, and generates the second signal; and The second delay control module, the second delay control module determines the delay time between the third signal and the fourth signal according to the second control signal, the second delay control module includes: a third NOR gate, receiving the fourth signal and the inverted second average signal, and generating a seventh signal; The fourth NOR gate receives the second average signal and the inverted third signal, and generates an eighth signal; a third delay unit, coupled to the third NOR gate, receives the seventh signal, delays the seventh signal under the control of the second control signal, and generates the third signal; and a fourth delay unit, coupled to the fourth NOR gate, receives the eighth signal, delays the eighth signal under the control of the second control signal, and generates the fourth signal; and The output stage module is coupled to the differential hysteresis control module, and is controlled by the first signal, the second signal, the third signal and the fourth signal to generate the output signal to drive a load. 2. The power amplifier according to claim 1, wherein the first hysteresis control module further comprises: a first buffer unit coupled to the first delay unit; and The second buffer unit is coupled to the second delay unit. 3. The power amplifier according to claim 1, wherein the first delay unit comprises: a first inverter whose input terminal receives the fifth signal; a first resistor, the first end of which is coupled to the output end of the first inverter; a second resistor, the first end of which is coupled to the second end of the first resistor; a first capacitor, the first end of which is coupled to the second end of the second resistor, and the second end of which is coupled to ground voltage; a first switch, the two terminals of which are respectively coupled to the first terminal and the second terminal of the first resistor, and controlled by the first average signal to determine whether to conduct; a second inverter, the input end of which is coupled to the second end of the second resistor; and The input terminal of the third inverter is coupled to the output terminal of the second inverter, and the output terminal generates the first signal. 4. The power amplifier according to claim 1, wherein the second delay unit comprises: a fourth inverter, the input end of which receives the sixth signal; a third resistor, the first end of which is coupled to the output end of the fourth inverter; a fourth resistor, the first end of which is coupled to the second end of the third resistor; a second capacitor, the first end of which is coupled to the second end of the fourth resistor, and the second end of which is coupled to ground voltage; a second switch, the two terminals of which are respectively coupled to the first terminal and the second terminal of the third resistor, and are controlled by the first control signal to determine whether to conduct; and The input terminal of the fifth inverter is coupled to the second terminal of the fourth resistor; the output terminal generates the second signal. 5. The power amplifier according to claim 1, wherein the second hysteresis control module further comprises: a first buffer unit coupled to the first delay unit; and The second buffer unit is coupled to the second delay unit. 6. The power amplifier of claim 1, wherein the first delay unit comprises: a first inverter whose input terminal receives the fifth signal; a first resistor, the first end of which is coupled to the output end of the first inverter; a second resistor, the first end of which is coupled to the second end of the first resistor; a first capacitor, the first end of which is coupled to the second end of the second resistor, and the second end of which is coupled to ground voltage; a first switch, the two terminals of which are respectively coupled to the first terminal and the second terminal of the first resistor, and controlled by the second control signal to determine whether to conduct; a second inverter, the input end of which is coupled to the second end of the second resistor; and The input terminal of the third inverter is coupled to the output terminal of the second inverter, and the output terminal generates the third signal. 7. The power amplifier of claim 1, wherein the second delay unit comprises: a fourth inverter, the input end of which receives the sixth signal; a third resistor, the first end of which is coupled to the output end of the fourth inverter; a fourth resistor, the first end of which is coupled to the second end of the third resistor; a second capacitor, the first end of which is coupled to the second end of the fourth resistor, and the second end of which is coupled to ground voltage; a second switch, the two terminals of which are respectively coupled to the first terminal and the second terminal of the third resistor, and are controlled by the second control signal to determine whether to conduct; and The fifth inverter has its input terminal coupled to the second terminal of the fourth resistor, and its output terminal generates the fourth signal. 8. The power amplifier as claimed in claim 1, wherein the first control signal is the first average signal, and the second control signal is the second average signal. 9. The power amplifier as claimed in claim 1, wherein the first control signal and the second control signal are externally provided control signals. 10. The power amplifier according to claim 1, wherein the sum and difference modulation module comprises: an adding unit for calculating the difference between the differential mode input signal and the output signal; a loop filter unit, coupled to the adding unit, which accumulates the difference and generates a differential mode error signal; and The quantization unit, coupled to the integration unit, quantizes the differential mode error signal to generate the first average signal and the second average signal. 11. The power amplifier according to claim 10, wherein the quantization unit is a three-level quantizer, and the quantization unit comprises: The first comparator receives the differential mode error signal, and quantizes the differential mode error signal according to the level difference between the first reference signal and the second reference signal; The second comparator receives the differential mode error signal, and quantizes the differential mode error signal according to the level difference between the second reference signal and the first reference signal; and The logic circuit receives the signals output by the first comparator and the second comparator, and generates the first average signal and the second average signal after logic processing. 12. The power amplifier of claim 1, wherein the output stage module comprises: a first transistor, the gate of which receives the first signal, and the first source/drain of which is coupled to the system voltage; a second transistor, the gate of which receives the second signal, the first source/drain of which is coupled to the second source/drain of the first transistor, and the second source/drain of which is coupled to ground voltage; a third transistor, the gate of which receives the third signal, and the first source/drain of which is coupled to the first source/drain of the first transistor; and The fourth transistor, whose gate receives the fourth signal, whose first source/drain is coupled to the second source/drain of the third transistor, and whose second source/drain is coupled to the second source/drain; Wherein, the first transistor and the second source/drain of the third transistor generate the output signal. 13. A method for reducing common mode noise of a power amplifier, comprising: receiving a differential mode input signal; integrating and quantizing the error of the differential mode input signal and output signal to generate a first average signal and a second average signal; A first signal and a second signal corresponding to the first average signal are generated through logical processing, wherein the dead time between the first signal and the second signal is determined according to the first control signal. This step includes: performing a NOR gate operation on the second signal and the inverted first average signal to generate a fifth signal; performing a NOR gate operation on the first average signal and the inverted first signal to generate a sixth signal; delaying the fifth signal according to the first control signal to generate the first signal; and delaying the sixth signal according to the first control signal to generate the second signal; A third signal and a fourth signal corresponding to the second average signal are generated through logical processing, wherein the dead time between the third signal and the fourth signal is determined according to the second control signal. This step includes: performing a NOR gate operation on the fourth signal and the inverted second average signal to generate a seventh signal; performing a NOR gate operation on the second average signal and the inverted third signal to generate an eighth signal; delaying the seventh signal according to the second control signal to generate the third signal; and delaying the eighth signal according to the second control signal to generate the fourth signal; and According to the first signal, the second signal, the third signal and the fourth signal, the power amplifier is controlled to generate the output signal to drive a load. 14. The method for reducing common mode noise of a power amplifier as claimed in claim 13, wherein the step of generating the first average signal and the second average signal comprises: calculating the difference between the differential mode input signal and the output signal; accumulating the difference and generating a differential mode error signal; and The differential mode error signal is quantized, and the first average signal and the second average signal are generated after logic processing. 15. The method for reducing common mode noise of a power amplifier as claimed in claim 13, wherein the first control signal is the first average signal, and the second control signal is the second average signal. 16. The method for reducing common-mode noise of a power amplifier as claimed in claim 13, wherein the first control signal and the second control signal are control signals provided externally.

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