CN114203830A - FRD structure and manufacturing method and application thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000005468 ion implantation Methods 0.000 claims description 41
- 230000000670 limiting effect Effects 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 8
- 238000009825 accumulation Methods 0.000 abstract description 5
- 230000000875 corresponding effect Effects 0.000 description 25
- 230000008569 process Effects 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000012535 impurity Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000002829 reductive effect Effects 0.000 description 9
- 230000002441 reversible effect Effects 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 8
- 238000011084 recovery Methods 0.000 description 7
- -1 boron ions Chemical class 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66113—Avalanche diodes
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Abstract
The application provides an FRD structure and a manufacturing method and application thereof. The FRD structure comprises a P-well region, a plurality of P + well regions, at least one internal field oxide layer, a substrate and an external field oxide layer covering the substrate; the external field oxide layer is annularly arranged along the periphery of the substrate, the external field oxide layer surrounds to form a source region corresponding to the middle position of the substrate, the P-well region covers the substrate and is positioned in the source region, the P + well regions cover the P-well region and are embedded into the P-well region, the P + well regions are mutually spaced to form at least one discharge channel, the positions of the P-well region corresponding to the discharge channel are covered with the internal field oxide layer, and two opposite ends of the internal field oxide layer are connected with the external field oxide layer; the bleed channels are used to direct avalanche current of the FRD structure directly to the middle of the source region. The avalanche current flows more smoothly, heat accumulation can not be generated by concentrating on the edge of a chip, and therefore avalanche tolerance and reliability of the FRD structure can be effectively improved.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the technical field of power electronic devices, in particular to an FRD structure and a manufacturing method and application thereof.
[ background of the invention ]
FRD (Fast Recovery Diode) is a semiconductor Diode having advantages of good switching characteristics and short reverse Recovery time, and is mainly applied to electronic circuits such as a switching power supply, a PWM (Pulse Width Modulation) Pulse Width modulator, and a frequency converter, and is used as a high-frequency rectifier Diode, a freewheeling Diode, or a damping Diode. The internal structure of the FRD is different from that of a common PN junction diode, and the FRD belongs to a PIN junction diode, namely a base region I is added between a P-type silicon material and an N-type silicon material to form a PIN silicon chip; wherein, because the base region I is thinner, the reverse recovery charge of the FRD is smaller, the reverse recovery time is shorter, the forward voltage drop is lower, and the reverse breakdown voltage (withstand voltage) is higher.
In the related art, the FRD generally includes a low concentration P-well region and a high concentration P + well region stacked on each other to ensure ohmic contact of an anode region of the FRD. When the FRD is in reverse avalanche, avalanche current (namely hole current in avalanche) can be blocked by a P +/P-junction formed by the low-concentration P-well region and the high-concentration P + well region together, so that the avalanche current is difficult to reach the center of a chip (or the avalanche current reaching the center of the chip is very little), because the direction of an electric field in the P +/P-junction points to the low-concentration P-well region from the high-concentration P + well region, and the avalanche current is mainly hole current, so that the flow of the avalanche current from the low-concentration P-well region to the high-concentration P + well region is blocked, most of the avalanche current is reflected by the high-concentration P + well region, namely most of the avalanche current cannot pass through the P +/P-junction; at this time, avalanche current is concentrated on the edge of the chip, so that the heat dissipation area of the chip is reduced, heat accumulation and local hot spots are easy to form, and the chip is burnt in severe cases, which indicates that the avalanche tolerance of the conventional FRD is low. In order to improve the avalanche tolerance of the FRD, a technician sets a plurality of high-concentration P + well regions, and makes the plurality of high-concentration P + well regions be arranged at equal intervals and in a staggered manner, and the shape of the orthographic projection of any one high-concentration P + well region to the low-concentration P-well region is a regular hexagon, so as to improve the softness factor and the avalanche tolerance of the FRD. However, in such an FRD having a plurality of high concentration P + well regions, when avalanche is reversed, the flow of avalanche current to the center of the chip is not smooth, and therefore, the avalanche resistance of the FRD can be increased only by a small amount, so that the avalanche resistance of the FRD is still at a low level.
Therefore, there is a need for an improved structure of the FRD.
[ summary of the invention ]
The application provides an FRD structure and a manufacturing method and application thereof, aiming at solving the problem of low avalanche tolerance of the FRD in the related technology.
In order to solve the above technical problem, a first aspect of the embodiments of the present application provides an FRD structure, including a substrate and an external field oxide layer covering the substrate, where the external field oxide layer is annularly disposed along a periphery of the substrate, and the external field oxide layer surrounds a source region corresponding to a middle position of the substrate;
the FRD structure further comprises a P-well region, a plurality of P + well regions and at least one inner field oxide layer, wherein the P-well region covers the substrate and is positioned in the source region, the P + well regions cover the P-well region and are embedded into the P-well region, the P + well regions are mutually spaced to form at least one discharge channel, the inner field oxide layer covers the positions of the P-well region corresponding to the discharge channel, and two opposite ends of the inner field oxide layer are connected with the outer field oxide layer; wherein the bleed channels are configured to direct avalanche current of the FRD structure through to an intermediate location of the source region.
A second aspect of the present embodiment provides a method for manufacturing an FRD structure, which is used to manufacture the FRD structure according to the first aspect of the present embodiment; the manufacturing method of the FRD structure comprises the following steps:
forming the external field oxide layer and the internal field oxide layer on the substrate;
forming the P-well region on the substrate at the position of the source region by taking the external field oxide layer and the internal field oxide layer as masks;
and forming a plurality of P + well regions on the P-well region by taking the external field oxide layer and the internal field oxide layer as masks.
A third aspect of embodiments of the present application provides a use of the FRD structure according to the first aspect of embodiments of the present application in a switching power supply, a PWM pulse width modulator, and a frequency converter.
As can be seen from the above description, the present application has the following advantages compared with the related art:
and a plurality of P + well regions are embedded on one side of the P-well region, which is far away from the substrate, and are arranged at intervals to form at least one discharge channel for guiding avalanche current of the FRD structure to directly pass through to the middle position of the source region, and two opposite ends of the discharge channel are both connected with the external field oxide layer. In practical application, because the discharge channel is formed by a plurality of P + well regions at intervals, only a P-well region exists at the discharge channel, namely the doping concentration is low and impurity ions are few, so that after the FRD structure is turned off, the impurity scattering is small in the process that avalanche current flows to the middle position of the source region, and the avalanche current can more easily reach the middle position of the source region; and because the P + well region not only has the P + well region itself, but also has the P-well region positioned at the bottom layer, namely the P + well region has high doping concentration and more impurity ions, the impurity scattering received at the P + well region is large in the process that the avalanche current flows to the middle position of the source region after the FRD structure is turned off, so that the avalanche current is difficult to reach the middle position of the source region. Therefore, the avalanche current mainly flows to the middle position of the source region through the discharge channel in a straight-through mode (namely, no barrier), so that the flow of the avalanche current is smoother, the avalanche current is not concentrated on the edge of the chip, the heat dissipation area of the chip is increased, heat accumulation and local hot spots are not easy to form, and the avalanche tolerance and the reliability of the FRD structure can be effectively improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the drawings needed to be used in the description of the related art or the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, not all embodiments, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic cross-sectional view of a conventional FRD;
FIG. 2 is a schematic diagram of a conventional FRD from a top view;
fig. 3 is a schematic structural diagram of an FRD structure according to an embodiment of the present disclosure in a top view;
fig. 4 is a schematic cross-sectional view of an FRD structure provided in an embodiment of the present application along a direction a-a in fig. 3;
fig. 5 is a schematic diagram of avalanche current flow at a cross section cut along direction a-a in fig. 3 for an FRD structure provided by an embodiment of the present application;
fig. 6 is a schematic cross-sectional view of an FRD structure according to an embodiment of the present disclosure along the direction B-B in fig. 3;
fig. 7 is a schematic diagram of avalanche current flow at a cross section cut along the direction B-B in fig. 3 of an FRD structure provided by an embodiment of the present application;
fig. 8 is a schematic diagram illustrating the flow of avalanche current in an FRD structure provided by an embodiment of the present application;
fig. 9 is a schematic main flow chart of a manufacturing method of an FRD structure according to an embodiment of the present disclosure;
FIG. 10 is a schematic flow chart of step 901 in FIG. 9 according to an embodiment of the present application;
FIG. 11 is a schematic flow chart of step 902 of FIG. 9 according to an embodiment of the present disclosure;
fig. 12 is a schematic flowchart of step 903 in fig. 9 according to an embodiment of the present disclosure.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present application more apparent and understandable, the present application will be clearly and completely described below in conjunction with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only for explaining the present application and are not intended to limit the present application, that is, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts based on the embodiments of the present application belong to the protection scope of the present application. In addition, the technical features involved in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
In the related art, the FRD generally includes a low concentration P-well region and a high concentration P + well region stacked on each other to ensure ohmic contact of an anode region of the FRD. When the FRD is in reverse avalanche, avalanche current can be blocked by a P +/P-junction formed by the low-concentration P-well region and the high-concentration P + well region together, so that the avalanche current is difficult to reach the center of a chip (or the avalanche current reaching the center of the chip is very little), because the direction of an electric field in the P +/P-junction points to the low-concentration P-well region from the high-concentration P + well region, and the avalanche current is mainly hole current, so that the flow of the avalanche current from the low-concentration P-well region to the high-concentration P + well region is blocked, most of the avalanche current is reflected by the high-concentration P + well region, namely most of the avalanche current cannot pass through the P +/P-junction; at this time, avalanche current is concentrated on the edge of the chip, so that the heat dissipation area of the chip is reduced, heat accumulation and local hot spots are easy to form, and the chip is burnt in severe cases, which indicates that the avalanche tolerance of the conventional FRD is low. In order to improve the avalanche tolerance of the FRD, a technician sets a plurality of high-concentration P + well regions, and makes the plurality of high-concentration P + well regions be arranged at equal intervals and in a staggered manner, and the shape of the orthographic projection of any one high-concentration P + well region to the low-concentration P-well region is a regular hexagon, so as to improve the softness factor and the avalanche tolerance of the FRD. However, in such an FRD having a plurality of high concentration P + well regions, when avalanche is reversed, the flow of avalanche current to the center of the chip is not smooth, and therefore, the avalanche resistance of the FRD can be increased only by a small amount, so that the avalanche resistance of the FRD is still at a low level. To this end, embodiments of the present application provide an FRD structure that may be applied to, but not limited to, switching power supplies, PWM pulse width modulators, and frequency converters.
Prior to describing the structure of the FRD provided by the embodiments of the present application in detail, a brief understanding of the FRD is provided. Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a conventional FRD; wherein, 1 ' is cathode region metal, 2 ' is an N + substrate, 3 ' is an N-epitaxial layer, 4 ' is a low-concentration P-well region, 5 ' is a high-concentration P + well region, 6 ' is a field oxide layer, and 7 ' is anode region metal. Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of a conventional FRD in a top view; wherein 8' is the source region. As can be seen from fig. 2, the high-concentration P + well regions 5 'include a plurality of high-concentration P + well regions 5', the low-concentration P-well regions 4 'are covered by the plurality of high-concentration P + well regions 5', the plurality of high-concentration P + well regions 5 'are arranged at equal intervals and in a staggered manner, and the shape of the orthographic projection of any one high-concentration P + well region 5' to the low-concentration P-well region 4 'is a regular hexagon, at this time, the avalanche current a flowing from the left side to the middle position of the source region 8' is divided into a1、a2And a3Three branches, the avalanche current b flowing from the right to the middle of the source region 8' being divided into b1、b2And b3Three branches, of which branch a3And b3Is blocked by the high concentration P + well region 5 'and hardly reaches the middle position of the source region 8', and the branch a1、a2、b1And b2It takes many turns to reach the middle of source region 8' (i.e. the flow of branches a1, a2, b1 and b2 is not smooth), resulting in branch a1、 a2、b1And b2The FRD is damaged by avalanche breakdown before reaching the middle of the source region 8', resulting in the avalanche tolerance of the conventional FRD still being at a low level.
Referring to fig. 3 and fig. 4, fig. 3 is a schematic structural diagram of an FRD structure provided in an embodiment of the present application in a top view, and fig. 4 is a schematic cross-sectional diagram of the FRD structure provided in the embodiment of the present application along a direction a-a in fig. 2. As can be seen from fig. 3 and 4, the FRD structure provided by the embodiment of the present application includes a substrate 0 and an external field oxide layer 2 overlying the substrate 0; wherein, the external field oxide layer 2 is annularly arranged along the periphery of the substrate 0, and the external field oxide layer 2 encloses a source region 21 corresponding to the middle position of the substrate 0. Here, it should be noted that the region outside the source region 21 is referred to as a termination region, and the termination region covers at least the external field oxide layer 2.
Further, the FRD structure provided by the embodiment of the present application further includes a P-well region 3, a plurality of P + well regions 4, and at least one internal field oxide layer 10; the doping concentration of the P-well region 3 is less than that of the P + well region 4, the P-well region 3 covers the substrate 0 and is located in the source region 21, the P + well regions 4 cover the P-well region 3 and are embedded into the P-well region 3, the P + well regions 4 are spaced from each other to form at least one discharge channel 5, the positions of the P-well region 3 corresponding to the discharge channel 5 are covered with an internal field oxide layer 10, and two opposite ends of the internal field oxide layer 10 are connected with the external field oxide layer 2. Specifically, at least one of the drain channels 5 formed by the P + well regions 4 at intervals is used to guide the avalanche current of the FRD structure to pass from the termination region to the middle position of the source region 21, and since the two opposite ends of the inner field oxide layer 10 are both connected to the outer field oxide layer 2 and the inner field oxide layer 10 corresponds to the drain channel 5, the two opposite ends of the drain channel 5 are both connected to the outer field oxide layer 2.
Here, it should be noted that, the P-well region 3 and the position corresponding to the discharge channel 5 are covered with the inner field oxide layer 10, and two opposite ends of the inner field oxide layer 10 are connected to the outer field oxide layer 2, for the purpose of: as a barrier to ion implantation, or in other words, as an auxiliary structure for forming an ion implantation window, in the process of fabricating the FRD structure, thereby forming the P-well region 3 and the plurality of P + well regions 4 by ion implantation. At this moment, the photoresist formed by the photoetching process is no longer needed to be used as an auxiliary structure for forming the ion implantation window, namely, at least one step of photoetching process can be omitted in the process of manufacturing the FRD structure, so that the complexity in manufacturing the FRD structure is reduced, and the efficiency in manufacturing the FRD structure is improved.
In practical application, since the bleed channel 5 is formed by a plurality of P + well regions 4 at intervals, only the P-well region 3 exists at the bleed channel 5, that is, the doping concentration is low, and there are few impurity ions, so after the FRD structure is turned off, the impurity scattering received is small in the process that the avalanche current flows from the terminal region to the middle position of the source region 21, so that the avalanche current can more easily reach the middle position of the source region 21. Moreover, since the P + well region 4 itself and the P-well region 3 located at the bottom layer exist at the P + well region 4, that is, the P + well region 4 has high doping concentration and many impurity ions, when the FRD structure is turned off, the avalanche current flows from the terminal region to the middle position of the source region 21, the impurity scattering received at the P + well region 4 is large, so that the avalanche current is difficult to reach the middle position of the source region 21. In addition, in the process of flowing the avalanche current from the termination region to the middle position of the source region 21, the avalanche current flows in a straight-through manner, namely directly flows to the middle position of the source region 21, and the flow is extremely small due to the extremely small blockage.
It can be understood that the mutual superimposed setting of P + well region 4 and P-well region 3 can increase the FRD structure and convert the flexibility to the heavy current by the undercurrent, the size of the forward surge current of increase FRD structure, the safe workspace of increase FRD structure also can play the effect that blocks the reverse recovery current of FRD structure simultaneously to a certain extent for the softness factor of FRD structure obtains promoting. Moreover, because a plurality of P + well regions 4 are spaced from each other, the whole side of the P-well region 3 far away from the substrate 0 is not covered with the P + well region 4, that is, the area of the side of the P-well region 3 far away from the substrate 0 is larger than the sum of the areas of the sides of all the P + well regions 4 close to the substrate 0, which means that the area of the P + well region 4 can be reduced by the application, so that the reverse recovery peak current of the FRD structure is reduced, and the power consumption of the FRD structure is reduced.
Furthermore, it should be noted that since the junction depth of the P-well region 3 at B-B is deeper and the junction depth of the P-well region 3 at C-C is shallower in FIG. 3, the junction depth of the P-well region 3 at B-B is closer to the P + well region 4 (equivalent to being closer to the ion implantation window) and the junction depth of the C-C is farther from the P + well region 4 (equivalent to being farther from the ion implantation window).
Therefore, avalanche current mainly flows from the terminal region to the middle position of the source region 21 through the discharge channel 5, so that the avalanche current is not concentrated on the edge of the chip, the heat dissipation area of the chip is increased, heat accumulation and local hot spots are not easy to form, and the avalanche tolerance and reliability of the FRD structure can be effectively improved.
In one embodiment, still referring to fig. 3, the P + well regions 4 may be distributed in a rectangular array, in which case the drain channel 5 includes a first channel 51 and a second channel 52, and the inner field oxide layer 10 includes a first field oxide layer (not shown) and a second field oxide layer (not shown). Specifically, in the length direction x of the substrate 0, two rows of P + well regions 4 adjacent to each other at intervals form first channels 51, the first channels 51 extend along the length direction x of the substrate 0, and the positions of the P-well regions 3 corresponding to the first channels 51 are covered with first field oxide layers; in the width direction y of the substrate 0, second channels 52 are formed at intervals in any two adjacent rows of P + well regions 4, the second channels 52 extend along the width direction y of the substrate 0, and second field oxide layers are respectively covered on the P-well regions 3 and the positions corresponding to the second channels 52. Here, it is necessary to explain that the shape of the orthographic projection of the P + well regions 4 to the P-well regions may include, but is not limited to, a rectangle, a triangle, a circle, an ellipse, a diamond, a trapezoid, and a polygon, or may also be a combination of shapes.
To this embodiment, because each first field oxide all extends along the length direction x of substrate 0, each second field oxide all extends along the width direction y of substrate 0, and all first field oxide and the relative both ends of second field oxide all link up with external field oxide 2, so external field oxide 2, first field oxide and second field oxide can form a plurality of ion implantation windows that correspond with the formation position of a plurality of P + well regions 4 respectively through enclosing each other, at this moment, just, the photoresist that the photoetching technology formed no longer needs as the auxiliary structure that forms ion implantation window, promptly at the in-process of preparation FRD structure, can save at least one-step photoetching technology, thereby the loaded down with trivial details when having reduced preparation FRD structure, efficiency when having promoted preparation FRD structure.
For this embodiment, the portion of the P-well region 3 corresponding to the first channel 51 may be referred to as a first well region, the portion of the P-well region 3 corresponding to the second channel 52 may be referred to as a second well region, and the combination of any one P + well region 4 and the corresponding portion of the P-well region 3 may be referred to as a hybrid well region. It can be understood that the number of the first well region and the second well region is positively correlated with the row number of the mixed well region along the length direction x/width direction y of the substrate 0, and the number of the first well region and the second well region can be adjusted according to practical application scenarios, so that the forward conduction voltage drop, the reverse recovery peak current and the softness factor of the FRD structure are compromised.
For this embodiment, please combine fig. 4 and 5; fig. 5 is a schematic diagram of the flow of avalanche current at a cross section of the FRD structure cut along the direction a-a in fig. 2 according to an embodiment of the present application, wherein an arrow Q in fig. 5 represents avalanche current, the direction of the arrow Q represents the flow direction of the avalanche current, the thickness of the arrow Q represents the magnitude of the avalanche current (or the magnitude of the current density of the avalanche current), and the length of the arrow Q represents the distance of the flow of the avalanche current. As can be seen from fig. 4 and 5, when the FRD structure is turned off, in the process of flowing the avalanche current to the middle position of the source region 21, if the flow path of the avalanche current passes through the hybrid well region, the avalanche current is greatly scattered by the impurity or blocked by the hybrid well region, and the avalanche current cannot reach the middle position of the source region 21 easily.
For this embodiment, please refer to fig. 6 and 7, in which fig. 6 is a schematic cross-sectional view of the FRD structure provided in the present embodiment along the direction B-B in fig. 2, and fig. 7 is a schematic flow diagram of avalanche current at a cross-section of the FRD structure provided in the present embodiment along the direction B-B in fig. 2; in fig. 7, an arrow Q indicates avalanche current, a direction of the arrow Q indicates a flowing direction of the avalanche current, a thickness of the arrow Q indicates a magnitude of the avalanche current (or a magnitude of a current density of the avalanche current), and a length of the arrow Q indicates a distance of flowing of the avalanche current. As can be seen from fig. 6 and 7, when the FRD structure is turned off, the avalanche current flows to the middle of the source region 21, if the avalanche current does not flow through the mixed well region, the avalanche current is less scattered by the impurity, or the mixed well region has very little blocking, so that the avalanche current can more easily reach the middle of the source region 21, and it also indicates that the avalanche current mainly flows to the middle of the source region 21 through the first well region and the second well region, which is consistent with the aforementioned "avalanche current mainly flows to the middle of the source region 21 through the bleed channel 5".
In addition, referring to fig. 8, fig. 8 is a schematic diagram illustrating the flow of avalanche current of the FRD structure according to the embodiment of the present disclosure; the arrow Q indicates the avalanche current, the direction of the arrow Q indicates the flowing direction of the avalanche current, the thickness of the arrow Q indicates the magnitude of the avalanche current (or the magnitude of the current density of the avalanche current), and the length of the arrow Q indicates the distance of the flowing avalanche current. As can be seen more intuitively from fig. 8, in the FRD structure of the present embodiment, that is, "when the FRD structure is turned off, and the avalanche current flows to the middle position of the source region 21, if the flow path of the avalanche current passes through the hybrid well region, the avalanche current is scattered by a large amount of impurities, or is blocked by the hybrid well region, and the avalanche current hardly reaches the middle position of the source region 21; if the avalanche current does not flow through the hybrid well region, it is less scattered by impurities or is blocked by the hybrid well region, and the avalanche current can reach the middle position of the source region 21 more easily.
It should be understood that the above-described embodiment is only a preferred implementation of the present application, and is not the only limitation on the form of the bleed channel 5 formed by the distribution of the plurality of P + well regions 4 in the present application; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application. For example, in other embodiments, the plurality of P + well regions 4 may be distributed in a circular array, a triangular array, a polygonal array, or the like, or may be distributed along a predetermined path in an array, which is not listed here. However, regardless of the distribution form of the plurality of P + well regions 4, it is necessary to satisfy the condition that "the avalanche current can flow straight to the middle position of the source region 21 through the bleed channel 5".
In some embodiments, still referring to fig. 4 and 6, the substrate 0 may include an N + substrate 1 and an N-epitaxial layer 6, the N-epitaxial layer 6 overlying the N + substrate 1 and being located between the N + substrate 1 and the P-well region 3, the inner field oxide layer 10, and the outer field oxide layer 2.
For this embodiment, when substrate 0 comprises an N + substrate 1 and an N-epitaxial layer 6, with N-epitaxial layer 6 between N + substrate 1 and P-well region 3, inner field oxide layer 10, and outer field oxide layer 2, then P-well region 3 and outer field oxide layer 2 actually overlie N-epitaxial layer 6, and P-well region 3 is embedded in N-epitaxial layer 6.
Still referring to fig. 4 and 6, as an embodiment, the N-epitaxial layer 6 may include a first epitaxial layer 61 and a second epitaxial layer 62; the first epitaxial layer 61 and the second epitaxial layer 62 are sequentially stacked along a direction in which the N + substrate 1 points to the P-well region 3. At this point, the P-well region 3 and the external field oxide layer 2 are actually overlying the second epitaxial layer 62, and the P-well region 3 is embedded in the second epitaxial layer 62.
For this embodiment, the N-epitaxial layer 6 is a double layer structure, i.e. comprises a first epitaxial layer 61 and a second epitaxial layer 62. At this time, the N + substrate 1 is a high-concentration N-type doped region, the first epitaxial layer 61 is a lower-concentration N-type doped region, and the second epitaxial layer 62 is a lower-concentration N-type doped region, that is, the doping concentrations of the N + substrate 1, the first epitaxial layer 61, and the second epitaxial layer 62 are sequentially reduced. Accordingly, the resistivity of the first epitaxial layer 61 is smaller than that of the second epitaxial layer 62, and the thickness of the first epitaxial layer 61 is smaller than that of the second epitaxial layer 62.
Here, it is necessary to explain that the N-epitaxial layer 6 adopts a double-layer structure, and can reduce the forward conduction voltage drop of the FRD structure under the same chip area, which will be beneficial to reducing the chip area and reducing the temperature rise, and at the same time, can also improve the softness factor of the FRD structure, and enhance the reliability of the FRD structure.
It should be understood that the above embodiment is only a preferred implementation of the embodiment of the present application, and is not the only limitation on the specific composition of the N-epitaxial layer 6 in the embodiment of the present application; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
In some embodiments, still referring to fig. 4 and 6, the FRD structure provided by the embodiments of the present application may further include a plurality of field limiting rings 7, where the plurality of field limiting rings 7 are all located in the second epitaxial layer 62 and all cover the inner surface of the outer field oxide layer 2.
For this embodiment, the external field oxide layer 2 may further enclose a plurality of field limiting ring regions corresponding to the plurality of field limiting rings 7, respectively, so that the space enclosed by the external field oxide layer 2 and corresponding to the plurality of field limiting ring regions serves as an ion implantation window, that is, in the process of manufacturing the FRD structure, ion implantation is performed through the ion implantation windows to form the plurality of field limiting rings 7.
In some embodiments, still referring to fig. 4 and 6, the FRD structure provided by embodiments of the present application may further include an anode metal 9 and a cathode metal 8; the cathode metal 8 covers one side of the N + substrate 1 away from the P-well region 3, and the anode metal 9 covers one side of the external field oxide layer 2, the internal field oxide layer 10 and the P + well regions 4 away from the N + substrate 1.
In summary, the FRD structure provided in the embodiment of the present application includes a plurality of structures, such as an N + substrate 1, an N-epitaxial layer 6, an external field oxide layer 2, an internal field oxide layer 10, a P-well region 3, a plurality of P + well regions 4, a plurality of field limiting rings 7, and the like. However, it should be understood that the FRD structure provided in the embodiments of the present application may actually include other structures commonly found in FRDs in the art, such as a stop ring, a dielectric layer, a contact hole, and the like, and the embodiments of the present application are not listed here.
Referring to fig. 9, fig. 9 is a schematic main flowchart of a manufacturing method of an FRD structure according to an embodiment of the present disclosure.
As shown in fig. 9, an embodiment of the present application further provides a manufacturing method of an FRD structure, which is used for manufacturing the FRD structure provided in the embodiment of the present application; the method for manufacturing the FRD structure includes the following steps 901 to 903.
In the embodiment of the present application, it is necessary to form the external field oxide layer 2 and the internal field oxide layer 10 on the substrate 0 first. Specifically, the external field oxide layer 2 and the internal field oxide layer 10 may be formed on the substrate 0 through a field oxide process, a photolithography process, an etching process, and the like.
Further, when the substrate 0 comprises an N + substrate 1 and an N-epitaxial layer 6, the N-epitaxial layer 6 is located between the N + substrate 1 and the external field oxide layer 2, i.e. the external field oxide layer 2 actually overlies the N-epitaxial layer 6. Therefore, before step 901, the method may further include: an N-epitaxial layer 6, i.e., a first epitaxial layer 61 and a second epitaxial layer 62, is formed on an N + substrate 1. Based on this, first and second epitaxial layers 61 and 62 are formed on an N + substrate 1, and then an external field oxide layer 2 and an internal field oxide layer 10 are formed on the second epitaxial layer 62.
As an embodiment, please further refer to fig. 10, where fig. 10 is a schematic flowchart of step 901 in fig. 9 according to an embodiment of the present disclosure. As can be seen in fig. 10, step 901 may include the following steps 9011 to 9012.
And 9011, forming a field oxide layer on the second epitaxial layer.
In this embodiment, when the external field oxide layer 2 and the internal field oxide layer 10 are formed on the substrate 0, a field oxide layer needs to be formed on the second epitaxial layer 62; wherein the field oxide layer covers the entire second epitaxial layer 62.
In this embodiment, after the field oxide layer is formed on the second epitaxial layer 62, the field oxide layer needs to be etched, so as to form the external field oxide layer 2, the first field oxide layer, and the second field oxide layer; wherein, each first field oxide all extends along the length direction x of substrate 0, and each second field oxide all extends along the width direction y of substrate 0, and all first field oxide and the relative both ends of second field oxide all link up with external field oxide 2. Based on this, the external field oxide layer 2, the first field oxide layer and the second field oxide layer enclose each other to form a forming position respectively corresponding to the plurality of P + well regions 4 and a plurality of ion implantation windows respectively corresponding to the plurality of field limiting ring regions.
It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 901; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
And 902, forming a P-well region on the position of the source region on the substrate by using the external field oxide layer and the internal field oxide layer as masks.
In the embodiment of the present application, after the external field oxide layer 2 and the internal field oxide layer 10 are formed on the substrate 0, the P-well region 3 is formed on the substrate 0 at the position of the source region 21 by using the external field oxide layer 2 and the internal field oxide layer 10 as masks through an ion implantation process. It will be appreciated that when the substrate 0 comprises an N + substrate 1 and an N-epitaxial layer 6, the N-epitaxial layer 6 is located between the N + substrate 1 and the P-well region 3, i.e., the P-well region 3 is actually overlying the second epitaxial layer 62. Therefore, after a first epitaxial layer 61 and a second epitaxial layer 62 are formed on the N + substrate 1, and an external field oxide layer 2 and an internal field oxide layer 10 are formed on the second epitaxial layer 62, a P-well region 3 is formed on the second epitaxial layer 62 at the position of the source region 21; after the field oxide layer 2 is formed on the second epitaxial layer 62, the field oxide layer 2 encloses a source region 21 corresponding to the middle position of the N + substrate 1 (or the second epitaxial layer 62) and a plurality of field limiting ring regions corresponding to the plurality of field limiting rings 7, respectively.
As an embodiment, please further refer to fig. 11, where fig. 11 is a flowchart illustrating step 902 in fig. 9 according to an embodiment of the present disclosure. As can be seen in fig. 11, step 902 may include the following steps 9021 to 9022.
And 9021, performing ion implantation through the plurality of ion implantation windows by using the external field oxide layer, the first field oxide layer and the second field oxide layer as masks to form a P-well region and a plurality of field limiting rings.
In this embodiment, the external field oxide layer 2 and the internal field oxide layer 10 are formed on the second epitaxial layer 62, so that the external field oxide layer 2, the first field oxide layer and the second field oxide layer enclose each other to form forming positions respectively corresponding to the plurality of P + well regions 4, and after a plurality of ion implantation windows respectively corresponding to the plurality of field limiting ring regions, ion implantation is performed through the plurality of ion implantation windows by using the external field oxide layer 2 and the internal field oxide layer 10 as masks, thereby forming the P-well region 3 and the plurality of field limiting rings 7.
In this embodiment, after the P-well region 3 and the field limiting rings 7 are formed, the P-well region 3 and the field limiting rings 7 need to be diffused.
It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 902; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
In the embodiment of the present application, after forming the P-well region 3 on the second epitaxial layer 62 at the position of the source region 21, an ion implantation process is further required, and the outer field oxide layer 2 and the inner field oxide layer 10 are used as masks to form a plurality of P + well regions 4 on the P-well region 3, so that the plurality of P + well regions 4 are spaced from each other to form at least one discharge channel 5 for guiding the avalanche current of the FRD structure to directly reach the middle position of the source region 21.
As an embodiment, please further refer to fig. 12, where fig. 12 is a schematic flowchart of step 903 in fig. 9 according to an embodiment of the present disclosure. As can be seen in fig. 12, step 903 may include the following steps 9031 to 9032.
And 9031, performing ion implantation through the plurality of ion implantation windows by using the external field oxide layer, the first field oxide layer and the second field oxide layer as masks to form a plurality of P + well regions.
In this embodiment, after the P-well region 3 is formed at the position of the second epitaxial layer 62 in the source region 21, ion implantation is performed through a plurality of ion implantation windows by using the external field oxide layer 2, the first field oxide layer and the second field oxide layer as masks through an ion implantation process, so as to form a plurality of P + well regions 4.
In this embodiment, after the plurality of P + well regions 4 are formed, the plurality of P + well regions 4 need to be diffused.
It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 903; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
In summary, the FRD structure provided in the embodiment of the present invention is manufactured through steps 901 to 903, so that the FRD structure has the structures of the N + substrate 1, the N-epitaxial layer 6, the external field oxide layer 2, the internal field oxide layer 10, the P-well region 3, the P + well regions 4, the field limiting rings 7, and the like, and since the external field oxide layer 2 and the internal field oxide layer 10 are used as auxiliary structures for forming the ion implantation window, the photoresist formed by the photolithography process is no longer required to be used as an auxiliary structure for forming the ion implantation window, and therefore, the photolithography of the P + well region is no longer required in steps 901 to 903, that is, a photolithography process is omitted, thereby reducing complexity in manufacturing the FRD structure, and improving efficiency in manufacturing the FRD structure. However, it is also mentioned that the FRD structure provided in the embodiments of the present application further includes the anode metal 9 and the cathode metal 8, and other structures commonly found in FRDs in the art, such as the stop ring, the dielectric layer, the contact hole, and the like, and the manufacturing method of the FRD structure provided in the embodiments of the present application may include other steps besides steps 801 to 803, such as steps of manufacturing the anode metal 9 and the cathode metal 8, and steps of manufacturing the stop ring and steps of manufacturing the dielectric layer.
In order to more clearly understand the manufacturing method of the FRD structure provided in the embodiments of the present application, the manufacturing method of the FRD structure is described in detail below by using a specific example, which is as follows:
a. manufacturing an N-epitaxial layer 6: the N-epitaxial layer 6 comprises a first epitaxial layer 61 and a second epitaxial layer 62, and the first epitaxial layer 61 and the second epitaxial layer 62 are sequentially stacked along the direction of the N + substrate 1 pointing to the P-well region 3; the N + substrate 1 is a high-concentration N-type doped region, the first epitaxial layer 61 is a lower-concentration N-type doped region, and the second epitaxial layer 62 is a lower-concentration N-type doped region, namely the doping concentrations of the N + substrate 1, the first epitaxial layer 61 and the second epitaxial layer 62 are sequentially reduced; the resistivity of the first epitaxial layer 61 is less than that of the second epitaxial layer 62, and the thickness of the first epitaxial layer 61 is less than that of the second epitaxial layer 62;
b. manufacturing a field oxide layer: the field oxide layer covers one side, far away from the N + substrate 1, of the second epitaxial layer 62, the thickness of the field oxide layer is 10000-25000A, and the temperature of the field oxide process is 900-1050 ℃;
c. photoetching and etching of the source region 21 and the field limiting ring 7: etching the field oxide layer to form an external field oxide layer 2 and an internal field oxide layer 10, wherein the internal field oxide layer 10 comprises a first field oxide layer and a second field oxide layer; the external field oxide layer 2 is annularly arranged along the periphery of the second epitaxial layer 62, and the external field oxide layer 2 encloses a source region 21 corresponding to the middle position of the second epitaxial layer 62 and a plurality of field limiting ring regions respectively corresponding to the field limiting rings 7; the external field oxide layer 2, the first field oxide layer and the second field oxide layer mutually enclose to form forming positions which are respectively corresponding to the plurality of P + well regions 4 and a plurality of ion implantation windows which are respectively corresponding to the plurality of field limiting ring regions, so that ion implantation is carried out by taking the external field oxide layer 2 and the internal field oxide layer 10 as masks through the plurality of ion implantation windows;
d. ion implantation of source region 21 and field limiting ring 7: using the external field oxide layer 2 and the internal field oxide layer 10 as masks, implanting boron ions through multiple ion implantation windows to form a P-well region 3 and multiple field limiting rings 7, wherein the implantation dosage of boron ions is 1E13-1E14cm-2The implantation energy is 50-100 Kev;
e. diffusion of source region 21 and field limiting ring 7: diffusing the P-well region 3 and the field limiting rings 7 at the temperature of 1100-1175 ℃ for 90-500 min;
f. photoetching, etching, ion implantation and diffusion of the stop ring: opening a preset stop ring injection window, performing arsenic ion injection to form a stop ring, and then performing diffusion, wherein the injection dose of the arsenic ions is 1E 15-1E 16cm-2, the injection energy is 120-;
g. ion implantation and diffusion of the P + well region: using the external field oxide layer 2 and the internal field oxide layer 10 as masks, implanting boron ions through multiple ion implantation windows to form multiple P + well regions 4, and then diffusing, wherein the implantation dosage of boron ions is 1E14-1E15cm-2The implantation energy is 50-100Kev, and the diffusion temperature is 8Diffusion time is 30-100min at 50-950 ℃;
h. and (3) life control: carrying out Pt doping and annealing at the temperature of 800-1100 ℃;
i. manufacturing anode metal 9: sputtering metal, and photoetching and etching the sputtered metal to form anode metal 9, wherein the thickness of the anode metal 9 is 2-5 mu m;
j. manufacturing a passivation layer: depositing silicon nitride by a chemical vapor deposition process, and photoetching and etching the silicon nitride to form a passivation layer, wherein the thickness of the silicon nitride is 5000-10000A;
k. thinning the side of the N + substrate 1 away from the P-well region 3: carrying out ion implantation and annealing activation on one side of the N + substrate 1 away from the P-well region 3;
l, preparation of cathode metal 8: through a metal evaporation process, evaporating and depositing titanium/nickel/silver on one side of the N + substrate 1 away from the P-well region 3 to form cathode metal 8, wherein the thickness of the titanium is 500-2000A, the thickness of the nickel is 1000-4000A, and the thickness of the silver is 5000-20000A;
and m, thus finishing the manufacture of the FRD structure.
It should be noted that, the embodiments in the present disclosure are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the method class embodiment, since it is similar to the product class embodiment, the description is simple, and the relevant points can be referred to the partial description of the product class embodiment.
It is further noted that, within the context of this application, relational terms such as first and second, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An FRD structure comprises a substrate and an external field oxide layer covering the substrate, wherein the external field oxide layer is annularly arranged along the periphery of the substrate and surrounds a source region corresponding to the middle position of the substrate; the FRD structure is characterized by further comprising a P-well region, a plurality of P + well regions and at least one inner field oxide layer, wherein the P-well region covers the substrate and is positioned in the source region, the P + well regions cover the P-well region and are embedded into the P-well region, the P + well regions are mutually spaced to form at least one discharge channel, the inner field oxide layer covers the positions of the P-well region corresponding to the discharge channel, and two opposite ends of the inner field oxide layer are connected with the outer field oxide layer; wherein the bleed channels are configured to direct avalanche current of the FRD structure through to an intermediate location of the source region.
2. The FRD structure of claim 1 wherein the plurality of P + well regions are distributed in a rectangular array, the bleed channel includes a first channel and a second channel, the inner field oxide layer includes a first field oxide layer and a second field oxide layer;
in the length direction of the substrate, the first channels are formed by two rows of the P + well regions which are adjacent at intervals, the first channels extend along the length direction of the substrate, and the first field oxide layers are covered on the positions of the P-well regions corresponding to the first channels; in the width direction of the substrate, two rows of the P + well regions which are adjacent randomly form the second channels at intervals, the second channels extend along the width direction of the substrate, and the positions of the P-well regions corresponding to the second channels are covered with the second field oxide layers.
3. The FRD structure of claim 1, wherein the substrate includes an N + substrate and an N-epitaxial layer; the N-epitaxial layer covers the N + substrate and is positioned between the N + substrate and the P-well region, the internal field oxide layer and the external field oxide layer; the P-well region covers the N-epitaxial layer and is embedded into the N-epitaxial layer.
4. The FRD structure of claim 3, wherein the N-epitaxial layers include a first epitaxial layer and a second epitaxial layer, the first epitaxial layer and the second epitaxial layer being sequentially stacked along a direction of the N + substrate toward the P-well region, the P-well region overlying the second epitaxial layer and being embedded in the second epitaxial layer; the resistivity of the first epitaxial layer is smaller than that of the second epitaxial layer, and the thickness of the first epitaxial layer is smaller than that of the second epitaxial layer.
5. The FRD structure of claim 4, further comprising a plurality of field limiting rings, the plurality of field limiting rings each located within the second epitaxial layer and each overlying an inner surface of the outer field oxide layer; and the external field oxide layer also encloses a plurality of field limiting ring areas respectively corresponding to the field limiting rings.
6. A manufacturing method of an FRD structure is used for manufacturing the FRD structure; the FRD structure comprises a substrate and an external field oxide layer covering the substrate, wherein the external field oxide layer is annularly arranged along the periphery of the substrate, and the external field oxide layer surrounds a source region corresponding to the middle position of the substrate; the FRD structure is characterized by further comprising a P-well region, a plurality of P + well regions and at least one inner field oxide layer, wherein the P-well region covers the substrate and is positioned in the source region, the P + well regions cover the P-well region and are embedded into the P-well region, the P + well regions are mutually spaced to form at least one discharge channel, the inner field oxide layer covers the positions of the P-well region corresponding to the discharge channel, and two opposite ends of the inner field oxide layer are connected with the outer field oxide layer; wherein the bleed channels are used to direct avalanche current of the FRD structure through to an intermediate location of the source region;
the manufacturing method of the FRD structure comprises the following steps:
forming the external field oxide layer and the internal field oxide layer on the substrate;
forming the P-well region on the substrate at the position of the source region by taking the external field oxide layer and the internal field oxide layer as masks;
and forming a plurality of P + well regions on the P-well region by taking the external field oxide layer and the internal field oxide layer as masks.
7. The method of fabricating the FRD structure of claim 6, wherein the substrate includes an N + substrate and an N-epitaxial layer; the N-epitaxial layer covers the N + substrate and is positioned between the N + substrate and the P-well region, the internal field oxide layer and the external field oxide layer; the P-well region covers the N-epitaxial layer and is embedded into the N-epitaxial layer;
the N-epitaxial layer comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer and the second epitaxial layer are sequentially stacked along the direction of the N + substrate pointing to the P-well region, and the P-well region covers the second epitaxial layer and is embedded into the second epitaxial layer; the resistivity of the first epitaxial layer is smaller than that of the second epitaxial layer, and the thickness of the first epitaxial layer is smaller than that of the second epitaxial layer;
before the forming the external field oxide layer and the internal field oxide layer on the substrate, the method further comprises:
and forming the first epitaxial layer and the second epitaxial layer on the N + substrate.
8. The method of fabricating the FRD structure of claim 7 wherein the plurality of P + well regions are distributed in a rectangular array, the bleed channel includes a first channel and a second channel, the inner field oxide layer includes a first field oxide layer and a second field oxide layer; in the length direction of the substrate, the first channels are formed by two rows of the P + well regions which are adjacent at intervals, the first channels extend along the length direction of the substrate, and the first field oxide layers are covered on the positions of the P-well regions corresponding to the first channels; in the width direction of the substrate, the second channels are formed by two rows of the P + well regions which are adjacent at intervals, the second channels extend along the width direction of the substrate, and the second field oxide layers are covered on the positions of the P-well regions corresponding to the second channels;
the FRD structure further comprises a plurality of field limiting rings, wherein the field limiting rings are all positioned in the second epitaxial layer and cover the inner surface of the external field oxide layer; the external field oxide layer also encloses a plurality of field limiting ring areas respectively corresponding to the field limiting rings;
the forming the external field oxide layer and the internal field oxide layer on the substrate includes:
forming a field oxide layer on the second epitaxial layer;
etching the field oxide layer to form the external field oxide layer, the first field oxide layer and the second field oxide layer; the external field oxide layer, the first field oxide layer and the second field oxide layer mutually enclose to form forming positions respectively corresponding to the plurality of P + well regions and a plurality of ion implantation windows respectively corresponding to the plurality of field limiting ring regions;
forming the P-well region on the substrate at the position of the source region by using the external field oxide layer and the internal field oxide layer as masks, including:
performing ion implantation through the plurality of ion implantation windows by using the external field oxide layer, the first field oxide layer and the second field oxide layer as masks to form the P-well region and the plurality of field limiting rings;
diffusing the P-well region and the plurality of field limiting rings.
9. The method of fabricating the FRD structure of claim 8 wherein forming the plurality of P + well regions over the P-well regions using the outer field oxide layer and the inner field oxide layer as masks comprises:
performing ion implantation through the plurality of ion implantation windows by using the external field oxide layer, the first field oxide layer and the second field oxide layer as masks to form a plurality of P + well regions;
and diffusing the plurality of P + well regions.
10. Use of the FRD structure of any of claims 1-5 in switching power supplies, PWM pulse width modulators and frequency converters.
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| JP2016015392A (en) * | 2014-07-02 | 2016-01-28 | 株式会社日立製作所 | Semiconductor device and power conversion system using the same |
| CN105720107A (en) * | 2014-12-05 | 2016-06-29 | 国家电网公司 | Fast recovery diode and manufacture method for the same |
| CN105826399A (en) * | 2016-05-25 | 2016-08-03 | 上海安微电子有限公司 | Soft fast recovery diode of multi-mixture structure and preparation method thereof |
| US20210050345A1 (en) * | 2019-08-13 | 2021-02-18 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN113053993A (en) * | 2019-12-27 | 2021-06-29 | 株洲中车时代半导体有限公司 | Fast recovery diode chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2016015392A (en) * | 2014-07-02 | 2016-01-28 | 株式会社日立製作所 | Semiconductor device and power conversion system using the same |
| CN105720107A (en) * | 2014-12-05 | 2016-06-29 | 国家电网公司 | Fast recovery diode and manufacture method for the same |
| CN105826399A (en) * | 2016-05-25 | 2016-08-03 | 上海安微电子有限公司 | Soft fast recovery diode of multi-mixture structure and preparation method thereof |
| US20210050345A1 (en) * | 2019-08-13 | 2021-02-18 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN113053993A (en) * | 2019-12-27 | 2021-06-29 | 株洲中车时代半导体有限公司 | Fast recovery diode chip |
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