CN114203128A - Display panel driving method and circuit and display device - Google Patents
Display panel driving method and circuit and display device Download PDFInfo
- Publication number
- CN114203128A CN114203128A CN202111556577.7A CN202111556577A CN114203128A CN 114203128 A CN114203128 A CN 114203128A CN 202111556577 A CN202111556577 A CN 202111556577A CN 114203128 A CN114203128 A CN 114203128A
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- target
- slope
- pixel row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
Abstract
The invention discloses a display panel driving method, a circuit and a display device, wherein the method comprises the following steps: determining a current target pixel row to be refreshed aiming at each clock signal line; acquiring a target signal slope matched with a target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between the high level and the low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal; and outputting the scanning driving signal of the target pixel row based on the target signal slope. The method can effectively inhibit the poor horizontal stripes of the display screen.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel driving method, a circuit and a display device.
Background
With the development of LCD (Liquid Crystal Display) technology, products generally require high resolution, large size, and high refresh rate. However, in the course of development, particularly high resolution, large size, high refresh rate panels are relatively prone to periodic striations.
Therefore, a method or apparatus for improving the periodic horizontal stripe defect of the display panel is needed.
Disclosure of Invention
In view of the above problems, the present invention provides a display panel driving method, circuit and display device, which can realize independent control of driving capability between different clock signal lines, and control based on a slope comparison table calibrated by testing, so as to effectively reduce difference of gate voltage drop time (Gout Timing dropping, Gout Tf) of each pixel row, and effectively suppress poor horizontal stripes of a display screen.
In a first aspect, the present application provides the following technical solutions through an embodiment:
a display panel driving method, comprising:
determining a current target pixel row to be refreshed aiming at each clock signal line; acquiring a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal; and outputting the scanning driving signal of the target pixel row based on the target signal slope.
Optionally, the outputting the scan driving signal of the target pixel row based on the target signal slope includes:
controlling a first level shift unit matched with a current clock signal line to output the scanning driving signal with the driving capability matched with the target signal slope; each clock signal line corresponds to a first level shift unit.
Optionally, the controlling the first level shift unit matched with the current clock signal line to output the scan driving signal with the driving capability matched with the slope of the target signal includes:
when the target signal slope is changed relative to the signal slope of the last historical refresh pixel row, increasing or decreasing the control bit in the register by a preset value to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table; and controlling a first level shift unit matched with the current clock signal line to output the scanning driving signal based on the target control bit.
Optionally, the outputting the scan driving signal of the target pixel row based on the target signal slope includes:
determining a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage; and controlling a second level shift unit to output the scanning driving signal based on the target voltage.
Optionally, the determining a current target pixel row to be refreshed includes:
receiving a trigger signal; initializing a counting unit based on the trigger signal to obtain an initial counting value; and obtaining the target pixel row based on the scanning driving signal of the historical refreshing pixel row and the initial counting value.
Optionally, the obtaining the target pixel row based on the scanning driving signal of the history refreshing pixel row and the initial count value includes:
adding one to the initial count value based on the scanning driving signal of each historical refreshing pixel row to obtain the target pixel row; wherein each count value corresponds to at least one row of pixels.
Optionally, the trigger signal includes:
a pre-frame reset signal and/or a pre-frame pulse trigger signal.
In a second aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a display panel driving circuit comprising: the counting circuit is connected with the change judging circuit, and the change judging circuit is connected with the driving capability control circuit;
for each clock signal line, the counting circuit is configured to determine a target pixel row to be refreshed currently; the change judging circuit is configured to acquire a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal; the driving capability control circuit is configured to output a scan driving signal of the target pixel row based on the target signal slope.
Optionally, the driving capability control circuit includes a first level shift sub-circuit, and each clock signal line matches with one first level shift sub-circuit;
the first level shift sub-circuit is configured to output the scan driving signal of a driving capability matched with the target signal slope.
Optionally, the driving capability control circuit further includes a control bit changing sub-circuit, and a register connected to the control bit changing sub-circuit;
the control bit changing sub-circuit is configured to increase or decrease the control bit in the register by a preset value in response to a change of the target signal slope relative to the signal slope of the last historical refresh pixel row, so as to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table; the first level shift unit is further configured to output the scan driving signal based on the target control bit.
Optionally, the driving capability control circuit includes a voltage divider sub-circuit and a second level shift sub-circuit connected to the voltage divider sub-circuit;
the voltage divider sub-circuit is configured to determine a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage; the second level shift sub-circuit configured to output the scan driving signal based on the target voltage.
Optionally, the counting circuit includes an initialization sub-circuit and a counting sub-circuit connected to the initialization sub-circuit;
the initialization sub-circuit is configured to initialize the counting sub-circuit based on the received trigger signal to obtain an initial count value; the counting sub-circuit is configured to obtain the target pixel row based on a scan driving signal of a history refresh pixel row and the initial count value.
Optionally, the counting sub-circuit is further configured to obtain the target pixel row by adding one to the initial count value based on the scan driving signal of each of the history refresh pixel rows; wherein each count value corresponds to at least one row of pixels.
Optionally, the trigger signal includes:
a pre-frame reset signal and/or a pre-frame pulse trigger signal.
In a third aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment:
a display device comprising the display panel drive circuit of any one of the second aspect.
In the display panel driving method in the embodiment of the invention, for each clock signal line, the current clock signal line is subjected to the comparisonCounting the target pixel rows to be refreshed to determine the row number of the target pixel rows; reading a slope comparison table and judging the signal slope corresponding to the target pixel row; and outputting a corresponding scanning driving signal based on the signal slope. Therefore, the signal slopes driven by different pixel rows can be independently controlled by the same clock signal line, the independent control can be realized among different clock signal lines, the control is carried out based on the slope comparison table calibrated by testing, and the G of each pixel row can be effectively reducedoutTf difference effectively inhibits the poor striation of the display screen.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts. In the drawings:
FIG. 1 is a schematic diagram illustrating a comparison between a row gate voltage drop and a row gate voltage drop of each pixel row of a conventional display panel;
FIG. 2 is a graph showing a comparison of the time taken for a row gate voltage to drop for each pixel row of another conventional display panel;
FIG. 3 is a flow chart of a display panel driving method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing waveforms of clock signals corresponding to different signal slopes according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a display panel driving circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a display panel driving circuit according to another embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display panel driving circuit according to still another embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The applicant finds through test analysis that in a high-resolution, large-size, high-refresh-rate display panel, there is a doubling reduction in the pixel charging time per row. Therefore, in a very short charging time, the image quality of the panel display is very sensitive to external disturbances and charging differences due to large size. For example, the periodic clock signal may be subjected to crosstalk from other signals, so that the charging rate of the pixel controlled by one of the periodic clock signals changes, and the whole line appears bright or dark.
Referring to fig. 1-2, fig. 1 shows a time (G) consumed by a row gate voltage drop of each pixel row when a periodic horizontal stripe occurs in a display panel with a 75-inch 4K resolution and a 144HZ refresh rateout Timing falling，GoutTf) comparison scheme; FIG. 2 is a graph illustrating how it takes for the row gate voltage of each pixel row to drop when a periodic horizontal streak occurs in another 75 inch 4K resolution 144HZ refresh rate display panel. In the display panel corresponding to fig. 1 and 2, the resistance of the clock signal line before it enters the pixel row is 10 Ω, and the gate row driving corresponds to 6 sets of clock period signals (6 CLK); the abscissa m of fig. 1 and 2 is the number of rows of pixels, and the ordinate t is the row gate voltage drop elapsed time. It can be found through the tests of fig. 1 and 2 that G can be caused at different positions for the same clock signal due to external interference and wiring factorsoutTf appeared to be different. For example, there is a time difference between rows D2130, D2160; meanwhile, there will be more obvious G between different clock signalsoutTf difference, e.g. G for each row between rows D2155 through D2160outTf also has a more significant difference; thereby easily resulting in more pronounced cross-hatching failure. And is generally represented by the degree of inconsistency between the DP side and the DPO side (the side on which the active driver is provided is generally called the DP side, and the DPO side is the side opposite to the DP side). At present, different resistors are matched with a Gate Driver on Array (GOA) unit to improve a clock signal, but the improvement method has the disadvantages of poor operability, low realization efficiency, incapability of considering the middle and the upper and lower sides of a screen and unobvious improvement effect.
Therefore, in the embodiments of the present invention, a display panel driving method, a display panel driving circuit capable of implementing the display panel driving method, and a display device using the display panel driving method and the display panel driving circuit are proposed to overcome the problem of the conventional LCD display panel due to GoutThe striae and the like caused by the Tf difference showed poor results. The following describes the specific concept of the present invention in detail by way of specific examples, respectively.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for driving a display panel according to an embodiment of the present invention. The display panel driving method includes:
step S10: determining a current target pixel row to be refreshed aiming at each clock signal line;
step S20: acquiring a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal;
step S30: and outputting the scanning driving signal of the target pixel row based on the target signal slope.
In this embodiment, in the process of scanning the display panel line by line through steps S10-S30, for each clock signal line, when a certain row of target pixel rows is refreshed, a corresponding signal slope (slope rate) is searched in the slope comparison table, so as to ramp based on the searched target signalAnd outputting the scanning driving signal of the target pixel row. Therefore, independent control of scanning driving signals of different pixel rows can be realized, so that the scanning driving signals of each pixel row are respectively adjusted to compensate G of each pixel rowoutTf is influenced by the outside, namely the charging rate of each pixel row is adjusted, and G of each pixel row is reducedoutTf difference effectively inhibits the poor horizontal striation of the display screen; and the operability achieved is strong. Specific possible implementations of the various steps of the present embodiment are illustrated and described in more detail below.
Step S10: for each clock signal line, a target pixel row to be refreshed currently is determined.
In step S10, it is understood that, for each clock signal line, the steps can be performed according to the method of the present embodiment to realize the independent adjustment of the scan driving signals at different pixel rows.
When the current target pixel row to be refreshed is determined, counting and obtaining can be carried out according to the following mode; specifically, each time a frame of picture is refreshed, counting can be performed from an initial count value; and increasing a numerical value on the basis of the initial count value every time one pixel row is refreshed, and increasing the count for several times when the pixel row is refreshed, so that the target pixel row to be refreshed can be positioned in real time.
For example, the counting unit may be initialized by the received trigger signal; the trigger signal can be a pre-frame reset signal and/or a pre-frame pulse trigger signal, the pre-frame reset signal is a signal (STV0) which is transmitted by a reset signal line and used for resetting the GOA unit, and the pre-frame pulse trigger signal is a signal (STV1) used for triggering the GOA unit to output a driving pulse; the pre-frame reset signal and/or the pre-frame pulse trigger signal may be from a TCON (Timer Control Register). Secondly, initializing a counting unit based on the trigger signal to obtain an initial counting value; the counting unit can adopt the existing counting circuit to realize the counting function without limitation. Then, the target pixel row is obtained based on the scanning drive signal and the initial count value of the history refresh pixel row. In some implementations, the initial count value may be incremented based on the scan driving signal of each history refresh pixel row, that is, the count value may be incremented by one every time a clock cycle passes, so as to obtain the target pixel row; the first rising edge of a corresponding clock signal of a row may be used to trigger counting; each count value corresponds to at least one row of pixels; when more than two rows are refreshed simultaneously, one count value can correspond to more than two rows of pixels.
For ease of understanding, referring to an example of a 6CLK clock signal, if the clock signal CLK1 is asserted, the initial count value is 0 (corresponding to the 1 st row of pixels on the display panel) and the initial count value can be stored in a memory; every time the pixel row corresponding to 1 row of CLK1 is refreshed, 1 may be added to the count value in the memory; when the pixel row corresponding to the 2 nd row CLK1 is refreshed (corresponding to the 7 th row pixels of the display panel at this time), the initial count value in the memory is increased by 1 and stored as 2; when the pixel row corresponding to the 3 rd row CLK1 is refreshed (corresponding to the 13 th row pixels of the display panel at this time), the count value in the memory is added by 1 and is stored as 3; and so on. In the display panel of 4K resolution, the total number of counts of CLK1 is 360; the clock signals CLK2, CLK3, CLK4, CLK5, and CLK6 may all be implemented with reference to the clock signal CLK1, and the description will continue with this example. In other implementations, the number of clock signal lines is not limited, and may be, for example, 4CLK, 12CLK, 16CLK, etc.
By the counting mode, the current pixel row to be refreshed can be accurately positioned, and the premise of realizing independent control of each row of scanning driving signals is provided.
Step S20: acquiring a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between the high level and the low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal.
In step S20, the slope comparison table may include a corresponding relationship between each pixel row corresponding to the clock signal line and the signal slope; the corresponding relationship between each pixel row corresponding to a plurality of clock signal lines and the signal slope may also be included without limitation. The corresponding relation can be that the identification code of the target pixel line corresponds to the signal slope or the identification code thereof; the target signal slope may be indexed in a slope look-up table based on the target pixel row, the data structure of the slope look-up table not being limited; the slope lookup table may be pre-stored in a memory and recalled or read by a processor or circuit performing the step as the step is performed.
It should be noted that the signal slope may be a rising slope, i.e. a speed (slope) at which the clock signal changes from a low level to a high level; or a falling slope, i.e., the speed (slope) at which the clock signal transitions from a high level to a low level.
Since the GOA RC loading (resistance-capacitance loading) is different in the display panels with different sizes and different processes, the slope comparison tables corresponding to different display panels are also different. In this embodiment, the signal slope corresponding to the pixel line may be determined in a test calibration manner, for example, the signal slope of each region of the display panel is adjusted in the test process, and whether the display screen has a cross-stripe defect is observed or tested; based on the picture quality requirement to be achieved, an optimal or better set of signal slopes is found. The signal slope is changed in a stepwise manner, so that excessive control gears are avoided, and the operability is improved; for example, the first 100 lines of the clock signal CLK1 have the same slope, the middle 200 lines have the same slope, and the last 60 lines have the same slope. Different signal slopes correspond to different signal waveforms, thereby achieving GoutTf, as shown in FIG. 4. FIG. 4 shows waveforms of clock signals of a 75-inch 4K-resolution 144hz refresh rate display panel at signal slopes C1(1000V/us), R2(400V/us), and R1(100V/us), respectively.
Step S30: and outputting the scanning driving signal of the target pixel row based on the target signal slope.
In step S30, the determined target signal slope may be achieved by one or more implementations, such that the scan driving signal matched to the target signal slope is output, and G is achievedoutAnd (f) adjusting. At least two implementations are provided in this embodiment.
1. The driving capability of driving the scanning signal is controlled by controlling the magnitude of the output current of each clock signal line channel.
The driving capability of the clock signal corresponding to different pixel rows can be set according to the requirement, and the signal slope can be debugged. In this way, all the current clock signal lines can share the same driving capability setting, and the driving capability setting is changed to be independent for each clock signal line, so that the level shift unit matched with each clock signal line is connected with each clock signal line.
In particular, in this embodiment, a plurality of level shift units (named as first level shift units for convenience of distinguishing the level shift units in this embodiment) may be used to implement different driving capabilities, and each clock signal line corresponds to one first level shift unit. Then, the first level shift unit matched with the current clock signal line can be controlled to output a scanning driving signal with the driving capability matched with the target signal slope. For the convenience of control, a register is provided for storing the driving capability and corresponding control bits of the first level shift unit. The circuit implementation of the level shift unit can adopt the existing implementation mode, and is not described in detail.
For example, continuing with the aforementioned description of the display panel with the 75-inch 4K resolution and the 144hz refresh rate, the clock signal corresponding to each clock signal line can be set to 4 gears through testing, and each gear can be implemented by using the first level shift unit, which respectively is: 100% drive capability, 80% drive capability, 40% drive capability, and 10% drive capability; the change between these 4 gears can be controlled with 2 bits. For the clock signal CLK1, the correspondence between the control bit and the driving capability shift position may be: 00 (100% drive capacity), 01 (80% drive capacity), 10 (40% drive capacity), 11 (10% drive capacity).
Further, when step S30 is implemented, the first level shift unit matched with the current clock signal line may be controlled to output a scan driving signal with a driving capability matched with the slope of the target signal; for example, when 100% of the driving capability is required to reach the target signal slope, the first level shift unit is controlled to adjust the output current based on the control bit being 00, so as to output the scan driving signal with 100% of the driving capability, and so on. The scanning driving signal also needs to be processed through a GOA unit of the display panel, and finally a grid driving signal for driving a pixel row is obtained; for example, shift processing by a shift unit (shift register) or the like is performed.
The driving capability of the output scan driving signal can be adjusted as follows:
and in response to the fact that the slope of the target signal does not change relative to the previous historical refreshing pixel row, keeping the original driving capacity unchanged, and keeping the value of the control bit in the register unchanged.
The driving capability of the clock signal corresponding to all the clock signal lines can be initialized by electrifying the display panel according to needs, and the driving capability of the clock signal is changed according to the determined target signal slope; as the common panel is uniformly transited from the DP side to the DPO side, the driving capability of the adjacent pixel rows corresponding to the same clock signal does not jump.
Therefore, when the target signal slope changes relative to the signal slope of the last historical refresh pixel row, the control bit in the register is increased or decreased by a preset value to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table. Then, a first level shift unit matched with the current clock signal line is controlled to output a scanning driving signal based on the target control bit. Taking the example of controlling 4 gears by 2 bits as an example, the value of the control bit in the register can be increased by 1 or decreased by 1, so as to realize the continuous adjustment of the driving capability by the first level shift unit; in addition, based on the difference of the gear number, the bit width of the control bit can be correspondingly adjusted without limitation.
2. The target signal slope is achieved by adjusting by controlling the magnitude of the pixel row off hold Voltage (VGL).
In this implementation, a voltage dividing unit may be added to adjust the off-hold voltage of the pixel row, and a circuit of the voltage dividing unit is implemented in the following embodiments of the apparatus. Specifically, the implementation process may be as follows:
firstly, determining a target voltage from a scanning turn-off voltage interval based on a target signal slope; wherein, the sweepThe upper limit of the line-off voltage interval is a pixel row off holding voltage, and the lower limit is a pixel row off voltage (LVGL); the pixel row turn-off holding voltage is the voltage of the GOA unit turn-off holding stage; the off-pixel voltage is the voltage when the GOA unit is turned off. Also, to provide operability, multiple control gears may be provided; namely, a plurality of voltage value taking points are determined in the scanning turn-off voltage interval, and each voltage value taking point corresponds to a control gear. For example, when 4 gears are set, V1, V2, V3, and V4 may be set. The 4 voltages correspond to different signal slopes. The target voltage is input to the level shift unit (for the convenience of distinguishing, the level shift unit is called as a second level shift unit), then the second level shift unit is controlled to output a scanning driving signal based on the target voltage, the signal slope adjustment of the clock signal is realized, and G is reducedoutTf difference effectively inhibits the poor striation of the display screen.
Therefore, in this embodiment, the scanning driving signals of different pixel rows can be independently controlled by the two methods, the signal slopes of the clock signals of the pixel rows in different areas of the display panel can be flexibly adjusted, the control is performed based on the slope comparison table calibrated by testing, and the G of each pixel row can be effectively reducedoutTf difference effectively inhibits the poor striation of the display screen.
Referring to fig. 5, based on the same inventive concept, in another embodiment of the present invention, a display panel driving circuit 300 is further provided, including: a counter circuit 31, a change determination circuit 32, and a driving capability control circuit 33, wherein the counter circuit 31 is connected to the change determination circuit 32, and the change determination circuit 32 is connected to the driving capability control circuit 33; each circuit configuration in the present embodiment can perform the following function for each clock signal line.
The counting circuit 31 is configured to determine a target pixel row to be refreshed currently.
In some realizable embodiments, the counting circuit 31 includes an initialization sub-circuit and a counting sub-circuit connected to the initialization sub-circuit. Wherein the initialization sub-circuit is configured to initialize the counting sub-circuit based on the received trigger signal to obtain an initial count value; the counting sub-circuit is configured to obtain a target pixel row based on the initial count value and the scan driving signal of the history refresh pixel row. The trigger signal may include: a pre-frame reset signal and/or a pre-frame pulse trigger signal.
Further, the counting sub-circuit is further configured to increment the initial count value by one based on the scan driving signal of each history refresh pixel row to obtain a target pixel row; wherein each count value corresponds to at least one row of pixels.
A change determination circuit 32 configured to acquire a target signal slope matching the target pixel row in the slope lookup table; the signal slope represents the speed of the clock signal switching between the high level and the low level, and the slope look-up table includes the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal. The slope comparison table may be pre-stored in a memory.
A driving capability control circuit 33 configured to output a scanning driving signal of a target pixel row based on a target signal slope.
The scanning driving signal is a signal output by the displacement unit, and further processing is needed to obtain a grid driving signal of a pixel row; for example, shift processing by a shift unit (shift register) is required.
The driving signal transmission circuit at least comprises two specific implementation modes:
1. the scanning driving signals with different signal slopes are output by controlling the magnitude of the output current of the first level shift sub-circuit 331 a; and each clock signal line is matched with a first level shift sub-circuit, so that different clock signal lines are independently controlled.
Referring to fig. 6, in this alternative embodiment, the driving capability control circuit 33 includes a first level shift sub-circuit 331 a; the first level shift sub-circuit 331a is configured to output a scan driving signal of a driving capability matching a slope of a target signal. Specifically, after the display panel is powered on, the first level shift sub-circuit 331a initializes the driving capability corresponding to the clock line, and then changes the driving capability according to the received signal of the change determination circuit 32.
Further, the driving-capability control circuit 33 further includes a control-bit changing sub-circuit, and a register (not shown) connected to the control-bit changing sub-circuit; the control bit change sub-circuit is configured to: when the target signal slope is changed relative to the signal slope of the last historical refresh pixel row, increasing or decreasing the control bit in the register by a preset value to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table; the first level shift unit 331a is also configured to output a scan driving signal based on the target control bit.
2. The pixel row off holding voltage is divided by the voltage dividing sub-circuit 330b to realize the output of the scan driving signals with different signal slopes.
Referring to fig. 7, in this alternative embodiment, the driving capability control circuit 33 includes a voltage divider sub-circuit 330b and a second level shifter sub-circuit 333b connected to the voltage divider sub-circuit 330 b; the voltage divider sub-circuit 330b is configured to determine a target voltage from the scan-off voltage interval based on a target signal slope; wherein, the upper limit of the scanning turn-off voltage interval is a pixel row turn-off holding Voltage (VGL), and the lower limit is a pixel row turn-off voltage (LVGL); a second level shift sub-circuit 333b configured to output a scan driving signal based on the target voltage.
The voltage dividing sub-circuit 330b may be formed by a controller 331b and a digital-to-analog converter (DAC)332b, where the controller 331b may receive a signal indicating a signal slope or a change in the signal slope transmitted by the change determination circuit 32, and then drive the DAC to process the off hold voltage to output a target voltage (VGLx) in a scan off voltage interval, that is, the target voltage is less than or equal to the pixel row off hold voltage and greater than or equal to the pixel row off voltage; then, the second level shift sub-circuit 333b receives the target voltage and outputs the scan driving signal according to the target voltage and the original turn-on Voltage (VGH). The controller 331b and the digital-to-analog converter 332b may be implemented by using existing devices or circuit structures, without limitation.
If adjacent rows of the display panel have a signal slope change, the change manner is continuously changed instead of jumping, and the change determination circuit 32 determines the target signal slope and then determines whether the target signal slope changes relative to the signal slope corresponding to the previous pixel row. If the change occurs, the change determination circuit 32 outputs a signal indicating the change to the controller 331b, so that the controller 331b drives the digital-to-analog converter 332b to output the target voltage; if there is no change, the change determination circuit 32 can output a signal indicating that the slope of the signal has not changed to the level shift sub-circuit, so as to keep the scan driving signal output by the driving capability control circuit 33 unchanged, which does not need to be processed by the controller 331 b.
In this embodiment, since the voltage divider circuit 330b is used to divide the pixel row off hold voltage, the second level shifter circuit 333b can be shared by a plurality of clock signal lines.
In the display panel driving circuit 300 of the present embodiment, for each clock signal line, the counting circuit 31 may count a current target pixel row to be refreshed, so as to determine a number of rows where the target pixel row is located; then, the slope comparison table is read by the change judgment circuit 32 and the signal slope corresponding to the target pixel row is judged; finally, the driving capability control circuit 33 outputs a corresponding scanning driving signal based on the signal slope. Therefore, the independent control of the signal slopes driven by different pixel rows by the same clock signal line is realized, the independent control can be realized among different clock signal lines, the control is carried out by taking the slope comparison table calibrated by testing as the basis, and the G of each pixel row can be effectively reducedoutTf difference effectively inhibits the poor striation of the display screen.
In the present embodiment, the counter circuit 31 and the change determination circuit 32 can be shared among a plurality of clock signal lines, and signal processing for different clock signal lines can be performed by distinguishing between different signal marks; the counter circuit 31 and the change determination circuit 32 may be designed independently for different clock signal lines, and are not limited.
It should be further noted that the display panel driving circuit 300 provided in this embodiment can be used to implement the processing steps in the foregoing method embodiments; therefore, the detailed implementation of each function of each circuit and sub-circuit structure in this embodiment can refer to the foregoing method embodiments, which are not described in detail in this embodiment. The specific hardware implementation of each circuit or sub-circuit structure not mentioned in this embodiment may adopt the existing common implementation method, which is not described in detail in this embodiment.
Based on the same inventive concept, in yet another embodiment of the present invention, there is provided a display device including the display panel driving circuit of any one of the foregoing embodiments.
It should be noted that, the display device provided by the embodiment of the present invention employs the display panel driving circuit of the foregoing embodiment, and the specific implementation and the generated technical effects are the same as those of the foregoing method embodiment.
The term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship; the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A display panel driving method, comprising:
determining a current target pixel row to be refreshed aiming at each clock signal line;
acquiring a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal;
and outputting the scanning driving signal of the target pixel row based on the target signal slope.
2. The method of claim 1, wherein outputting the scan drive signal for the target row of pixels based on the target signal slope comprises:
controlling a first level shift unit matched with a current clock signal line to output the scanning driving signal with the driving capability matched with the target signal slope; each clock signal line corresponds to a first level shift unit.
3. The method of claim 2, wherein the controlling the first level shift unit matched to the current clock signal line to output the scan driving signal with a driving capability matched to the target signal slope comprises:
when the target signal slope is changed relative to the signal slope of the last historical refresh pixel row, increasing or decreasing the control bit in the register by a preset value to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table;
and controlling a first level shift unit matched with the current clock signal line to output the scanning driving signal based on the target control bit.
4. The method of claim 1, wherein outputting the scan drive signal for the target row of pixels based on the target signal slope comprises:
determining a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage;
and controlling a second level shift unit to output the scanning driving signal based on the target voltage.
5. The method of claim 1, wherein determining the target row of pixels to be refreshed currently comprises:
receiving a trigger signal;
initializing a counting unit based on the trigger signal to obtain an initial counting value;
and obtaining the target pixel row based on the scanning driving signal of the historical refreshing pixel row and the initial counting value.
6. The method of claim 5, wherein obtaining the target row of pixels based on the initial count value and the scan drive signal to refresh the row of pixels based on the history comprises:
adding one to the initial count value based on the scanning driving signal of each historical refreshing pixel row to obtain the target pixel row; wherein each count value corresponds to at least one row of pixels.
7. The method of claim 5, wherein the trigger signal comprises:
a pre-frame reset signal and/or a pre-frame pulse trigger signal.
8. A display panel driving circuit, comprising: the counting circuit is connected with the change judging circuit, and the change judging circuit is connected with the driving capability control circuit;
for each clock signal line, the counting circuit is configured to determine a target pixel row to be refreshed currently;
the change judging circuit is configured to acquire a target signal slope matched with the target pixel row in a slope comparison table; the signal slope represents the speed of the clock signal switching between a high level and a low level, and the slope comparison table comprises the corresponding relation between each pixel row of the display panel and the signal slope of the clock signal;
the driving capability control circuit is configured to output a scan driving signal of the target pixel row based on the target signal slope.
9. The display panel driving circuit according to claim 8, wherein the driving capability control circuit comprises a first level shift sub-circuit, each clock signal line matching a first level shift sub-circuit;
the first level shift sub-circuit is configured to output the scan driving signal of a driving capability matched with the target signal slope.
10. The display panel driving circuit according to claim 9, wherein the driving capability control circuit further comprises a control bit changing sub-circuit, and a register connected to the control bit changing sub-circuit;
the control bit changing sub-circuit is configured to increase or decrease the control bit in the register by a preset value in response to a change of the target signal slope relative to the signal slope of the last historical refresh pixel row, so as to obtain a target control bit; the preset value is a control bit difference value of two adjacent signal slopes corresponding to the same clock signal line in the slope comparison table;
the first level shift unit is further configured to output the scan driving signal based on the target control bit.
11. The display panel driving circuit according to claim 8, wherein the driving capability control circuit comprises a voltage divider sub-circuit and a second level shift sub-circuit connected to the voltage divider sub-circuit;
the voltage divider sub-circuit is configured to determine a target voltage from a scan-off voltage interval based on the target signal slope; the upper limit of the scanning turn-off voltage interval is the pixel row turn-off holding voltage, and the lower limit of the scanning turn-off voltage interval is the pixel row turn-off voltage;
the second level shift sub-circuit configured to output the scan driving signal based on the target voltage.
12. The display panel driving circuit according to claim 8, wherein the counting circuit comprises an initialization sub-circuit and a counting sub-circuit connected to the initialization sub-circuit;
the initialization sub-circuit is configured to initialize the counting sub-circuit based on the received trigger signal to obtain an initial count value;
the counting sub-circuit is configured to obtain the target pixel row based on a scan driving signal of a history refresh pixel row and the initial count value.
13. The display panel driving circuit according to claim 12, wherein the counting sub-circuit is further configured to obtain the target pixel row by adding one to the initial count value based on a scan driving signal of each of the history refresh pixel rows; wherein each count value corresponds to at least one row of pixels.
14. The display panel driving circuit according to claim 12, wherein the trigger signal comprises:
a pre-frame reset signal and/or a pre-frame pulse trigger signal.
15. A display device comprising the display panel drive circuit according to any one of claims 8 to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111556577.7A CN114203128B (en) | 2021-12-17 | 2021-12-17 | Display panel driving method and circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111556577.7A CN114203128B (en) | 2021-12-17 | 2021-12-17 | Display panel driving method and circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114203128A true CN114203128A (en) | 2022-03-18 |
| CN114203128B CN114203128B (en) | 2022-11-15 |
Family
ID=80655230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111556577.7A Active CN114203128B (en) | 2021-12-17 | 2021-12-17 | Display panel driving method and circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114203128B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114765013A (en) * | 2022-05-23 | 2022-07-19 | 合肥京东方显示技术有限公司 | Display driving circuit, display driving method and related equipment |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003208141A (en) * | 2002-10-28 | 2003-07-25 | Sharp Corp | Display device and display method |
| CN101802903A (en) * | 2007-10-04 | 2010-08-11 | 夏普株式会社 | Display device and display device drive method |
| CN102376274A (en) * | 2010-08-06 | 2012-03-14 | 群康科技(深圳)有限公司 | Liquid crystal display |
| JP2014032282A (en) * | 2012-08-02 | 2014-02-20 | Sharp Corp | Display device and television receiver including the same |
| CN106683630A (en) * | 2016-12-29 | 2017-05-17 | 惠科股份有限公司 | Pixel charge method and pixel charge circuit |
| CN107665687A (en) * | 2017-10-26 | 2018-02-06 | 惠科股份有限公司 | A kind of display device |
| CN107767832A (en) * | 2017-11-07 | 2018-03-06 | 深圳市华星光电半导体显示技术有限公司 | A kind of liquid crystal display panel and gate driving circuit |
| CN108376522A (en) * | 2018-04-27 | 2018-08-07 | 上海中航光电子有限公司 | A kind of abnormity panel and display device |
| CN108470551A (en) * | 2018-05-28 | 2018-08-31 | 京东方科技集团股份有限公司 | The driving method and driving device of GOA circuits, display device |
| CN109345996A (en) * | 2018-12-05 | 2019-02-15 | 惠科股份有限公司 | Timing controller, display driving assembly and display device |
| CN109637352A (en) * | 2018-12-28 | 2019-04-16 | 上海天马微电子有限公司 | A kind of display panel and display device |
| CN111179799A (en) * | 2018-11-09 | 2020-05-19 | 堺显示器制品株式会社 | Display device and method for driving display panel |
| CN112419992A (en) * | 2020-11-26 | 2021-02-26 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN113189808A (en) * | 2021-06-09 | 2021-07-30 | 合肥京东方显示技术有限公司 | Array substrate, display panel and display device |
-
2021
- 2021-12-17 CN CN202111556577.7A patent/CN114203128B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003208141A (en) * | 2002-10-28 | 2003-07-25 | Sharp Corp | Display device and display method |
| CN101802903A (en) * | 2007-10-04 | 2010-08-11 | 夏普株式会社 | Display device and display device drive method |
| CN102376274A (en) * | 2010-08-06 | 2012-03-14 | 群康科技(深圳)有限公司 | Liquid crystal display |
| JP2014032282A (en) * | 2012-08-02 | 2014-02-20 | Sharp Corp | Display device and television receiver including the same |
| CN106683630A (en) * | 2016-12-29 | 2017-05-17 | 惠科股份有限公司 | Pixel charge method and pixel charge circuit |
| CN107665687A (en) * | 2017-10-26 | 2018-02-06 | 惠科股份有限公司 | A kind of display device |
| CN107767832A (en) * | 2017-11-07 | 2018-03-06 | 深圳市华星光电半导体显示技术有限公司 | A kind of liquid crystal display panel and gate driving circuit |
| CN108376522A (en) * | 2018-04-27 | 2018-08-07 | 上海中航光电子有限公司 | A kind of abnormity panel and display device |
| CN108470551A (en) * | 2018-05-28 | 2018-08-31 | 京东方科技集团股份有限公司 | The driving method and driving device of GOA circuits, display device |
| CN111179799A (en) * | 2018-11-09 | 2020-05-19 | 堺显示器制品株式会社 | Display device and method for driving display panel |
| CN109345996A (en) * | 2018-12-05 | 2019-02-15 | 惠科股份有限公司 | Timing controller, display driving assembly and display device |
| CN109637352A (en) * | 2018-12-28 | 2019-04-16 | 上海天马微电子有限公司 | A kind of display panel and display device |
| CN112419992A (en) * | 2020-11-26 | 2021-02-26 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN113189808A (en) * | 2021-06-09 | 2021-07-30 | 合肥京东方显示技术有限公司 | Array substrate, display panel and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114765013A (en) * | 2022-05-23 | 2022-07-19 | 合肥京东方显示技术有限公司 | Display driving circuit, display driving method and related equipment |
| CN114765013B (en) * | 2022-05-23 | 2024-02-23 | 合肥京东方显示技术有限公司 | Display driving circuit, display driving method and related equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114203128B (en) | 2022-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5676069B2 (en) | Liquid crystal display | |
| US7154464B2 (en) | Liquid crystal display and driving method thereof | |
| KR101115730B1 (en) | Gate driver and display device having the same | |
| US8400439B2 (en) | Integrated circuit device, electro optical device and electronic apparatus | |
| JP2004061670A (en) | Liquid crystal display device and its driving method | |
| US20050270282A1 (en) | Flat display panel driving method and flat display device | |
| US20210201729A1 (en) | Driving method and driving system for display apparatuses | |
| CN109979392B (en) | Time sequence control method, time sequence control module and display device | |
| CN114203128B (en) | Display panel driving method and circuit and display device | |
| JP5132037B2 (en) | Display panel and driving method thereof | |
| JPH0895000A (en) | Driving device and method of liquid crystal display | |
| US8350793B2 (en) | Image over-driving devices and image over-driving controlling methods | |
| US7956840B2 (en) | Electro-optical device, driving method, and electronic apparatus | |
| US20090278829A1 (en) | Electro-optic device, driving method, and electronic apparatus | |
| TWI410922B (en) | Electro-optical apparatus, method for driving electro-optical apparatus, and method for monitoring voltage | |
| WO2004013835A1 (en) | Method and circuit for driving a liquid crystal display | |
| US20130057600A1 (en) | Display apparatus and driving method thereof | |
| TWI416476B (en) | Liquid crystal device, control circuit therefor, and electronic apparatus | |
| JP2007003967A (en) | Display apparatus | |
| US20020097211A1 (en) | Liquid crystal display device and method for driving the same | |
| KR100329538B1 (en) | Method and apparatus for driving liquid crystal display panel | |
| JP3900256B2 (en) | Liquid crystal drive device and liquid crystal display device | |
| CN113971943A (en) | Display driving method and device and display device | |
| US20080062210A1 (en) | Driving device, display apparatus having the same and method of driving the display apparatus | |
| KR100627995B1 (en) | Matrix display device adapted to display video signals from different video standards |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |