CN102376274A - Liquid crystal display - Google Patents
Liquid crystal display Download PDFInfo
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- CN102376274A CN102376274A CN2010102471608A CN201010247160A CN102376274A CN 102376274 A CN102376274 A CN 102376274A CN 2010102471608 A CN2010102471608 A CN 2010102471608A CN 201010247160 A CN201010247160 A CN 201010247160A CN 102376274 A CN102376274 A CN 102376274A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 42
- 230000000630 rising effect Effects 0.000 claims description 23
- 230000008771 sex reversal Effects 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 4
- 239000010409 thin film Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
The invention discloses a liquid crystal display which comprises a liquid crystal panel, a display control circuit and a data driven circuit, wherein the display control circuit is used for receiving an image signal and generating a time sequence signal and a data signal according to the image signal; the data driven circuit is used for receiving the time sequence signal and the data signal so as to form a plurality of data voltages; and before the data voltage for driving a non-polar inversed pixel is pre-output, the data driven circuit is used for adjusting the voltages of a plurality of data wires to be preset voltage, so that the electric charge quantity stored by a polar inversed pixel is the same as that stored by the non-polar inversed pixel for the same-gram scale frame. The liquid crystal display can be used for improving the phenomenon that the frame flashes when the image of the liquid crystal display is displayed and has a better display effect.
Description
Technical field
The present invention relates to a kind of LCD.
Background technology
The liquid crystal molecule of LCD has such specific character: remain unchanged for a long time if be loaded into the direction of an electric field at liquid crystal layer two ends; The characteristic of liquid crystal molecule just can be destroyed so, promptly can't rotate to form different gray levels in response to the variation of electric field again.Therefore, LCD just must change direction of an electric field so that liquid crystal molecule reverses at regular intervals, thereby avoids the characteristic of liquid crystal molecule to be destroyed.Common inversion driving mode has at present: frame inversion driving (Frame Inversion), row inversion driving (Column Inversion), row inversion driving (Line/Row Inversion) and some inversion driving (Dot Inversion).Wherein, The point inversion driving comprises single line point inversion driving (1-line dot inversion) and two-wire point inversion driving type of drive such as (2-line dot inversion) again, can make that as the LCD of type of drive the power consumption of LCD is less and its film flicker phenomenon is less with two-wire point inversion driving.
So-called two-wire point inversion driving; The polarity that is the capable pixel institute on-load voltage with each same column during 4i+2 is capable of the 4i+1 of LCD is consistent; The polarity of the capable pixel institute on-load voltage with each same column during 4i+4 is capable of 4i+3 is consistent; And 4i+2 capable with 4i+3 capable in the polarity of pixel institute on-load voltage of each same column opposite, and the polarity of pixel institute of the same delegation on-load voltage of adjacent two row is opposite arbitrarily.Wherein, i is the integer more than or equal to zero.The polarity of each pixel institute on-load voltage is by the frame counter-rotating.
Yet for 4i+1 and the capable pixel of 4i+3, its on-load voltage is the data voltage that little by little changes to required polarity, and the duration of charging that therefore needs is longer.And for 4i+2 capable with the capable pixel of 4i+4, the polarity of its on-load voltage is identical with the polarity of previous row respective pixel, but then reaches required data voltage within a short period of time.Therefore; When the same row pixel that 4i+1 is capable and 4i+2 is capable adds identical data voltage in advance; This 4i+1 is capable, and in fact institute's charge stored amount is different with the capable pixel of this 4i+2, and then causes the capable brightness that is shown with the capable pixel of this 4i+2 of this 4i+1 different.So when the same grey menu of this liquid crystal display displays, bright line and concealed wire can appear in its images displayed, the user will see more serious film flicker phenomenon.
Equally, adopt row inversion driving and other multi-thread some inversion driving also to have mentioned problem in the above-mentioned two-wire point inversion driving.
Summary of the invention
The film flicker phenomenon that is occurred when solving liquid crystal display displays image in the prior art is necessary to provide a kind of LCD of film flicker phenomenon can improve display image the time.
A kind of LCD, it comprises liquid crystal panel, display control circuit and data drive circuit.This liquid crystal panel comprises the multi-strip scanning line, many data lines that intersect with the insulation of this multi-strip scanning line and a plurality of pixels that defined by this multi-strip scanning line and these many data lines.This display control circuit receives picture signal and generates clock signal and data-signal according to this picture signal.This data drive circuit this clock signal of reception and this data-signal are to form a plurality of data voltages.This data drive circuit is before output drives the data voltage of the pixel of nonpolarity counter-rotating row in advance; Voltage on these many data lines is all adjusted to predetermined voltage; So that for same grey menu, the pixel of this reversal of poles row institute charge stored amount is regarded as identical with the pixel institute charge stored amount of this nonpolarity counter-rotating row.
Compared to prior art; Because the data drive circuit of LCD of the present invention is before the data voltage of the pixel of exporting nonpolarity counter-rotating row in advance; Voltage on these many data lines is all adjusted to predetermined voltage; Therefore, the data voltage of the pixel of the corresponding nonpolarity counter-rotating row that this many data lines transmitted need little by little change to the data voltage of required polarity from this predetermined voltage, and then makes for same grey menu; The pixel institute charge stored amount difference of the pixel of reversal of poles row and nonpolarity counter-rotating row reduces, thus phenomenon of picture flicker when improving this liquid crystal display displays image.
Description of drawings
Fig. 1 is the structural representation of LCD first embodiment of the present invention.
When Fig. 2 is liquid crystal display displays one a frame picture shown in Figure 1, the synoptic diagram of its pixel institute on-load voltage polarity.
Fig. 3 is the driving sequential chart of LCD shown in Figure 1.
Fig. 4 is the structural representation of LCD second embodiment of the present invention.
Fig. 5 is the synoptic diagram of the look-up table of LCD shown in Figure 4.
Fig. 6 is the process flow diagram of LCD shown in Figure 4 driving method of film flicker phenomenon when improving display image.
Fig. 7 is the driving sequential chart of the refreshing frequency of LCD shown in Figure 4 when being 60HZ.
Fig. 8 is the driving sequential chart of the refreshing frequency of LCD shown in Figure 4 when being 75HZ.
Fig. 9 is the driving sequential chart of LCD the 3rd embodiment of the present invention.
Figure 10 is the oscillogram of the load control signal of another embodiment of LCD shown in Figure 1.
Figure 11 is the oscillogram of the load control signal of another embodiment of LCD shown in Figure 4.
Figure 12 is the driving sequential chart of another embodiment of LCD shown in Figure 4.
Figure 13 is the driving sequential chart of the another embodiment of LCD shown in Figure 4.
The main element symbol description
LCD 100,200
Display control circuit 10,20
Public voltage generating circuit 18,28
Sweep trace G
1～G
L, G '
1～G '
L
Data line D
1～D
M, D '
1～D '
M
Pixel 127,227
Thin film transistor (TFT) 121,221
Pixel electrode 123,223
Public electrode 125,225
Grid g, g '
Source electrode s, s '
Drain electrode d, d '
Frequency detector 210
Storer 220
Sequential control circuit 130,230
Look-up table 222
Embodiment
Main thought of the present invention is the load control signal that outputs to data drive circuit through the display control circuit of adjustment LCD; This load control signal not only can be exported the data voltage that drives each row pixel by the control data driving circuit; The more important thing is that this load control circuit can also be adjusted the voltage on these many data lines by the control data driving circuit.Particularly; This load control signal has a plurality of first and triggers sign and a plurality of second triggering sign; This a plurality of first trigger to indicate and to comprise and a plurality ofly be used for that the first output property triggering of data voltage that the output of trigger data driving circuit drives the pixel of nonpolarity counter-rotating row (explanation to the reversal of poles row sees also described in bright LCD first embodiment of this law) indicates and the second output property triggering of the data voltage of a plurality of pixels that are used for trigger data driving circuit output driving stage sex reversal capable (explanation to nonpolarity counter-rotating row sees also described in bright LCD first embodiment of this law) indicates; This second triggering indicates and comprises that a plurality of first scalability trigger sign; These a plurality of first scalability trigger to indicate and were used for before this data drive circuit is exported the data voltage of the pixel that drives nonpolarity counter-rotating row in advance, trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage.Wherein, This first scalability trigger indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this first output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the pixel of the nonpolarity counter-rotating row of driving.
Because the data drive circuit of LCD is used to drive in output in advance before the data voltage of pixel of nonpolarity counter-rotating row; Voltage on these many data lines is all adjusted to same predetermined voltage; Promptly for the pixel of nonpolarity counter-rotating row; Its charging voltage also as the charging voltage of the pixel of reversal of poles row, has the process that gradually changes.Therefore; The charging voltage of the pixel of corresponding nonpolarity counter-rotating row is reduced; And then make that for same grey menu, the pixel institute charge stored amount difference of reversal of poles row and nonpolarity counter-rotating row reduces, thereby phenomenon of picture flicker when improving this liquid crystal display displays image.
Further; This second triggering indicates and comprises that further a plurality of second scalability trigger sign; Each second output property triggering indicates respectively corresponding one second scalability triggering and indicates; These a plurality of second scalability trigger to indicate and were used for before this data drive circuit is exported the data voltage of the capable pixel of driving stage sex reversal in advance; Trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage; Wherein, this second scalability trigger indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this second output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the capable pixel of driving stage sex reversal.That is, this data drive circuit also can all be adjusted to this predetermined voltage with the voltage on these many data lines before the data voltage of the pixel that output driving stage sex reversal is capable in advance.
Because the data drive circuit of LCD is used in output before the data voltage of pixel of the capable and nonpolarity counter-rotating row of driving stage sex reversal; All the voltage on many data lines is all adjusted to same predetermined voltage; Therefore, the Changing Pattern of the charging voltage of the pixel of the pixel of reversal of poles row and nonpolarity counter-rotating row is basic identical.Thereby, make that for same grey menu, the pixel institute charge stored amount difference of reversal of poles row and nonpolarity counter-rotating row reduces, and then phenomenon of picture flicker when improving this liquid crystal display displays image.
About detail of the present invention, see also each following embodiment.
See also Fig. 1, it is the structural representation of LCD first embodiment of the present invention.This LCD 100 comprises the sweep trace G that a display control circuit 10, a liquid crystal panel 12, scan driving circuit 14, a data drive circuit 16, a public voltage generating circuit 18, multirow are parallel to each other
1～G
L(L is a natural number, and L＞1), multiple row is parallel to each other and respectively with this fine scanning line G
1～G
LThe data line D that insulation is intersected
1～D
M(M is a natural number, and M＞1).This fine scanning line G
1～G
LWith this multi-column data line D
1～D
MThis liquid crystal panel 12 is divided into a plurality of pixels 127.Each pixel 127 comprises a thin film transistor (TFT) 121, a pixel electrode 123, one and the public electrode 125 that is oppositely arranged of this pixel electrode 123 and be sandwiched in the liquid crystal molecule between this pixel electrode 123 and this public electrode 125.The grid g of this thin film transistor (TFT) 121 and this sweep trace G
LConnect the source electrode s of this thin film transistor (TFT) 121 and this data line D
MConnect, the drain electrode d of this thin film transistor (TFT) 121 is connected with this pixel electrode 123, and the public electrode 125 of these a plurality of pixels 127 is shared.
This display control circuit 10 comprises a sequential control circuit 130.This sequential control circuit 130 is used to receive outside view data and pixel clock signal CLK; Produce a plurality of data-signals (as: RGB DATA signal), one first control signal CONT1, reach the second control signal CONT2 according to this view data correspondence; And according to corresponding one first load control signal LD1 and the one second load control signal LD2 of producing of this pixel clock signal CLK; And this first control signal CONT1, this first load control signal LD1, this second load control signal LD2 and this data-signal offered this data drive circuit 16, and this second control signal CONT2 is offered this scan drive circuit 14.This pixel clock signal CLK is the square-wave pulse signal that changes in the cycle, and supposes that its cycle is T.This pixel clock signal CLK is used for controlling this data-signal and is transferred to liquid crystal panel 12 in order.The frequency of this pixel clock signal CLK is relevant with the mode of operation of this liquid crystal panel 12, and the resolution of this liquid crystal panel 12 is high more, and the frequency of this pixel clock signal CLK is also high more.In delegation, the quantity of the pixel 127 that has in the number of the cycle T of this pixel clock signal CLK and these liquid crystal panel 12 delegation equates.This first load control signal LD1 and this second load control signal LD2 are square-wave pulse signal.
This scan drive circuit 14 receives this second control signal CONT2, and corresponding output scanning voltage, and this scanning voltage is loaded on the grid g of corresponding thin film transistor (TFT) 101 through this fine scanning line GL, and corresponding thin film transistor (TFT) 121 is opened.
This data drive circuit 16 receives this first control signal CONT1, this first load control signal LD1, this second load control signal LD2 and this a plurality of data-signals, and these a plurality of data-signals of conversion are corresponding data voltage.Wherein, this first load control signal LD1 and this second load control signal LD2 are used for outputing to as this data drive circuit 16 trigger pip of the data voltage of each row pixel 127.When this data drive circuit 16 received this first load signal LD1 or this second load control signal LD2, it exported this data voltage, and this data voltage is loaded on the source electrode s of corresponding thin film transistor (TFT) 121 through these many data line DM.If this moment, this thin film transistor (TFT) 121 was in conducting state, then this data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123.This public voltage generating circuit 18 is used for to this public electrode 125 common electric voltage (Vcom) being provided.Therefore, can produce the rotation of an electric field between this pixel electrode 123 and this public electrode 125, thereby make this liquid crystal panel 12 display images with the control liquid crystal molecule.In order to protect liquid crystal molecule can not be damaged, the direction of this electric field needs cyclical variation.
Describe for convenient; When the data voltage that is loaded into this pixel electrode 123 is higher than the common electric voltage of its public electrode 125; Defining the voltage that this pixel 127 loaded is positive polarity voltage, and the data voltage that definition is loaded into this pixel electrode 123 is the positive polarity data voltage; When the data voltage that is loaded into this pixel electrode 123 was lower than the common electric voltage of its public electrode 125, defining the voltage that this pixel 127 loaded was reverse voltage, and the data voltage that definition is loaded into this pixel electrode 123 is the negative polarity data voltage.When the absolute value of positive polarity voltage equated with the absolute value of reverse voltage, this pixel 127 showed same gray level.
See also Fig. 2, when it is this LCD 100 demonstrations one frame picture, the synoptic diagram of 127 on-load voltage polarity of its pixel.This LCD 100 adopts the work of two-wire point inversion driving mode; Promptly the polarity of capable 127 on-load voltages of pixel with each same column during 4i+2 is capable of the 4i+1 of this LCD 100 is consistent; The polarity of capable 127 on-load voltages of pixel with each same column during 4i+4 is capable of 4i+3 is consistent; And 4i+2 capable with 4i+3 capable in the polarity of 127 on-load voltages of pixel of each same column opposite, and the polarity of 127 on-load voltages of same delegation pixel of adjacent two row is opposite arbitrarily.Wherein, i is the integer more than or equal to zero.The polarity of 127 on-load voltages of each pixel is by the frame counter-rotating.
When this LCD 100 shows a frame picture; Except that the 1st row pixel 127 of this liquid crystal panel 12; The polarity of data voltage of same row pixel 127 that offers current line and previous row when this data drive circuit 26 is opposite, then defines current behavior reversal of poles row; If to offer current line identical with the polarity of the data voltage of the same row pixel 127 of previous row when this data drive circuit 26, then define the nonpolarity counter-rotating row of current behavior.
Further, for the 1st row pixel 127 of this liquid crystal panel 12, when this liquid crystal panel 12 shows the 1st frame picture, before this data drive circuit 16 output data voltages to the 1 row pixel 127, because these many data line D
MOn on-load voltage not, therefore, when the data voltage of corresponding the 1st row pixel 127 of these data drive circuit 16 outputs to these many data line D
MThe time, this data voltage is at these many data line D
MOn need rise to target data voltage gradually from 0 volt, therefore, the 1st behavior reversal of poles row of corresponding the 1st frame display frame of definition; When this liquid crystal panel 12 shows that (j is a natural number to the j frame; And j＞1) during picture; If last 1 row of corresponding j-1 frame picture is identical with the polarity of 127 loaded data voltages of same row pixel of the 1st row of corresponding j frame picture; Then define the nonpolarity counter-rotating row of the 1st behavior of corresponding j frame picture, on the contrary, then define the 1st behavior reversal of poles row of corresponding j frame picture.
Below in conjunction with the notion of reversal of poles row and nonpolarity counter-rotating row, at length introduce this first load control signal LD1 and this second load control signal LD2.This sequential control circuit 130 is according to the drive pattern of LCD and corresponding this first load control signal LD1 and this second load control signal LD2 of producing of this pixel clock signal CLK that receives thereof.This first load control signal LD1 is used to control the data voltage of the capable pixel 127 of the corresponding driving stage sex reversal of these data drive circuit 16 outputs.This second load control signal LD2 not only is used to control the corresponding data voltage that drives the pixel 127 of nonpolarity counter-rotating row of these data drive circuit 16 outputs; Also be used for this data drive circuit 16 output data voltages after the pixel 127 of reversal of poles row and at output data voltage before the pixel 127 of nonpolarity counter-rotating row, controlling this data drive circuit 16 should many data line D
MOn voltage all adjust to same predetermined voltage.This predetermined voltage should satisfy following requirement: when the corresponding positive polarity data voltage that drives the pixel 127 of nonpolarity counter-rotating row of these data drive circuit 16 outputs arrives these many data line D
MThe time, these many data line D
MOn voltage be elevated to target data voltage gradually by this predetermined voltage; On the contrary, the negative polarity data voltage that drives the pixel 127 of nonpolarity counter-rotating row when these data drive circuit 16 output correspondences arrives these many data line D
MThe time, these many data line D
MOn voltage drop to target data voltage gradually by this predetermined voltage.And then, make the data voltage of the pixel 127 that corresponding driving stage sex reversal is capable at these many data line D
MOn the data voltage of Changing Pattern and the pixel 127 of the nonpolarity counter-rotating row of corresponding driving at these many data line D
MOn the difference of Changing Pattern reduce.Correspondingly, the pixel 127 of this reversal of poles row reduces with the difference of 127 charge stored amounts of pixel of this nonpolarity counter-rotating row.Wherein, the span of this predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage and 2 volts of sums.
Further, the second output property triggering during the negative edge of the high level pulse of this first load control signal LD1 preferably indicates as first triggering indicates, and it is used to trigger the data voltage that this data drive circuit 16 is exported the pixel 127 of corresponding reversal of poles row.The rising edge of the high level pulse of this second load control signal LD2 preferably triggers first scalability that indicates as second and triggers sign, and it is used to trigger this data drive circuit 16 and begins these many data line D of adjustment
MOn the size of voltage, and the size of the width of its high level pulse is this data drive circuit 16 corresponding these many data line D of adjustment
MOn time of voltage; The first output property triggering during the negative edge of the high level pulse of this second load control signal LD2 preferably indicates as first triggering indicates, and it is used to trigger this data drive circuit 16 and stops these many data line D of adjustment
MOn voltage, and trigger the data voltage of the pixel 127 of the corresponding nonpolarity counter-rotating row of this data drive circuit 16 outputs.
Particularly, when the high level pulse of this first load control signal LD1 that receives when this data drive circuit 16 is in negative edge, this data drive circuit 16 output data voltages and through these many data line D
MBe loaded into corresponding pixel electrode 123.At this moment, the pixel electrode 123 of loading data voltage is the pixel electrode 123 of reversal of poles row.When the high level pulse of this second load control signal LD2 that receives when this data drive circuit 16 was in rising edge, this data drive circuit 16 began these many data line D of adjustment
MOn voltage, and the high level pulse of this second load control signal LD2 negative edge when arriving, should many data line D
MOn voltage all adjust to this predetermined voltage.The adjustment mode can be: will every two adjacent data line D
MBe divided into one group, 16 controls of this data drive circuit are with two data line D in every group
MShort circuit is because two adjacent data line D
MThe polarity of last loaded data voltage is opposite, therefore, shares through electric charge, makes all data line D
MOn voltage all be adjusted to this predetermined voltage.When the high level pulse of this second load control signal LD2 that receives when this data drive circuit 16 is in negative edge, the data line D of these data drive circuit 16 control phase short circuits
MBreak off each other, and these many data line D of control
MWith corresponding connections of a plurality of output pins of this data drive circuit 16 (figure does not show),, this data drive circuit 26 arrives these many data line D thereby beginning to export through these a plurality of output pins the data voltage of the pixel 127 that is used to drive nonpolarity counter-rotating row
M, and be loaded into corresponding pixel electrode 123 through this thin film transistor (TFT) 121.At this moment, the pixel electrode 123 of loading data voltage is the pixel electrode 123 of nonpolarity counter-rotating row.
In addition; Because in any delegation; The quantity of the pixel 127 that has in the number of cycles of this pixel clock signal CLK and these liquid crystal panel 12 delegation equates; And this first, second load control signal LD1, LD2 are the pulse signal of the data voltage of the pixel 127 of these data drive circuit 16 corresponding reversal of poles row of output of control and nonpolarity counter-rotating row; Therefore, the width between any two adjacent high level pulses of each load control signal LD1, LD2 all is the integral multiple of the cycle T of this pixel clock signal CLK.Correspondingly; According to the size of the cycle T of this pixel clock signal, the width of the width of per two adjacent high level pulses of the width of the high level pulse of this first, second load control signal LD1, LD2, this first load control signal LD1 and per two adjacent high level pulses of this second load control signal LD2 all is adopted as what of cycle T of this pixel clock signal and doubly representes.
This sequential control circuit 130 is according to the width of per two adjacent high level pulses of the width of per two adjacent high level pulses of the width of the high level pulse of cycle of this pixel clock signal CLK, this first, second load control signal LD1, LD2, this first load control signal LD1 and this second load control signal LD2, and then corresponding this first, second load control signal LD1, the LD2 of producing.
Type of drive for the counter-rotating of two-wire point; This sequential control circuit 130 is given this data drive circuit 16 through this second load control signal of output LD2; And then make this data drive circuit 16 under the control of the high level pulse of this second load control signal LD2, can either realize these many data line D
MOn voltage adjust, also can realize exporting the data voltage of the pixel 127 that drives nonpolarity counter-rotating row.Further; For other not mentioned in this manual inversion driving mode (inversion driving mode that is limited to the branch that reversal of poles row and nonpolarity counter-rotating row are arranged); Inner parameter through this sequential control circuit 130 of artificial adjustment; Can make this sequential control circuit 130 produce the corresponding second load control signal LD2 of inversion driving mode that is adopted with this LCD 100; This data drive circuit 16 can either be realized these many data line D under the control of this corresponding second load control signal LD2 equally
MOn voltage adjust, also can realize exporting the data voltage of the pixel 127 that drives nonpolarity counter-rotating row.And then when this LCD 100 showed same grey menu, 127 charge stored amounts of each row pixel were basic identical.Thereby, reduce the film flicker phenomenon of this LCD 100.
Please consult Fig. 3 simultaneously, it is the driving sequential chart of this LCD 100.Show that with this LCD 100 same grey menu is an example, its principle of work is following:
This public voltage generating circuit 18 continues outputting common voltage to this public electrode 125.
The sequential control circuit 130 of this display control circuit 10 receives outside picture signal and pixel clock signal CLK, and a plurality of data-signals of corresponding output, the first control signal CONT1, the second control signal CONT2, the first load control signal LD1 and the second load control signal LD2.Wherein, the width of the high level pulse of this second load control signal LD2 is preferably 30T.Because the size of the width of the high level pulse of this first load control signal LD1 is for this data drive circuit 16 this data line of adjustment D
MOn voltage and inoperative, therefore, the width of the high level pulse of this first load control signal LD1 and identical the getting final product of width of the high level pulse of load control signal of the prior art.
This scan drive circuit 14 receives this second control signal CONT2, and corresponding output scanning voltage, and this scanning voltage is through this fine scanning line G
LBe loaded on the grid g of corresponding thin film transistor (TFT) 101, corresponding thin film transistor (TFT) 121 is opened.
This data drive circuit 16 receives this first control signal CONT1, this first load control signal LD1 and this second load control signal LD2 and this a plurality of data-signals, and changes the data voltage of these a plurality of data-signals for correspondence.What receive when this data drive circuit 16 is the high level pulse of this first load control signal LD1 and this first load control signal LD1 when being in negative edge, and the data voltage that these data drive circuit 16 outputs are used for the capable pixel of driving stage sex reversal 127 is to these many data line D
M, these many data line D
MOn voltage begin to taper to target data voltage.Wherein, these many data line D
MOn a certain moment of voltage in the process that gradually changes, the scanning voltage of this scan drive circuit 14 output gate turn-on is given corresponding sweep trace G
L, make and this sweep trace G
LThin film transistor (TFT) 121 conductings that are connected, then these many data line D
MOn data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123.After the data voltage loaded on this pixel electrode 123, the scanning voltage that these scan drive circuit 14 output grids end is given this corresponding sweep trace G
L, make and this sweep trace G
LThe thin film transistor (TFT) 121 that is connected ends.What receive when this data drive circuit 16 is the high level pulse of this second load control signal LD2 and this second load control signal LD2 when being in rising edge, and this data drive circuit 16 begins these many data line D of adjustment
MOn voltage, and when the high level pulse of this second load control signal LD2 is in negative edge, make these many data line D
MOn voltage all reach same predetermined voltage, and when the high level pulse of this second load control signal LD2 is in negative edge, these data drive circuit 16 outputs are used to drive the data voltage of pixel 127 of corresponding nonpolarity counter-rotating row to these many data line D
M, these many data line D
MOn voltage taper to required target data voltage equally.If this moment, this thin film transistor (TFT) 121 was in open mode, then this data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123, thereby this liquid crystal panel 12 realizes that picture shows.Wherein, can find out, after a certain pixel 127 of reversal of poles row is applied in the data voltage of positive polarity, apply the data line D of pixel 127 corresponding connections of the data voltage of positive polarity with this by the waveform of the data voltage among Fig. 3
MOn voltage at first drop to this predetermined voltage, when the pixel 127 of next nonpolarity counter-rotating row is recharged, begin to rise to target data voltage then again.On the contrary, this data line D
MOn voltage at first rise to this predetermined voltage, and then drop to target data voltage.
Because the data drive circuit 16 of this LCD 100 is after output is used for the data voltage of the capable pixel of driving stage sex reversal 127, and be used to drive in output before the data voltage of pixel 127 of nonpolarity counter-rotating row, should many data line D
MOn voltage all adjust to same predetermined voltage, promptly for the pixel 127 of nonpolarity counter-rotating row, its charging voltage also as the charging voltage of the pixel 127 of reversal of poles row, has the process that gradually changes.Therefore; The charging voltage of the pixel 127 of corresponding nonpolarity counter-rotating row is reduced; And then make that for same grey menu, 127 charge stored amounts of pixel difference of reversal of poles row and nonpolarity counter-rotating row reduces, thereby phenomenon of picture flicker when improving these LCD 100 display images.
Yet, in above-mentioned embodiment,, still still have the problem of flicker though scintillation is improved to a great extent.Above-mentioned LCD 100 is to utilize the high level pulse of the second load control signal LD2 to realize discharging and recharging of data voltage; And the width of the high level pulse of this second load control signal LD2 is fixed, but the frame rate of external image signal and disunity.For different frame rates, the cycle of this pixel clock signal CLK is different, and for different frame rates, these many data line D
MOn the speed that discharges and recharges of data voltage can be different.Wherein, along with the increase of frame rate, these many data line D
MOn voltage charging slack-off to the speed of target data voltage, and also slack-off through two data line short circuits being made target data voltage discharge into the speed of this predetermined voltage.Therefore, if for different frame rates, the width of the high level pulse of the second load control signal LD2 of these sequential control circuit 130 outputs is all identical, for the picture signal of higher frame rate, and the data line D of the mutual short circuit that this data drive circuit 16 is controlled
MOn voltage when not reaching this predetermined voltage, just finish discharge.Correspondingly; The pixel 127 of this reversal of poles row still exists than evident difference with the charging voltage of the pixel 127 of this nonpolarity counter-rotating row; And then for the picture signal of different frame rates, the user can see that still there is phenomenon of picture flicker in this LCD 100.Particularly the developing direction of following LCD will trend towards 120HZ and 60HZ; Even one LCD have two or more refreshing frequencys; As; (user just sees phenomenon of picture flicker more easily for Motion Estimate/Motion Compensation, the ME/MC) LCD of technology to adopt moving estimation/motion compensation.
In order to make that this LCD 100 can both have good display for the picture signal of different frame rates, reduce phenomenon of picture flicker, the embodiment of said LCD below the present invention further proposes.
See also Fig. 4, it is the structural representation of LCD second embodiment of the present invention.This LCD 200 comprises the sweep trace G ' that a display control circuit 20, a liquid crystal panel 22, scan driving circuit 24, a data drive circuit 26, a public voltage generating circuit 28, multirow are parallel to each other
1～G '
L(L is a natural number, and L＞1), multiple row is parallel to each other and respectively with this fine scanning line G '
1～G '
LThe data line D ' that insulation is intersected
1～D '
M(M is a natural number, and M＞1).This fine scanning line G '
1～G '
LWith this multi-column data line D '
1～D '
MThis liquid crystal panel 22 is divided into a plurality of pixels 227.Each pixel 227 comprises a thin film transistor (TFT) 221, a pixel electrode 223, one and the public electrode 225 that is oppositely arranged of this pixel electrode 223 and be sandwiched in the liquid crystal molecule between this pixel electrode 223 and this public electrode 225.The grid g ' of this thin film transistor (TFT) 221 and this sweep trace G '
LConnect the source electrode s ' of this thin film transistor (TFT) 221 and this data line D '
MConnect, the drain electrode d ' of this thin film transistor (TFT) 221 is connected with this pixel electrode 223, and the public electrode 225 of these a plurality of pixels 227 is shared.
Wherein, this liquid crystal panel 20, this scan drive circuit 24, this data drive circuit 26, this public voltage generating circuit 28, this fine scanning line G '
1～G '
L, this multi-column data line D '
1～D '
MAnd the structure of this pixel 227 is all corresponding with function and liquid crystal panel 10, scan drive circuit 14, data drive circuit 16, public voltage generating circuit 18, the fine scanning line G of the liquid of first embodiment
1～G
L, multi-column data line D
1～D
MAnd the structure of pixel 127 is identical with function, and therefore, structure and function about said modules repeat no more here.
The display control circuit 20 of this LCD 200 further comprises a frequency detector 210 and a storer 220.This storer 220 comprises a look-up table 222, and this look-up table 222 stores different frame rates, and and the width of the high level pulse of the corresponding first load signal LD1 ' of each frame rate and the second load signal LD2 '.Wherein, the width of the high level pulse of this first load signal LD1 ' and the second load signal LD2 ' adopts the multiple in the cycle of pixel clock signal CLK ' to represent.This frequency detector 210 is used to detect the frame rate of the external image signal that this display control circuit 20 received, and the corresponding frame rate that will detect is exported to this sequential control circuit 230.This sequential control circuit 230 is according to the frame rate that receives; Correspondence is searched in this look-up table 222 width with the high level pulse of corresponding first, second load signal of the frame rate LD1 ' that receives, LD2 '; And according to the width between per two adjacent high level pulses of the size in cycle of corresponding pixel clock signal CLK ', this first load signal LD1 ', and per two adjacent high level pulses of this second load signal LD2 ' between width, corresponding this first load control signal LD1 ' and this second load control signal LD2 ' of generating.Wherein, the second output property triggering during the negative edge of the high level pulse of this first load control signal LD1 ' preferably indicates as first triggering indicates; The negative edge of the high level pulse of this second load control signal LD2 ' preferably triggers the first output property triggering that indicates as first and indicates; The rising edge of the high level pulse of this second load control signal LD2 ' preferably triggers first scalability that indicates as second and triggers sign.
For different frame rates, the width of the high level pulse of this second load control signal LD2 ' is different, and increases along with the increase of frame rate; For same frame rate, the width of the high level pulse of this second load control signal LD2 ' is identical.Because this first load control signal LD1 ' is to this data drive circuit 26 these many data line D ' of adjustment
MOn voltage and inoperative, therefore, for same frame rate and different frame rates, the width of the high level pulse of this first load control signal LD1 ' can be all identical, also can be different.Easy for calculating, for same frame rate and different frame rates, select the width of high level pulse of this first load control signal LD1 ' all identical.
In addition, with T ' remarked pixel clock signal clk ' the size in cycle.Because the width of the high level pulse of this first, second load control signal LD1 ', LD2 ' all adopts the multiple in the cycle of this pixel clock signal CLK ' to represent; And the cycle of the pixel clock signal CLK ' that this display control circuit 20 receives reduces along with the increase of frame rate; Therefore; For the second load control signal LD2 ', the width that is stored in the high level pulse of the second load control signal LD2 ' in this look-up table 222 increases with respect to the increase along with frame rate of the multiple in the cycle of pixel clock signal CLK '.
Seeing also Fig. 5, is the synoptic diagram of this look-up table 222.For clear more the present invention is described compactly, existing frame rate with the picture signal that is transferred to this LCD 200 respectively is that 60HZ and 75HZ are that example describes.When this LCD 200 shows same grey menu; For the difference of 227 charge stored amounts of pixel of making reversal of poles row and nonpolarity counter-rotating row reduces; Through repeatedly measuring; When frame rate was 60HZ, the width of the high level pulse of this second load control signal LD2 ' was preferably 25T '.When frame rate was 75HZ, the width of the high level pulse of this second load control signal LD2 ' was preferably 35T '.And for this frame rate 60HZ and 75HZ, the width of the high level pulse of this first load control signal LD1 ' all is chosen as 30T '.Then with this frame rate 60HZ and 70HZ, and the width of the high level pulse of this first, second load control signal LD1 ', LD2 ' is stored in this look-up table 222 in advance.
See also Fig. 6, Fig. 6 is the process flow diagram of this LCD 200 driving method of film flicker phenomenon when improving display image.This driving method comprises the steps:
Step S1: receive picture signal and pixel clock signal CLK ';
Step S2: the frame rate of detecting this picture signal;
Step S3: according to the frame rate that detects, correspondence is searched in the look-up table 222 width with the high level pulse of the width of the high level pulse of the corresponding first load control signal LD1 ' of frame rate that detects and the second load control signal LD2 ';
Step S4: based on the width of the high level pulse of the width of the high level pulse of the width between per two adjacent high level pulses of the width between per two adjacent high level pulses of the size in cycle of this pixel clock signal CLK ', the first load control signal LD1 ', the second load control signal LD2 ', the first load control signal LD1 ' that finds and the second load control signal LD2 '; Corresponding the generation first load control signal LD1 ' and the second load control signal LD2 ', and export this first load control signal LD1 ' and arrive data drive circuit 26 with this second load control signal LD2 ';
Step S5: this data drive circuit 26 receives this load control signal LD1 ' and this second load control signal LD2 '; The negative edge of the high level pulse of this load control signal LD1 ' triggers the data voltage that these data drive circuit 26 outputs drive the pixel 227 of corresponding reversal of poles row, and the rising edge of the high level pulse of this second load control signal LD2 ' triggers this data drive circuit 26 and begins these many data line D ' of adjustment
MOn voltage, and when the negative edge of the high level pulse of this second load control signal LD2 ' arrives, should many data line D '
MOn voltage all adjust to predetermined voltage, next, the negative edge of the high level pulse of this second load control signal LD2 ' triggers the data voltage that these data drive circuit 26 outputs drive the pixel 227 of corresponding nonpolarity counter-rotating row.
Please consult Fig. 7 and Fig. 8 in the lump, Fig. 7 is the driving sequential chart of the refreshing frequency of this LCD 200 when being 60HZ.Fig. 8 is the driving sequential chart of the refreshing frequency of this LCD 200 when being 75HZ.Show that with this LCD 200 same grey menu is an example, the driving method that specifies this LCD 200 is following:
This display control circuit 20 receives outside picture signal and pixel clock signal CLK '; The frame rate of these frequency detector 210 these picture signals of detecting; When its frame rate that detects is 60HZ; This sequential control circuit 230 search in this look-up table 222 with frame rate be that the width of the high level pulse of the corresponding first load control signal LD1 ' of 60HZ is 30T '; The width of the high level pulse of this second load control signal LD2 ' is 25T '; Corresponding then this first load control signal of generation LD1 ' and this second load control signal LD2 ', and export this first load control signal LD1 ' and arrive this data drive circuit 26 with this second load control signal LD2 '.
When the frame rate that detects this picture signal when this frequency detector 210 is 75HZ; This sequential control circuit 230 search in this look-up table 222 with frame rate be that the width of the high level pulse of the corresponding first load control signal LD1 ' of 75HZ is 30T '; The width of the high level pulse of this second load control signal LD2 ' is 35T '; Corresponding then this first load control signal of generation LD1 ' and this second load control signal LD2 ', and export this first load control signal LD1 ' and arrive this data drive circuit 26 with this second load control signal LD2 '.
In addition, this sequential control circuit 230 also exports one first control signal CONT1 ' and data-signal (as: RGB DATA ') arrives this data drive circuit 26, and exports one second control signal CONT2g ' to this scan drive circuit 24.These data drive circuit 26 these data-signals of conversion are corresponding data voltage and export this data voltage to these many data line D '
M, when the scanning voltage of these scan drive circuit 24 outputs passes through this sweep trace G '
NBe loaded on the grid g ' of corresponding thin film transistor (TFT) 221, when corresponding thin film transistor (TFT) 221 was opened, these a plurality of data voltages were through these many data line D '
MBe loaded on the pixel electrode 223 of corresponding pixel 227.Simultaneously, public voltage generating circuit 28 continues outputting common voltage to the public electrode 225 of this corresponding pixel 227, thereby liquid crystal panel 22 realizes that picture shows.
Wherein, When the high level pulse of this first load control signal LD1 ' that receives when this data drive circuit 26 was initially located in negative edge, this data drive circuit 26 began to export the data voltage of the pixel 227 that is used to drive corresponding reversal of poles row to this multi-column data line D '
M, and the high level pulse of this second load control signal LD2 ' that receives when this data drive circuit 26 is when being initially located in rising edge, these data drive circuit 26 controls make every two adjacent data line D '
MShort circuit, and then, these many data line D '
MBegin discharge, and when the high level pulse of this second load control signal LD2 ' is initially located in negative edge, the data line D ' of these data drive circuit 26 control phase short circuits
MBreak off each other, and these many data line D ' of control
MWith the corresponding connection of a plurality of output pins (figure does not show) of this data drive circuit 26, at this moment, these many data line D '
MOn voltage all be same predetermined voltage.In addition, under the triggering of the negative edge of the high level pulse of this second load control signal LD2 ', this data drive circuit 26 is used to drive the data voltage of the pixel 227 of nonpolarity counter-rotating row through its a plurality of output pins outputs.Wherein, the span of this predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage and 2 volts of sums.
For different frame rates; The width of each high level pulse through adjusting this second load control signal LD2 '; Thereby make this data drive circuit 26 after output is used for the data voltage of the capable pixel of driving stage sex reversal 227; And be used to drive in output before the data voltage of pixel 227 of nonpolarity counter-rotating row, can control this data drive circuit 26 should many data line D '
MOn voltage all adjust to this predetermined voltage, thereby make the data voltage of data voltage and the pixel 227 that drives nonpolarity counter-rotating row of the pixel 227 that the driving stage sex reversal is capable at data line D '
MOn Changing Pattern be tending towards identical.Therefore; When this thin film transistor (TFT) 221 received the scanning voltage of gate turn-on, the quantity of electric charge of pixel 227 that stores the reversal of poles row into was with to store the quantity of electric charge of nonpolarity counter-rotating row into basic identical, and then; For different frame rates, these LCD 200 film flicker phenomenons are less.
Because the frame rate of 20 pairs of picture signals that receive of this display control circuit is detected; For different frame rates; Its width of high level pulse of the second load control signal LD2 ' that outputs to this data drive circuit 26 is different; And increase along with the increase of frame rate, to control this data drive circuit 26 before output data voltage arrives the pixel 227 of nonpolarity counter-rotating row, should many data line D '
MOn voltage all be adjusted into this predetermined voltage, and then make the data voltage of data voltage and the pixel 227 of corresponding reversal of poles row of pixel 227 of corresponding nonpolarity counter-rotating row at these many data line D '
MOn the Changing Pattern basically identical, thereby make that 227 charge stored amounts of pixel of this reversal of poles row and this nonpolarity counter-rotating row are basic identical.Therefore, this LCD 200 when receiving the picture signal of different frame frequency, phenomenon of picture flicker in the time of can both improving its display image.
For above-mentioned LCD 200; Because this first load control signal LD1 ' is also inoperative for the adjustment of this predetermined voltage; Therefore; For different frame rates, the width of the high level pulse of stored this first load control signal of correspondence formation LD1 ' also can be not limited to 30T ' in this look-up table 222.Equally, the width of the high level pulse of this second load control signal LD2 ' also can be other numerical value.For a person skilled in the art, because the different and corresponding experiments of measuring condition of the relevant configuration of LCD is different, all possibly cause testing the different clock quantity of clock quantity that draws with the record of this case instructions.Therefore, can not exceed with the numerical value of this instructions record.
See also Fig. 9, Fig. 9 is the driving sequential chart of LCD the 3rd embodiment of the present invention.This LCD (figure does not show) is roughly the same with the structure of this LCD 200, and its difference only is: for same frame rate, the sequential control circuit of the LCD of the 3rd embodiment only produces a load control signal LD "." the control data driving circuit was all adjusted to predetermined voltage with the voltage on these many data lines to this load control signal LD before the data voltage of the pixel of the every row of output.This load control signal LD " the rising edge of high level pulse trigger this data drive circuit the voltage on these many data lines adjusted; and at this load control signal LD " the negative edge of high level pulse when arriving, the voltage on these many data lines is adjusted to this predetermined voltage.And at this load control signal LD " the negative edge of high level pulse trigger down the data voltage of the pixel of this data drive circuit output driving corresponding line.
Wherein, Export before the data voltage of the capable pixel of driving stage sex reversal this load control signal LD in advance at this data drive circuit " being used for triggering the voltage of this data drive circuit on will these many data lines adjusts to the rising edge of the high level pulse of predetermined voltage and preferably triggers second scalability that indicates as second and trigger and indicate; This load control signal LD " is used for triggering this data drive circuit and exports the second output property triggering sign that the negative edge of the data voltage of the capable pixel of driving stage sex reversal preferably indicates as first triggering; Export before the data voltage of the pixel that drives nonpolarity counter-rotating row this load control signal LD in advance " being used for triggering the voltage of this data drive circuit on will this many data lines adjusts to the rising edge of the high level pulse of predetermined voltage and preferably triggers first scalability that indicates as second and trigger sign at this data drive circuit; This load control signal LD " is used for triggering this data drive circuit and exports the first output property triggering sign that the negative edge of the data voltage of the pixel that drives nonpolarity counter-rotating row preferably indicates as first triggering.
The present invention is not limited to above-mentioned embodiment, and the type of drive of this LCD 100,200 can also add some inversion driving mode of two lines etc. for one.Wherein, This one add two lines the some inversion driving mode be: the polarity of voltage that the 4i+2 of this LCD 100,200 same row pixel 127,227 capable and during 4i+3 is capable is loaded is identical; The polarity of capable 127,227 on-load voltages of same row pixel with during 4i+4 is capable of 4i+1 is identical; And the capable polarity with same row pixel 127,227 on-load voltages of 4i+3 in capable of 4i+2 is opposite, and 127,227 on-load voltage polarity of pixel of the same delegation of adjacent two row are opposite arbitrarily.The polarity of 127,227 on-load voltages of each pixel is by the frame counter-rotating.Wherein, i is the integer more than or equal to zero.
This LCD 100,200 can adopt the every triplex row of polarity or more the some inversion driving mode and two row or the capable inversion driving modes of multirow of multirow.
In a kind of change embodiment; This sequential control circuit 130 is according to the size of the cycle T of the drive pattern of this LCD 100 and this pixel clock signal CLK; Correspondence only produces a load control signal LD, and the waveform of this load control signal LD is specifically shown in figure 10.In fact, this load control signal LD is the first load control signal LD1 and the second load control signal LD2 signal after synthetic.Therefore; This data drive circuit 16 is according to this load control signal LD; Both can be corresponding the data voltage of output polarity counter-rotating row and the pixel 127 of nonpolarity counter-rotating row, also can be before the data voltage of the pixel 127 of the nonpolarity counter-rotating row of output in advance, should many data line D
MOn voltage all adjust to this predetermined voltage.
Similar with above-mentioned change embodiment; In another kind change embodiment; For the picture signal of same frame rate, this sequential control circuit 230 also only produces a load control signal LD ' according to this LCD 200, and the waveform of this load control signal LD ' is specifically shown in figure 11.Frame rate with 75HZ is an example, and this load control signal LD ' is the signal after the first load control signal LD1 ' shown in Fig. 8 synthesizes with the second load control signal LD2 '.For different frame rates, this sequential control circuit 230 produces different load control signal LD ', wherein, along with the increase of frame rate, these many data line D ' of this load control signal LD ' control adjustment
MOn voltage to the width of the high level pulse of this predetermined voltage also along with increase so that for same grey menu, the stored quantity of electric charge of the pixel of corresponding reversal of poles row and nonpolarity counter-rotating row 227 is basic identical.
See also Figure 12, it is the driving sequential chart of this LCD 200 another embodiment.For different frame rates, this predetermined voltage also can be for differing less and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltage with this common electric voltage.When the data voltage of these data drive circuit 26 preparatory output cathode property before the pixel 227 of this nonpolarity counter-rotating row, the data line D ' that it will be connected with the pixel 227 of the data voltage of this prestrain positive polarity
MOn voltage all adjust to this positive polarity predetermined voltage; On the contrary, this data drive circuit 26 data line D ' that will be connected with the pixel 227 of the data voltage of prestrain negative polarity
MOn voltage all adjust to this negative polarity predetermined voltage.Wherein, the span of this positive polarity predetermined voltage is: more than or equal to common electric voltage and less than common electric voltage and 2 volts of sums; The span of this negative polarity predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage.
Equally, for this LCD 100, this predetermined voltage also can be for differing less and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltage with this common electric voltage.
See also Figure 13, it is the driving sequential chart of this LCD 200 another embodiment.For different frame rates; The rising edge of the high level pulse of this first load control signal LD1 ' can substitute its negative edge and trigger the second output property triggering sign that indicates as first, in order to trigger the data voltage that these data drive circuit 26 outputs drive the pixel 227 of corresponding reversal of poles row.Frame rate with 60HZ is an example, and when the high level pulse of this first load control signal LD1 ' that receives when this data drive circuit 26 was in rising edge, 26 output data voltages of this data drive circuit were to the pixel 227 of corresponding reversal of poles row.
Equally, for this LCD 100, the rising edge of the high level pulse of this first load control signal LD1 also can substitute its negative edge, in order to trigger the data voltage that these data drive circuit 16 outputs drive the pixel 127 of corresponding reversal of poles row.
This predetermined voltage also can be preferably ground voltage.
In addition; Except that the rising edge or negative edge of the high level pulse of first, second load control signal, first described in this case triggers and indicates and second trigger that to indicate also can be other locational points or one section pulse of first, second load control signal.
Claims (17)
1. LCD, it comprises:
Liquid crystal panel; It comprises the multi-strip scanning line, many data wires that intersect with the insulation of this multi-strip scanning line and a plurality of pixels that defined by this multi-strip scanning line and these many data wires, and these a plurality of pixels are divided into the pixel of polarity inversion row and the pixel of nonpolarity counter-rotating row based on type of drive;
Display control circuit, it receives picture signal and generates clock signal and data-signal according to this picture signal;
Data drive circuit, its this clock signal of reception and this data-signal are to form a plurality of data voltages;
It is characterized in that: this data drive circuit is before output drives the data voltage of the pixel of nonpolarity counter-rotating row in advance; Voltage on these many data lines is all adjusted to predetermined voltage; So that for same grey menu, the pixel of this reversal of poles row institute charge stored amount is regarded as identical with the pixel institute charge stored amount of this nonpolarity counter-rotating row.
2. LCD as claimed in claim 1; It is characterized in that: also output load control signal of this display control circuit is to this data drive circuit; This load control signal has a plurality of first and triggers sign and a plurality of second triggering sign; This a plurality of first trigger to indicate to be divided into and a plurality ofly is used to trigger that the first output property triggering of data voltage that this data drive circuit output drives the pixel of nonpolarity counter-rotating row indicates and a plurality of second output property triggering that is used to trigger the data voltage of the capable pixel of this data drive circuit output driving stage sex reversal indicates; This second triggering indicates and comprises that a plurality of first scalability trigger sign; Each first output property triggering indicates respectively corresponding one first scalability triggering and indicates; These a plurality of first scalability trigger to indicate and were used for before this data drive circuit is exported the data voltage of the pixel that drives nonpolarity counter-rotating row in advance; Trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage; Wherein, this first scalability trigger indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this first output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the pixel of the nonpolarity counter-rotating row of driving.
3. LCD as claimed in claim 2 is characterized in that: this data drive circuit is before the data voltage of the pixel that in advance output driving stage sex reversal is capable, and the voltage on also will these many data lines is all adjusted to this predetermined voltage.
4. LCD as claimed in claim 3; It is characterized in that: this second triggering indicates and comprises that further a plurality of second scalability trigger sign; Each second output property triggering indicates respectively corresponding one second scalability triggering and indicates; These a plurality of second scalability trigger to indicate and were used for before this data drive circuit is exported the data voltage of the capable pixel of driving stage sex reversal in advance; Trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage; Wherein, this second scalability trigger indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this second output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the capable pixel of driving stage sex reversal.
5. LCD as claimed in claim 2; It is characterized in that: this load control signal is a square-wave pulse signal; This first output property triggering is denoted as the negative edge of the high level pulse of this load control signal; This second output property triggering is denoted as the negative edge of the high level pulse of this load control signal; This first scalability triggers the rising edge of the high level pulse that is denoted as this load control signal, and wherein, the width of the high level pulse of this load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to this predetermined voltage.
6. LCD as claimed in claim 2; It is characterized in that: this load control signal is a square-wave pulse signal; This first output property triggering is denoted as the negative edge of the high level pulse of this load control signal; This second output property triggering is denoted as the rising edge of the high level pulse of this load control signal; This first scalability triggers the rising edge of the high level pulse that is denoted as this load control signal, and wherein, the width of the high level pulse of this load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to this predetermined voltage.
7. LCD as claimed in claim 4; It is characterized in that: this load control signal is a square-wave pulse signal; This first output property triggering is denoted as the negative edge of the high level pulse of this load control signal; This second output property triggering is denoted as the negative edge of the high level pulse of this load control signal; This first scalability triggers the rising edge of the high level pulse that is denoted as this load control signal; This second scalability triggers the rising edge of the high level pulse that is denoted as this load control signal, and wherein, the width of the high level pulse of this load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to this predetermined voltage.
8. LCD as claimed in claim 2; It is characterized in that: this load control signal comprises one first load control signal and one second load control signal; This first load control signal and this second load control signal all are square-wave pulse signal; Wherein, This first output property triggering is denoted as the negative edge of the high level pulse of this second load control signal; This second output property triggering is denoted as the negative edge of the high level pulse of this first load control signal, and this first scalability triggers the rising edge of the high level pulse that is denoted as this second load control signal, and the width of the high level pulse of this second load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to predetermined voltage.
9. LCD as claimed in claim 2; It is characterized in that: this load control signal comprises one first load control signal and one second load control signal; This first load control signal and this second load control signal all are square-wave pulse signal; Wherein, This first output property triggering is denoted as the negative edge of the high level pulse of this second load control signal; This second output property triggering is denoted as the rising edge of the high level pulse of this first load control signal, and this first scalability triggers the rising edge of the high level pulse that is denoted as this second load control signal, and the width of the high level pulse of this second load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to this predetermined voltage.
10. LCD as claimed in claim 4; It is characterized in that: this load control signal comprises one first load control signal and one second load control signal; This first load control signal and this second load control signal all are square-wave pulse signal; Wherein, This first output property triggering is denoted as high level pulse following to the edge of this second load control signal; This second output property triggering is denoted as the negative edge of the high level pulse of this first load control signal; This first scalability triggers the rising edge of the high level pulse that is denoted as this second load control signal, and this second scalability triggers the rising edge of the high level pulse that is denoted as this first load control signal, and the width of the high level pulse of this first load control signal, second load control signal is the time of the voltage on these these many data lines of data drive circuit adjustment of control to this predetermined voltage.
11. LCD as claimed in claim 4; It is characterized in that: the frame rate of this this picture signal of display control circuit detecting; For same frame rate; The width of the high level pulse of this load control signal is identical, and for different frame rates, the width of the high level pulse of this load control signal is different.
12. LCD as claimed in claim 11 is characterized in that: for different frame rates, the width of the high level pulse of this load control signal increases along with the increase of frame rate.
13. like any described LCD among the claim 8-9; It is characterized in that: the frame rate of this this picture signal of display control circuit detecting; For same frame rate; The width of the high level pulse of this second load control signal is identical, and for different frame rates, the width of the high level pulse of this second load control signal is different.
14. LCD as claimed in claim 13 is characterized in that: for different frame rates, the width of the high level pulse of this second load control signal increases along with the increase of frame rate.
15. LCD as claimed in claim 1; It is characterized in that: this LCD further comprises a public voltage generating circuit; This public voltage generating circuit provides common electric voltage to arrive this a plurality of pixels, and this predetermined voltage is more than or equal to the difference of common electric voltage and 2 volts and smaller or equal to common electric voltage and 2 volts of sums; Perhaps this predetermined voltage is a ground voltage; Perhaps this predetermined voltage is opposite and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltages of two polarity; Before the data voltage of the preparatory output cathode property of this data drive circuit arrives the pixel of this nonpolarity counter-rotating row; It will all adjust to this positive polarity predetermined voltage with the voltage on the data line that the pixel of the data voltage of this prestrain positive polarity is connected; On the contrary; This data drive circuit will all be adjusted to this negative polarity predetermined voltage with the voltage on the data line that the pixel of the data voltage of prestrain negative polarity is connected; Wherein, this positive polarity predetermined voltage is greater than common electric voltage and smaller or equal to common electric voltage and 2 volts of sums, and this negative polarity predetermined voltage is more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage.
16. like claim 8 or 9 described LCDs; It is characterized in that: this display control circuit also is used to receive a pixel clock signal; This pixel clock signal is the square-wave pulse signal that changes one-period; For different frame rates; The frequency of the pixel clock signal that this display control circuit received increases along with the increase of frame rate, and this display control circuit comprises a storer, the width of the high level pulse of this first load control signal of a plurality of different frame rates of storage and corresponding each frame rate and this second load signal in this storer; Wherein, the width of the high level pulse of this first load control signal and this second load signal is represented with the multiple in the cycle of this pixel clock signal.
17. LCD as claimed in claim 16; It is characterized in that: this display control circuit is according to the frame rate that detects; Correspondence is searched in this storer the width with the high level pulse of corresponding first load control signal of this frame rate that detects and this second load signal; And then corresponding generation first load control signal and second load control signal, and export this first load control signal and arrive this data drive circuit with this second load control signal.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839526A (en) * | 2012-11-22 | 2014-06-04 | 联咏科技股份有限公司 | Display apparatus |
| CN104766583A (en) * | 2015-04-27 | 2015-07-08 | 京东方科技集团股份有限公司 | Polarity-reversal compensation method, device and liquid crystal display |
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| US9373293B2 (en) | 2012-11-12 | 2016-06-21 | Novatek Microelectronics Corp. | Display panel and display apparatus |
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| CN112669784A (en) * | 2021-01-07 | 2021-04-16 | 三星半导体(中国)研究开发有限公司 | Liquid crystal display device and method of driving the same |
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| US9373293B2 (en) | 2012-11-12 | 2016-06-21 | Novatek Microelectronics Corp. | Display panel and display apparatus |
| CN103839526A (en) * | 2012-11-22 | 2014-06-04 | 联咏科技股份有限公司 | Display apparatus |
| WO2016090944A1 (en) * | 2014-12-08 | 2016-06-16 | Boe Technology Group Co., Ltd. | Driving method, driving circuit and display apparatus |
| US10204577B2 (en) | 2014-12-08 | 2019-02-12 | Boe Technology Group Co. Ltd. | Driving method, driving circuit and display apparatus |
| CN104766583A (en) * | 2015-04-27 | 2015-07-08 | 京东方科技集团股份有限公司 | Polarity-reversal compensation method, device and liquid crystal display |
| WO2017190428A1 (en) * | 2016-05-04 | 2017-11-09 | 深圳市华星光电技术有限公司 | Driving method for display panel and display device comprising display panel |
| CN106652931B (en) * | 2016-11-03 | 2019-05-07 | 深圳市华星光电技术有限公司 | Display driver circuit, drive control method, voltage supply chip and display equipment |
| CN106652931A (en) * | 2016-11-03 | 2017-05-10 | 深圳市华星光电技术有限公司 | Display driving circuit, driving control method, voltage supply chip and display device |
| CN106683629A (en) * | 2016-12-28 | 2017-05-17 | 武汉华星光电技术有限公司 | Liquid crystal display panel driving device and liquid crystal display panel driving method |
| CN106683629B (en) * | 2016-12-28 | 2019-10-25 | 武汉华星光电技术有限公司 | The driving device and driving method of liquid crystal display panel |
| CN110085178A (en) * | 2018-01-26 | 2019-08-02 | 乐金显示有限公司 | Liquid crystal display device and its controller and driving method |
| CN110085178B (en) * | 2018-01-26 | 2021-08-17 | 乐金显示有限公司 | Liquid crystal display device, controller thereof and driving method thereof |
| CN112735349A (en) * | 2020-12-31 | 2021-04-30 | 成都中电熊猫显示科技有限公司 | Liquid crystal display and driving method thereof |
| CN112735349B (en) * | 2020-12-31 | 2022-04-22 | 成都中电熊猫显示科技有限公司 | Liquid crystal display and driving method thereof |
| CN112669784A (en) * | 2021-01-07 | 2021-04-16 | 三星半导体(中国)研究开发有限公司 | Liquid crystal display device and method of driving the same |
| CN112669784B (en) * | 2021-01-07 | 2022-07-19 | 三星半导体(中国)研究开发有限公司 | Liquid crystal display device and method of driving the same |
| US11798513B2 (en) | 2021-01-07 | 2023-10-24 | Samsung Electronics Co., Ltd. | Liquid crystal display device and method for driving the same |
| CN114203128A (en) * | 2021-12-17 | 2022-03-18 | 武汉京东方光电科技有限公司 | Display panel driving method and circuit and display device |
| CN114203128B (en) * | 2021-12-17 | 2022-11-15 | 武汉京东方光电科技有限公司 | Display panel driving method and circuit and display device |
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