CN114188436B - Silicon substrate preparation method and solar cell - Google Patents

Silicon substrate preparation method and solar cell Download PDF

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CN114188436B
CN114188436B CN202010969860.1A CN202010969860A CN114188436B CN 114188436 B CN114188436 B CN 114188436B CN 202010969860 A CN202010969860 A CN 202010969860A CN 114188436 B CN114188436 B CN 114188436B
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silicon wafer
phosphorus
silicon substrate
phosphorus source
silicon
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CN114188436A (en
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潘强强
刘勇
朴松源
王洪喆
王路
李家栋
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Yidao New Energy Technology Co ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
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    • Y02E10/00—Energy generation through renewable energy sources
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    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

The invention provides a silicon substrate preparation method and a solar cell, and belongs to the technical field of photovoltaics. According to the preparation method of the silicon substrate, the concentration distribution of phosphorus in the silicon wafer is flexibly adjusted by diffusing phosphorus in the silicon wafer twice at different depths, at this time, the surface concentration of the silicon substrate is higher, the surface concentration decline trend is more gentle, the ohmic contact between the silicon wafer and the metal electrode is optimized, the contact resistance is reduced, and the filling factor of the solar cell based on the silicon wafer is improved; the in-vivo concentration is lower, the in-vivo recombination of the silicon wafer is reduced, and the open-circuit voltage and the short-circuit current of the solar cell based on the silicon wafer are improved; finally, the improvement does not increase the time required by the phosphorus diffusion process, does not introduce other preparation processes, is convenient to apply in the existing large-scale production, and has low improvement cost.

Description

Silicon substrate preparation method and solar cell
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a silicon substrate preparation method and a solar cell.
Background
Currently, in order to cope with the increasingly urgent energy crisis, the development of solar energy is an emerging hot spot project, wherein the preparation of high-efficiency solar cells is a key for the development of solar energy.
The silicon solar cell is a solar cell taking silicon as a matrix material, the surface concentration and junction depth of phosphorus diffusion on a silicon wafer are key to influencing the efficiency of the solar cell in the preparation process of the silicon solar cell, the surface concentration is generally higher in the phosphorus diffusion process, when good contact conditions are met, the phosphorus diffusion concentration in the silicon body is also higher, and the junction depth is influenced by a longer tailing phenomenon, so that a PN junction depletion region is wider, and the open-circuit voltage (Uoc) and the short-circuit current (Isc) of the solar cell are reduced; when the surface concentration of phosphorus diffusion is low, the phosphorus diffusion concentration in the silicon body is low, so that the ohmic contact between the silicon and the metal electrode is poor, and the Filling Factor (FF) is low.
The high-temperature tube type diffusion technology is widely used in large-scale production, and nitrogen, oxygen and phosphorus oxychloride are simultaneously introduced into a furnace tube for diffusion in the phosphorus diffusion process, so that the surface concentration and junction depth of phosphorus diffusion on a silicon wafer cannot be effectively controlled, and the conversion efficiency of the prepared solar cell is affected.
Disclosure of Invention
The invention provides a silicon substrate preparation method and a solar cell, which are used for solving the problem that the conversion efficiency of the prepared solar cell is affected because the surface concentration and junction depth of phosphorus diffusion on a silicon wafer cannot be effectively controlled in the prior art.
In a first aspect, there is provided a method for preparing a silicon substrate, the method comprising:
depositing a first phosphorus source layer on the front side of the silicon wafer;
pushing the first phosphorus source layer into the silicon wafer at a first preset temperature, and forming a phosphorus concentration distribution layer with a first preset depth in the silicon wafer;
and depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process to form a silicon substrate, wherein the second preset depth is smaller than the first preset depth.
Optionally, depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process, and after forming the silicon substrate, the method further includes:
and oxidizing the front surface of the silicon substrate at the first preset temperature to form a first oxide layer.
Optionally, after oxidizing the front surface of the silicon substrate at the first preset temperature to form a first oxide layer, the method further includes:
oxidizing the front surface of the silicon substrate at a second preset temperature to form a second oxide layer, wherein the second preset temperature is smaller than the first preset temperature.
Optionally, before oxidizing the front surface of the silicon substrate at the second preset temperature to form the second oxide layer, the method further includes:
and depositing a third phosphorus source layer on the front surface of the silicon substrate at the second preset temperature so as to diffuse the third phosphorus source layer into the first oxide layer.
Optionally, before the first phosphorus source layer is formed on the front side of the silicon wafer by deposition, the method further comprises:
oxidizing the surface of the silicon wafer at a second preset temperature to obtain a third oxide layer;
the depositing a first phosphorus source layer on the surface of the silicon wafer comprises the following steps:
and depositing and forming the first phosphorus source layer on the third oxide layer of the silicon wafer at the second preset temperature.
Optionally, the silicon wafer comprises at least one of monocrystalline silicon wafer, polycrystalline silicon wafer, microcrystalline silicon wafer, nanocrystalline silicon wafer or amorphous silicon wafer.
Optionally, the first preset temperature is at least one of 800 ℃ to 900 ℃.
Optionally, the second preset temperature is at least one of 700 ℃ to 850 ℃. Optionally, the first preset depth is any value between 200 nanometers and 400 nanometers;
the second preset depth is less than 50 nanometers.
In a second aspect, a solar cell is provided, which is characterized in that the solar cell comprises a silicon substrate prepared by the silicon substrate preparation method according to the first aspect.
Compared with the related art, the invention has the following advantages:
in the embodiment of the invention, a first phosphorus source layer is firstly deposited on the surface of a silicon wafer, the first phosphorus source layer is pushed into the silicon wafer at a first preset temperature, so that a phosphorus concentration distribution layer with a first preset depth is formed in the silicon wafer, then a second phosphorus source layer is deposited on the surface of the silicon wafer, and the second phosphorus source layer diffuses into the silicon wafer to a second preset depth at the first preset temperature, wherein the second preset depth is smaller than the first preset depth, and then the surface of the silicon wafer is oxidized at the first preset temperature, so that the first oxide layer is obtained to finish phosphorus diffusion of the silicon wafer. In the embodiment of the invention, the concentration distribution of phosphorus in the silicon wafer is flexibly adjusted by diffusing phosphorus in the silicon wafer twice at different depths, at this time, the surface concentration of the silicon substrate is higher, the surface concentration decline trend is more gentle, the in-vivo concentration is lower, the in-vivo recombination of the silicon wafer is reduced, the PN junction depletion region is narrowed, and the open-circuit voltage and the short-circuit current of the solar cell based on the silicon wafer are improved; the surface concentration is higher, the ohmic contact between the silicon chip and the metal electrode is optimized, the contact resistance is reduced, and the filling factor of the solar cell based on the silicon chip is improved; finally, the improvement does not increase the time required by the phosphorus diffusion process, does not introduce other preparation processes, is convenient to apply in the existing large-scale production, and has low improvement cost.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a flow chart of steps of a method for preparing a silicon substrate according to an embodiment of the present invention;
FIG. 2 is a flow chart of steps of another method for preparing a silicon substrate according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating steps of another method for fabricating a silicon substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an ECV (Electrochemical Capacitance-Voltage) curve according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Fig. 1 is a flowchart of steps of a method for preparing a silicon substrate according to an embodiment of the present invention, where the method may include:
and step 101, depositing and forming a first phosphorus source layer on the front surface of the silicon wafer.
In the embodiment of the invention, the first phosphorus source layer can be deposited on the front surface of the silicon wafer for subsequent diffusion, and optionally, the deposition of the first phosphorus source layer can be constant temperature deposition, variable temperature deposition and the like, and also can be one-time deposition, multiple-time deposition and the like. Because the internal concentration of phosphorus atoms near the PN junction of the silicon wafer is related to the source concentration of the first phosphorus source layer, the internal concentration of the silicon wafer after diffusion can be reduced by reducing the source concentration of the first phosphorus source layer, so that the in-vivo recombination of the silicon wafer is reduced, wherein the source concentration refers to the concentration of phosphorus oxychloride and oxygen react at high temperature to form phosphorus pentoxide. Optionally, the source concentration may be reduced by reducing the flow rate of phosphorus oxychloride, the flow rate of oxygen, or the temperature, for example, when the first phosphorus source layer is deposited by a chemical vapor deposition furnace tube, phosphorus oxychloride is in a liquid state at normal temperature, nitrogen is introduced and then bubbled to form a vapor flow into the furnace tube, and at this time, the flow rate of nitrogen may be 500sccm to 2000sccm (standard cubic centimeter per minute, standard milliliters per minute), which is not a specific limitation of the embodiment of the present invention.
In the embodiment of the invention, the reaction temperature can be raised to 700-800 ℃ and kept stable before the first phosphorus source layer is formed on the front side of the silicon wafer, so that the efficiency of depositing the first phosphorus source layer is improved, and simultaneously, in order to avoid gas overflow, all gas valves and pumps of production equipment can be closed before deposition, and leakage detection can be performed, and when the gas leakage rate is less than or equal to 3mbar/min, the first phosphorus source layer is deposited.
Step 102, pushing the first phosphorus source layer into the silicon wafer at a first preset temperature, and forming a phosphorus concentration distribution layer with a first preset depth in the silicon wafer.
In the embodiment of the invention, the first preset temperature is a high temperature range capable of enabling the phosphorus source layer to diffuse into the silicon wafer, the promotion refers to a process of diffusing phosphorus atoms on the surface layer of the silicon wafer into the silicon wafer through high temperature, the first phosphorus source layer deposited on the shallow surface layer on the front surface of the silicon wafer can be pushed into the silicon wafer under the first preset temperature through high temperature action, so that phosphorus concentration distribution with a first preset depth is formed in the silicon wafer, at the moment, the surface concentration and the internal concentration of the silicon wafer are low, and the promotion can be alternatively variable-temperature promotion, constant-temperature promotion and the like, or can be one-time promotion, multiple-time promotion and the like. The first preset depth may be a junction depth of a PN junction in a silicon wafer, alternatively, the first preset depth may be controlled by controlling a reaction time and a reaction temperature of propulsion, and requirements of solar cells with different requirements on junction depths are different, so that a person skilled in the art may select the first preset depth according to actual production requirements, which is not particularly limited in the embodiment of the present invention.
And 103, depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process, and forming a silicon substrate, wherein the second preset depth is smaller than the first preset depth.
In the embodiment of the present invention, the second phosphorus source layer may be deposited on the front surface of the silicon wafer at the first preset temperature, and because the first preset temperature is a high temperature range capable of allowing the phosphorus source layer to diffuse into the silicon wafer, the second phosphorus source layer diffuses into the silicon wafer in the process of depositing the second phosphorus source layer, and at this time, because the second preset depth is smaller than the first preset depth, in order to diffuse into the second preset depth in the phosphorus concentration distribution layer, the reaction temperature, the reaction time and the flow of the deposition gas for depositing the second phosphorus source layer in step 103 may be adjusted within the first preset temperature, and are smaller than at least one of the reaction temperature, the reaction time and the flow of the deposition gas for depositing the first phosphorus source layer in step 101, so as to flexibly adjust the distribution of phosphorus concentration in the silicon wafer. Optionally, the reaction time in step 103 may be less than 10 minutes, so as to modify the phosphorus concentration distribution within the second preset depth on the surface of the silicon wafer, improve the surface concentration, reduce the contact resistance, enable the silicon substrate in the solar cell to form better ohmic contact with the metal electrode, and improve the filling factor.
In summary, in the embodiment of the present invention, a first phosphorus source layer is formed on the surface of a silicon wafer by deposition, the first phosphorus source layer is pushed into the silicon wafer at a first preset temperature, so as to form a phosphorus concentration distribution layer with a first preset depth in the silicon wafer, then a second phosphorus source layer is deposited on the surface of the silicon wafer, and the second phosphorus source layer diffuses into the silicon wafer at the first preset temperature to a second preset depth, wherein the second preset depth is smaller than the first preset depth, and then the surface of the silicon wafer is oxidized at the first preset temperature, so that the phosphorus diffusion of the silicon wafer is completed by the first oxide layer. In the embodiment of the invention, the concentration distribution of phosphorus in the silicon wafer is flexibly adjusted by diffusing the phosphorus in the silicon wafer twice at different depths, so that the concentration distribution of phosphorus in the silicon wafer from the surface to the inside of the silicon wafer from the second preset depth to the first preset depth is reduced, at the moment, the surface concentration of the silicon substrate is higher, the surface concentration decline trend is more gentle, the inside concentration is lower, the inside recombination of the silicon wafer is reduced, the PN junction depletion region is narrowed, and the open-circuit voltage and the short-circuit current of the solar cell based on the silicon wafer are improved; the surface concentration is higher, the ohmic contact between the silicon chip and the metal electrode is optimized, the contact resistance is reduced, and the filling factor of the solar cell based on the silicon chip is improved; finally, the improvement does not increase the time required by the phosphorus diffusion process, does not introduce other preparation processes, is convenient to apply in the existing large-scale production, and has low improvement cost.
Fig. 2 is a flowchart of steps of another method for preparing a silicon substrate according to an embodiment of the present invention, as shown in fig. 2, the method may include:
and step 201, depositing and forming a first phosphorus source layer on the front surface of the silicon wafer.
In the embodiment of the present invention, step 201 may correspond to the related description of step 101, and is not repeated here.
Optionally, the silicon wafer comprises at least one of monocrystalline silicon wafer, polycrystalline silicon wafer, microcrystalline silicon wafer, nanocrystalline silicon wafer or amorphous silicon wafer.
In the embodiment of the invention, the material and structure of the silicon wafer are not limited, and the silicon wafer can be one of monocrystalline silicon wafer, polycrystalline silicon wafer, microcrystalline silicon wafer, nanocrystalline silicon wafer or amorphous silicon wafer, or can be a combined structure of more than two of the above examples, and the embodiment of the invention is not particularly limited.
Step 202, pushing the first phosphorus source layer into the silicon wafer at a first preset temperature, and forming a phosphorus concentration distribution layer with a first preset depth in the silicon wafer.
In the embodiment of the present invention, step 202 may correspond to the related description of step 102, and is not repeated here.
Optionally, the first preset temperature is at least one of 800 ℃ to 900 ℃.
In the embodiment of the invention, the first preset temperature can be at least one of 800 ℃ to 900 ℃, in constant-temperature propulsion, the first preset temperature can be any temperature between 800 ℃ and 820 ℃, 840 ℃, 860 ℃, 880 ℃, 900 ℃ and the like, and in variable-temperature propulsion, the first preset temperature can be a plurality of continuous or discontinuous temperatures therein, and a person skilled in the art can enable the first phosphorus source layer to propel the silicon wafer by controlling the high temperature effect of the first preset temperature, so that a phosphorus concentration distribution layer with a first preset depth is formed in the silicon wafer, and phosphorus atoms are obtained to form a phosphorus concentration distribution layer with the first preset depth in the silicon wafer.
Optionally, the first preset depth is any value between 200 nanometers and 400 nanometers
In the embodiment of the present invention, the first preset depth may refer to a PN junction depth of the silicon substrate, and may be controlled to be 200 nm to 400 nm under the influence of the reaction temperature and the reaction time, or alternatively, the first preset depth may be any value between 200 nm and 400 nm, such as 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm. .
And 203, depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process, and forming a silicon substrate, wherein the second preset depth is smaller than the first preset depth.
In the embodiment of the present invention, step 203 may correspond to the related description of step 103, and is not repeated here.
Optionally, the second preset depth is less than 50 nanometers.
In the embodiment of the invention, the second preset depth can be limited on the shallow surface layer which is 50 nanometers inward and smaller than the surface of the silicon wafer, so that when the second phosphorus source layer is deposited in the step 203 and the silicon substrate is pushed by the second phosphorus source layer, the phosphorus atom concentration from the surface of the silicon wafer to the inner shallow surface layer is only increased, the phosphorus atom concentration of the shallow surface layer is more gradually reduced, and the contact resistance of the surface of the silicon substrate is reduced while the physical recombination of the silicon wafer is reduced. The surface concentration of the shallow surface layer of the silicon wafer is required to be kept in a proper range under the influence of screen printing and sintering processes, and alternatively, the surface concentration of phosphorus atoms of the shallow surface layer can be 10 19 Cubic centimeter to 10 21 Any number between cubic centimeters.
And 204, oxidizing the front surface of the silicon substrate at the first preset temperature to form a first oxide layer.
In the embodiment of the present invention, in order to protect the surface of the silicon wafer, the front surface of the silicon substrate may be oxidized at a first preset temperature, so that a first oxide layer composed of silicon dioxide is formed on the front surface of the silicon substrate, and the first preset temperature may be correspondingly referred to the related description of the foregoing step 202, so that repetition is avoided and no further description is provided herein. In addition, the phosphorus atom concentration on the surface of the silicon substrate is too high, or dead layers can appear under the influence of dislocation and defects, the life of photo-generated carriers of the dead layers is short, recombination can occur before the photo-generated carriers are diffused to PN junctions, and the photo-generated carriers do not contribute to the cell efficiency, at the moment, the surface of the silicon is oxidized to form a first oxide layer, and a large amount of redundant phosphorus atoms on the surface of the silicon wafer can be remained in the first oxide layer to form a glass layer, so that the concentration of the surface of the silicon is prevented from being too high, and the influence of the dead layers is reduced and eliminated. In the preparation process of applying the silicon substrate to the solar cell, the first oxide layer is subjected to etching, alkali polishing and the like, and a large amount of undoped phosphorus atoms are removed while a part of the front surface of the silicon substrate is protected, so that the silicon substrate with proper surface concentration is obtained. In addition, the reaction temperature, reaction time, oxygen flow rate, etc. of the first oxidation may be adjusted according to specific process conditions.
Optionally, after the step 204, the method further includes:
and S11, oxidizing the front surface of the silicon substrate at a second preset temperature to form a second oxide layer, wherein the second preset temperature is smaller than the first preset temperature.
In the embodiment of the invention, after the temperature is reduced, the front surface of the silicon substrate is further oxidized at a second preset temperature to form a second oxide layer so as to thicken the oxide layer on the front surface of the silicon substrate, thereby protecting the front surface of the silicon substrate from being etched when the oxide layer is removed and avoiding the damage of a diffusion surface. The second preset temperature should be lower than the first preset temperature for phosphorus atom diffusion, and optionally, oxidation may be high-temperature oxidation, low-temperature oxidation, or the like, or may be primary oxidation, multiple oxidation, or the like, which is not particularly limited in the embodiment of the present invention.
Optionally, the second preset temperature is at least one of 700 ℃ to 850 ℃.
In the embodiment of the present invention, the second preset temperature should be less than the first preset temperature, alternatively, the second preset temperature may be at least one temperature between 750 ℃ and 820 ℃ such as 700 ℃, 750 ℃, 780 ℃,800 ℃, 850 ℃, and the like, and a person skilled in the art may select a suitable temperature to form the second oxide layer according to specific process conditions, practical application requirements, and the like.
Optionally, before the step S11, the method further includes:
and S21, depositing a third phosphorus source layer on the front surface of the silicon substrate at the second preset temperature so as to diffuse the third phosphorus source layer into the first oxide layer.
In the implementation of the invention, based on the application requirements of different solar cells, higher requirements may be set for the surface concentration of phosphorus atoms on the front surface of the silicon substrate, optionally, after the first oxide layer is formed, the temperature is reduced to a second preset temperature, and the third phosphorus source layer is deposited again to diffuse into the first oxide layer, that is, the reaction temperature should be lower than the first preset temperature selected in the preparation, but the phosphorus atoms still can diffuse into the silicon substrate, at this time, the phosphorus atom concentration in the first oxide layer is increased, the surface concentration of phosphorus atoms in the silicon substrate can be further increased, and the silicon substrate with higher surface concentration can be obtained after the oxide layer is removed. The second preset temperature may correspond to the related description of step S11, and is not described herein again for avoiding repetition.
In the embodiment of the present invention, the reaction time, the gas flow rate, etc. in the step S11 and the step S21 may refer to the foregoing steps, wherein the gas flow rate may be 500sccm to 2000sccm, the reaction time may be changed along with the change of the gas flow rate and the reaction temperature, and may be affected by the furnace tube pressure, or may be less than 10 minutes.
In the embodiment of the invention, a first phosphorus source layer is firstly deposited on the surface of a silicon wafer, the first phosphorus source layer is pushed into the silicon wafer at a first preset temperature, so that a phosphorus concentration distribution layer with a first preset depth is formed in the silicon wafer, then a second phosphorus source layer is deposited on the surface of the silicon wafer, and the second phosphorus source layer diffuses into the silicon wafer to a second preset depth at the first preset temperature, wherein the second preset depth is smaller than the first preset depth, and then the surface of the silicon wafer is oxidized at the first preset temperature, so that the first oxide layer is obtained to finish phosphorus diffusion of the silicon wafer. In the embodiment of the invention, the concentration distribution of phosphorus in the silicon wafer is flexibly adjusted by diffusing the phosphorus in the silicon wafer twice at different depths, so that the concentration distribution of phosphorus in the silicon wafer from the surface to the inside of the silicon wafer from the second preset depth to the first preset depth is reduced, at the moment, the surface concentration of the silicon substrate is higher, the surface concentration decline trend is more gentle, the inside concentration is lower, the inside recombination of the silicon wafer is reduced, the PN junction depletion region is narrowed, and the open-circuit voltage and the short-circuit current of the solar cell based on the silicon wafer are improved; the surface concentration is higher, the ohmic contact between the silicon chip and the metal electrode is optimized, the contact resistance is reduced, and the filling factor of the solar cell based on the silicon chip is improved; finally, the improvement does not increase the time required by the phosphorus diffusion process, does not introduce other preparation processes, is convenient to apply in the existing large-scale production, and has low improvement cost.
Fig. 3 is a flowchart of steps of another method for preparing a silicon substrate according to an embodiment of the present invention, as shown in fig. 3, the method may include:
and step 301, oxidizing the surface of the silicon wafer at a second preset temperature to obtain a third oxide layer.
In the embodiment of the invention, before the first phosphorus source layer is deposited, the surface of the silicon wafer may be oxidized to obtain the third oxide layer, and optionally, in order to avoid the influence of the thickness of the third oxide layer on the diffusion concentration and the diffusion rate of the first phosphorus source layer, the thickness of the third oxide layer may be controlled by controlling the reaction time, so that the thickness of the third oxide layer is thinner, for example, the reaction time may be less than 10 minutes. Optionally, in the process of oxidizing the surface of the silicon wafer to obtain the third oxide layer, the reaction temperature may be controlled to be a second preset temperature, and the specific second preset temperature may be correspondingly described with reference to the foregoing step S11, so that no further description is provided herein for avoiding repetition.
And 302, depositing and forming the first phosphorus source layer on the third oxide layer of the silicon wafer at the second preset temperature.
In the embodiment of the invention, the first phosphorus source layer is formed on the third oxide layer by deposition, so that phosphorus atoms are more uniformly distributed on the surface of the silicon wafer, and therefore, the first phosphorus source layer can be uniformly diffused in the silicon wafer in the process of subsequently pushing the silicon wafer, and the yield of the silicon substrate is improved.
Step 303, pushing the first phosphorus source layer into the silicon wafer at a first preset temperature, and forming a phosphorus concentration distribution layer with a first preset depth in the silicon wafer.
And 304, depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process, and forming a silicon substrate, wherein the second preset depth is smaller than the first preset depth.
In the embodiment of the present invention, steps 303 to 304 may correspond to the descriptions related to steps 102 to 103, and are not repeated here.
In the embodiment of the invention, a first phosphorus source layer is firstly deposited on the surface of a silicon wafer, the first phosphorus source layer is pushed into the silicon wafer at a first preset temperature, so that a phosphorus concentration distribution layer with a first preset depth is formed in the silicon wafer, then a second phosphorus source layer is deposited on the surface of the silicon wafer, and the second phosphorus source layer diffuses into the silicon wafer to a second preset depth at the first preset temperature, wherein the second preset depth is smaller than the first preset depth, and then the surface of the silicon wafer is oxidized at the first preset temperature, so that the first oxide layer is obtained to finish phosphorus diffusion of the silicon wafer. In the embodiment of the invention, the concentration distribution of phosphorus in the silicon wafer is flexibly adjusted by diffusing the phosphorus in the silicon wafer twice at different depths, so that the concentration distribution of phosphorus in the silicon wafer from the surface to the inside of the silicon wafer from the second preset depth to the first preset depth is reduced, at the moment, the surface concentration of the silicon substrate is higher, the surface concentration decline trend is more gentle, the inside concentration is lower, the inside recombination of the silicon wafer is reduced, the PN junction depletion region is narrowed, and the open-circuit voltage and the short-circuit current of the solar cell based on the silicon wafer are improved; the surface concentration is higher, the ohmic contact between the silicon chip and the metal electrode is optimized, the contact resistance is reduced, and the filling factor of the solar cell based on the silicon chip is improved; finally, the improvement does not increase the time required by the phosphorus diffusion process, does not introduce other preparation processes, is convenient to apply in the existing large-scale production, and has low improvement cost.
The embodiment of the invention also provides a solar cell, which comprises the silicon substrate prepared by the silicon substrate preparation method as shown in fig. 1, 2 or 3.
The invention also exemplifies the following examples to illustrate the aspects of the invention, taking the PERC (Passivated Emitter and Rear Cell, passivated emitter and back cell) process as an example:
example 1
The reaction temperature is raised to any temperature between 700 ℃ and 850 ℃ at the time of deposition and kept stable.
The gas valve and pump were closed and leak detection was continued for two minutes, with a leak rate of less than or equal to 3mbar/min being determined.
And (3) introducing nitrogen and oxygen at the temperature of 700-850 ℃ within 10 minutes at the temperature of 500-2000 sccm to oxidize the surface of the silicon wafer to form an oxide layer.
And depositing a phosphorus source layer on the front surface of the oxide layer at 700-850 ℃.
Pushing the phosphorus source layer into the silicon wafer at 800-900 ℃ to form a phosphorus concentration distribution layer of 200-400 nanometers in the silicon wafer, thereby obtaining the silicon substrate of the example 1.
Example 2
The reaction temperature is raised to any temperature between 700 ℃ and 850 ℃ at the time of deposition and kept stable.
The gas valve and pump were closed and leak detection was continued for two minutes, with a leak rate of less than or equal to 3mbar/min being determined.
And (3) introducing nitrogen and oxygen at the temperature of between 700 and 850 ℃ in a range of 500 to 2000sccm within 10 minutes to oxidize the surface of the silicon wafer, thereby forming a third oxide layer.
And depositing a first phosphorus source layer on the front surface of the third oxide layer at 700-850 ℃.
Pushing the first phosphorus source layer into the silicon wafer at 800-900 ℃ to form a phosphorus concentration distribution layer of 200-400 nanometers in the silicon wafer.
And depositing a second phosphorus source layer on the front surface of the silicon wafer within 10 minutes at 800-900 ℃ so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to within 50 nanometers in the deposition process to form the silicon substrate of example 2.
Optionally, oxygen may be introduced into the silicon substrate of example 2 at a flow rate of 500sccm to 2000sccm at 800 ℃ to 900 ℃ to form a first oxide layer on the surface of the silicon substrate.
A third phosphorus source layer is deposited on the first oxide layer of the silicon substrate at 700 to 850 ℃ for less than 10 minutes and is allowed to diffuse toward the first oxide layer.
Introducing oxygen at the temperature of 700-850 ℃ for 10 minutes at the flow rate of 500-2000 sccm, and forming a second oxide layer on the surface of the silicon substrate.
When the silicon substrate of example 2 is applied to the preparation of a solar cell, part of the first oxide layer and the second oxide layer can be removed by etching, alkali polishing and the like to remove more phosphorus atoms, and meanwhile, the residual oxide layer can protect the diffusion surface of the silicon substrate.
Fig. 4 is a schematic diagram of an ECV curve provided in the embodiment of the present invention, as shown in fig. 4, the ECV curve of the silicon substrate in example 2 changes more gradually on the shallow surface layer, and when the concentration of the surface of the shallow surface layer is higher, the internal concentration is lower, and at this time, the silicon substrate can form good ohmic contact with the metal electrode, so as to reduce the contact resistance, improve the filling factor, reduce the in vivo recombination, and improve the open circuit voltage of the solar cell. The ECV curve of the silicon substrate in example 1 has an obvious trend of decreasing from high to low in the surface concentration of the shallow surface layer, the surface concentration is low, good ohmic contact with the metal electrode cannot be formed, the in-vivo phosphorus concentration of the silicon substrate is high, the in-vivo recombination is high, and the efficiency of the solar cell is affected.
In the embodiment of the invention, the phosphorus diffusion condition can be determined through ECV curve distribution, so that the reaction time, reaction temperature, gas flow and the like of each process step are adjusted, and the phosphorus concentration of the silicon substrate is distributed in such a way that the surface concentration of the shallow surface layer is high and the descending trend is gentle, and the concentration near the PN junction in the body is low.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus and modules described above may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims (8)

1. A method of preparing a silicon substrate, the method comprising:
depositing a first phosphorus source layer on the front side of the silicon wafer;
pushing the first phosphorus source layer into the silicon wafer at a first preset temperature, and forming a phosphorus concentration distribution layer with a first preset depth in the silicon wafer;
depositing a second phosphorus source layer on the front surface of the silicon wafer, so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process to form a silicon substrate, wherein the second preset depth is smaller than the first preset depth;
and depositing a second phosphorus source layer on the front surface of the silicon wafer so that the second phosphorus source layer diffuses into the phosphorus concentration distribution layer to a second preset depth in the deposition process, and after forming the silicon substrate, further comprising:
oxidizing the front surface of the silicon substrate at the first preset temperature to form a first oxide layer;
and oxidizing the front surface of the silicon substrate at the first preset temperature to form a first oxide layer, wherein the method further comprises the following steps:
oxidizing the front surface of the silicon substrate at a second preset temperature to form a second oxide layer, wherein the second preset temperature is smaller than the first preset temperature.
2. The method of claim 1, wherein before oxidizing the front surface of the silicon substrate at the second predetermined temperature to form the second oxide layer, further comprising:
and depositing a third phosphorus source layer on the front surface of the silicon substrate at the second preset temperature so as to diffuse the third phosphorus source layer into the first oxide layer.
3. The method of claim 1, wherein prior to forming the first phosphorus source layer by front side deposition of the silicon wafer, further comprising:
oxidizing the surface of the silicon wafer at a second preset temperature to obtain a third oxide layer;
the depositing a first phosphorus source layer on the surface of the silicon wafer comprises the following steps:
and depositing and forming the first phosphorus source layer on the third oxide layer of the silicon wafer at the second preset temperature.
4. The method of claim 1, wherein the silicon wafer comprises at least one of a monocrystalline silicon wafer, a polycrystalline silicon wafer, a microcrystalline silicon wafer, a nanocrystalline silicon wafer, or an amorphous silicon wafer.
5. The method of claim 1, wherein the first preset temperature is at least one of 800 ℃ to 900 ℃.
6. A method according to any one of claims 1 to 3, wherein the second preset temperature is at least one of 700 ℃ to 850 ℃.
7. The method of claim 1, wherein the first predetermined depth is any value between 200 nanometers and 400 nanometers;
the second preset depth is less than 50 nanometers.
8. A solar cell, wherein the solar cell comprises a silicon substrate prepared by the method for preparing a silicon substrate according to any one of claims 1 to 7.
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