WO2023179023A1

WO2023179023A1 - Solar cell manufacturing method, solar cell and power generation device

Info

Publication number: WO2023179023A1
Application number: PCT/CN2022/128526
Authority: WO
Inventors: 朱波; 谢文鹏
Original assignee: 通威太阳能（安徽）有限公司
Priority date: 2022-03-24
Filing date: 2022-10-31
Publication date: 2023-09-28
Also published as: CN114823304A

Abstract

The present disclosure provides a solar cell manufacturing method, a solar cell and a power generation device. The solar cell manufacturing method comprises the following steps: placing a P-type doped silicon wafer in a reaction chamber, and forming a N-type doped layer on the surface of the P-type doped silicon wafer; introducing a phosphorus source into the reaction chamber, controlling the flow rate of the phosphorus source to be 1200-1500 sccm, and heating the silicon wafer to form a phosphorus-silicon glass layer on the surface of the N-type doped layer; using a laser-doped silicon wafer, such that phosphorus atoms in the phosphorus-silicon glass layer are diffused into the N-type doped layer; and removing a silicon-silicon glass layer, forming a gate line electrode on the position on the surface layer of the silicon wafer subjected to laser doping, and performing sintering treatment.

Description

Preparation method of solar cell, solar cell and power generation device

This application claims priority to the Chinese patent application filed with the China Patent Office on March 24, 2022, with application number 2022102943245 and the public name of "Solar Cell Preparation Method, Solar Cell and Power Generation Device", the entire content of which is incorporated by reference. in this application.

Technical field

The present disclosure relates to the technical field of solar cells, and in particular to a method of preparing a solar cell, a solar cell and a power generation device.

Background technique

A solar cell is a semiconductor component that uses the photovoltaic effect to convert light energy into electrical energy. Solar energy is an inexhaustible clean energy source and has received widespread attention.

PERC (Passivated Emitter and Rear Cell), which is passivated emitter and rear cell technology, is considered to be a very cost-effective technology for preparing solar cells. PERC technology refers to adding a dielectric passivation layer on the back of the solar cell. The passivation layer can reduce the recombination of surface carriers and thus improve the conversion efficiency.

Wire mesh sintering is an indispensable part of the preparation process of PERC cells. Specifically, the surface of the solar cell is usually provided with a grid electrode for deducting carriers. Sintering melts the grid wire at high temperature to melt the metal and silicon in the grid wire, and etch away the silicon nitride film on the surface of the silicon wafer. , enters the silicon matrix, and forms a uniform and good ohmic contact on the back electrode, back electric field, positive electrode and silicon substrate. The printed cells can not only form a dense structure and have good electrode current collection and conductivity after being subjected to a good sintering environment, but also the hydrogen in the silicon nitride dielectric film on the surface of the cells is released during the high-temperature treatment and diffuses into the silicon wafer. It can not only passivate dangling bonds at the silicon material interface, but also passivate deep inside the silicon material, thereby ensuring cell efficiency and yield.

In the actual production process, when the sintering temperature is low, there is under-firing. When under-firing, the metal slurry cannot fully penetrate the silicon nitride dielectric film into the silicon wafer, and cannot form a good ohmic contact, resulting in solar cell yield. and reduction in efficiency. When the sintering temperature is high, over-burning will occur. During over-burning, the metal component of the gate line is more likely to enter the junction area, which will cause a partial short circuit; and aluminum metal will also melt into silicon and form an aluminum-silicon alloy layer, causing battery failure. If the wafer fails, the hydrogen in the silicon nitride thin layer will also escape from the silicon, weakening the passivation effect of hydrogen on the silicon wafer, and also leading to a reduction in solar cell yield and efficiency. The above two situations are contradictory to each other, and it is difficult to solve the above two problems at the same time in the actual preparation process, which limits the improvement of the efficiency of solar cell products.

Contents of the invention

According to some embodiments of the present disclosure, a method for preparing a solar cell is provided, which includes the following steps:

Place the P-type doped silicon wafer in the reaction chamber, and form an N-type doped layer on the surface of the silicon wafer;

Pass a phosphorus source into the reaction chamber, control the flow rate of the phosphorus source to 1200 sccm to 1500 sccm, and react the phosphorus source with the silicon wafer to form a phosphorus silicate glass layer on the surface of the N-type doped layer ;

Using a laser to dope the portion of the silicon wafer used for the screen-printed gate line electrode, so that the phosphorus atoms in the phosphorus silicate glass layer in the laser-doped portion diffuse into the N-type doped layer;

The phosphorus silicate glass layer is removed, a gate electrode is formed on the surface of the silicon wafer at a location for silk screen printing of the gate electrode, and sintering is performed.

In some embodiments of the present disclosure, in the step of forming the phosphosilicate glass layer, the temperature in the reaction chamber is controlled to be 780°C to 820°C.

In some embodiments of the present disclosure, in the step of forming the phosphosilicate glass layer, the reaction time is controlled to be 12 min to 16 min.

In some embodiments of the present disclosure, in the step of forming the phosphosilicate glass layer, an oxygen source with a flow rate of 300 sccm to 500 sccm is introduced into the reaction chamber.

In some embodiments of the present disclosure, the phosphorus source is selected from phosphorus oxychloride.

In some embodiments of the present disclosure, during sintering, the sintering temperature is controlled to be 760°C to 800°C.

In some embodiments of the present disclosure, in the step of laser doping the silicon wafer using laser doping, the power of the laser is controlled to be 15W to 35W.

In some embodiments of the present disclosure, in the process of forming the N-type doped layer, a phosphorus source is first introduced into the reaction chamber for pre-deposition, and then high temperature is performed at a temperature of 840°C to 880°C. Push-knot processing, and then perform low-temperature push-knot processing at a temperature of 780°C to 820°C.

In some embodiments of the present disclosure, during the formation of the N-type doped layer, the flow rate of the phosphorus source is 600 sccm to 800 sccm.

According to further embodiments of the present disclosure, a solar cell is also provided, which is prepared by a preparation method including the following steps:

According to further embodiments of the present disclosure, a power generation device is also provided, which includes the solar cell as claimed in any of the above embodiments.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of the drawings

Figure 1 is a schematic diagram of the surface concentration of phosphorus element in the silicon wafer of Example 1 and Comparative Example 1 as a function of junction depth.

Detailed ways

In order to facilitate an understanding of the invention, the invention will be described more fully below. Preferred embodiments of the invention are given herein. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough understanding of the present disclosure will be provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. As used herein, "more" includes two and more than two items. "A certain number or more" used in this article should be understood as a certain number and a range greater than a certain number.

According to an embodiment of the present invention, a method for preparing a solar cell includes the following steps:

Pass a phosphorus source into the reaction chamber, control the flow rate of the phosphorus source to 1200 sccm to 1500 sccm, and heat the silicon wafer to form a phosphosilicate glass layer on the surface of the N-type doped layer;

The solar cell preparation method in the above embodiment can be implemented in a specific manner including the following steps S1 to S4.

In step S1, a P-type doped silicon wafer is placed in a reaction chamber, and an N-type doped layer is formed on the surface of the P-type doped silicon wafer.

It can be understood that pure silicon is an intrinsic semiconductor, and the number of electrons and holes in it should be the same. P-type doped silicon wafers are silicon wafers doped with acceptor impurities. Acceptor impurities can provide hole carriers to the silicon wafer, making the holes in the silicon wafer a multi-carrier. The P-type doped silicon wafer may be selected from boron-doped silicon wafers.

In one specific example, the P-type doped silicon wafer is a textured silicon wafer. Texturing refers to the formation of a pyramid-shaped microstructure on the surface of the silicon wafer through alkali polishing and other processes to enhance the silicon wafer's ability to absorb light.

In one specific example, after placing the P-type doped silicon wafer in the reaction chamber, the reaction chamber can be preheated first, and the temperature of the chamber can be controlled to be heated to 660°C to 860°C. After the preheating is completed, the temperature of the reaction chamber is maintained, and the air pressure in the reaction chamber is evacuated to 50 Pa to 150 Pa.

In one specific example, before forming the N-type doped layer, a step of pre-oxidizing the silicon wafer by introducing an oxygen source is also included. Optionally, the flow rate into the oxygen source is 600 sccm. The main purpose of pre-oxidation is to grow dense silicon dioxide layers of corresponding thickness at different locations on the silicon wafer to alleviate the problem of high sheet resistance in the center and low surroundings of the silicon wafer.

In one specific example, pre-deposition can be performed on the surface of the silicon wafer after oxidation to form an N-type doped layer. Specifically, in the process of forming the N-type doped layer, a phosphorus source is first introduced into the reaction chamber for pre-deposition, and then a high-temperature pushing process is performed at a temperature of 840°C to 880°C, and then a phosphorus source is introduced into the reaction chamber at a temperature of 780°C to 820°C. Low-temperature push-knot processing is performed at a temperature of ℃. Among them, during the pre-deposition process, the temperature in the reaction chamber can be controlled to be maintained at 760°C to 800°C, the pressure is maintained at 90Pa to 110Pa, and a phosphorus source is introduced for pre-deposition. The flow rate of the phosphorus source is 600 to 800 sccm. Furthermore, after 4 minutes of deposition, the main function of pre-deposition is to deposit a layer of phosphorus elemental substance on the surface of the silicon wafer. The main purpose of the high-temperature push-down treatment is to redistribute the phosphorus elemental substance on the surface of the silicon wafer so that the phosphorus elemental substance deposited on the surface Diffusion into the silicon wafer and low-temperature push-bonding can make the phosphorus element more evenly distributed within the silicon wafer. It can be understood that the N-type doped layer is formed on the surface layer of the original silicon wafer, and forms a PN junction on the underlying P-type silicon wafer.

Step S2, introduce a phosphorus source into the reaction chamber, control the flow rate of the phosphorus source to 1200 sccm to 1500 sccm, and heat the silicon wafer to form a phosphosilicate glass layer (PSG) on the surface of the N-type doped layer.

It can be understood that the flow rate of the phosphorus source in this step is significantly higher than the flow rate of the phosphorus source in the previous step. This is mainly due to the need to diffuse phosphorus atoms into the silicon substrate when preparing the PN junction, and this step is for the purpose of forming the PN junction on the silicon wafer. A phosphosilicate glass layer with the required higher phosphorus content is formed on the surface in preparation for subsequent laser doping and further silk screen sintering. When forming the required phosphosilicate glass layer, there are requirements for the flow rate of the phosphorus source. If the flow rate of the phosphorus source is lower than 1200 sccm, the phosphorus concentration in the phosphosilicate glass layer formed cannot meet the requirements, and subsequent laser doping And further silk screen sintering is also difficult to obtain the required technical effects.

It can be understood that when forming the phosphosilicate glass layer, the silicon wafer needs to be heated to promote the reaction between the phosphorus source and the silicon wafer. In one specific example, in order to cooperate with the flow rate of the above-mentioned phosphorus source to save the preparation time as much as possible while maintaining the concentration of phosphorus in the phosphosilicate glass layer, in the step of forming the phosphosilicate glass layer, the reaction can also be controlled The temperature in the chamber is 800℃~820℃. Furthermore, the reaction time can also be controlled to 12 min to 16 min.

In one specific example, in the step of forming the phosphosilicate glass layer, an oxygen source with a flow rate of 300 sccm to 500 sccm is introduced into the reaction chamber.

In one specific example, the phosphorus source may be selected from phosphorus oxychloride.

In one specific example, after the phosphosilicate glass layer is formed, the silicon wafer may be further oxidized to remove impurities. Specifically, after the phosphosilicate glass layer is formed, 1000 sccm to 1200 sccm of oxygen is introduced to form silicon dioxide, which plays a gettering role, and the phosphosilicate glass layer is used to adsorb and fix sodium, potassium and other ions. These harmful ions are removed while removing the phosphosilicate glass layer.

Further, after the oxidation treatment, nitrogen can be introduced into the reaction chamber to a normal pressure state, and then the silicon wafer can be taken out of the reaction chamber for later use.

Step S3: Use laser to dope the silicon wafer to diffuse phosphorus atoms in the phosphorus silicate glass layer into the N-type doped layer.

Step S3 is the laser doping operation. Laser doping uses the thermal effect of the laser to melt the surface of the silicon wafer, allowing the phosphorus atoms in the phosphorus-silicate glass covering the top of the emitter to enter the surface of the silicon wafer. The diffusion coefficient of phosphorus atoms in liquid silicon is greater than that in solid silicon. Several orders of magnitude higher. After curing, doped phosphorus atoms replace the positions of silicon atoms to form a heavily doped layer.

In one specific example, the location of laser doping mainly corresponds to the location of subsequent gate line electrodes. Therefore, laser doping can eliminate the need for laser doping of the entire surface of the silicon wafer. In one specific example, a laser is used to dope a predetermined portion of the silicon wafer surface for silk-printed gate line electrodes.

Laser doping on the surface of silicon wafers also has the following problems. Usually, lower laser power cannot achieve the effect of heavy doping, resulting in poor ohmic contact between the emitter and the subsequently formed metal gate electrode. Therefore, in traditional technology, a higher power laser pair is usually selected. The surface of the silicon wafer is laser doped to obtain a heavily doped effect. Higher laser power will destroy the texture structure of the silicon wafer and further reduce the efficiency of the solar cell. In this embodiment, due to the specific process for preparing the phosphosilicate glass layer, the phosphorus content in the phosphosilicate glass layer is effectively increased, which is more conducive to the formation of heavy doping, and the dense and sufficient phosphosilicate glass layer can protect When laser pulse bombards the surface of the silicon wafer, it reduces texture damage, reduces dangling bonds and dislocation defects, reduces cell surface recombination, increases minority carrier lifetime, and thereby improves yield.

Furthermore, the above-mentioned process of preparing the phosphosilicate glass layer also allows the power of laser doping to be appropriately reduced, reducing damage to the textured structure, which is equivalent to improving the efficiency of solar cells based on traditional technology. In one specific example, in the step of laser doping the silicon wafer, the power of the laser is controlled to 15W~35W to reduce the damage caused by the laser doping to the textured structure on the surface of the silicon wafer. .

Further, in one specific example, during the process of laser doping and engraving of the auxiliary grid and the anti-breakage grid, the frequency of the laser is 200kHz to 240kHz. Further, the power factor (Powerfactor) value of the laser can be set to 230kHz to 270kHz.

Step S4: Remove the phosphosilicate glass layer, form a gate electrode on the laser-doped part of the silicon wafer surface, and perform sintering.

Among them, the method of removing the phosphosilicate glass layer can be alkali treatment, and the alkali treatment can be selected from the alkali polishing method commonly used in traditional technology.

The gate electrode may be formed by screen printing a paste containing metal to form the gate electrode. After screen printing, a sintering process is usually required to allow the metal paste to penetrate the silicon nitride dielectric film and enter the silicon wafer to form a good ohmic contact.

The process in step S2 can increase the phosphorus content in the phosphosilicate glass layer, so that the sintering temperature of the silk-printed gate line electrode can be effectively reduced in this step. In one specific example, during the sintering process, the sintering temperature can be controlled to be 760°C to 800°C. Furthermore, the sintering temperature can be controlled to 760°C to 790°C. Furthermore, the sintering temperature can be controlled to 760°C to 780°C.

From the above embodiments, it can be understood that the solar cell preparation method provided by the present invention has the following beneficial effects. The solar cell preparation method adopts a specific diffusion process, which increases the phosphorus content of the phosphorus silicate glass layer on the surface of the silicon wafer, and increases the phosphorus content in the silicon wafer under the gate line, which is beneficial to the interaction between the metal gate line electrode and the silicon Good ohmic contact is formed between the pieces. This enables the metal slurry to form good ohmic contact with the silicon wafer even if a lower-temperature sintering process is used, thereby overcoming the contradiction that will cause problems in both high-temperature sintering and low-temperature sintering.

Furthermore, the above-mentioned manufacturing steps of phosphosilicate glass with increased phosphorus content combined with sintering at a lower temperature can not only overcome the ohmic contact problem existing in low-temperature sintering, but also help to improve the passivation effect of hydrogen atoms in the silicon wafer, reducing the High-temperature sintering amplifies defects in silicon wafers, ultimately achieving the purpose of increasing the efficiency of solar cells and improving product quality.

Furthermore, the above-mentioned manufacturing steps of increasing the phosphorus content of phosphosilicate glass can also be combined with the step of heavy doping with lower laser power. By taking advantage of the characteristics of the phosphosilicate glass layer with high phosphorus content, lower laser power can be used. , combined with the protective effect of the dense phosphosilicate glass layer, it reduces the texture damage on the silicon wafer surface caused by the laser doping process and avoids the performance degradation caused by this process.

In order to make it easier to understand and implement the present invention, the following more specific and detailed examples and comparative examples that are easier to implement are also provided for reference. Various embodiments of the present invention and their advantages will also be apparent from the descriptions and performance results of the following specific examples and comparative examples.

Unless otherwise specified, the raw materials used in the following examples can all be purchased from the market.

In addition, during the actual preparation process, the actual thickness of each layer may be slightly different from the tested thickness, but this does not affect the progress of the comparative examples and examples.

Example 1: Preparation of silicon wafers with a phosphosilicate glass layer with high phosphorus content

(1) Send the textured silicon wafer into the reaction furnace tube, and the furnace tube is heated to 760℃±100℃;

(2) The temperature of each temperature zone is maintained at 760±100℃, and the vacuum is evacuated to 50Pa-150Pa;

(3) Keep the temperature of each temperature zone at 760±100℃, vacuum to 50Pa-150pa, stop vacuuming, and perform leak detection on the furnace tube;

(4) Pre-oxidation: The temperature in each temperature zone is maintained at 760±100°C, the pressure in the reactor tube is maintained at 100±10Pa, oxygen is introduced for oxidation, the time is controlled at 3 minutes, and the oxygen flow is 600 sccm;

(5) Pre-deposition: After oxidation, the temperature of each temperature zone is maintained at 770±20℃, the pressure is maintained at 100±10Pa, oxygen and phosphorus oxychloride are passed, the oxygen flow is 600sccm, and the flow rate of phosphorus oxychloride is 600sccm~800sccm , the step time is 4 minutes; then each temperature zone is increased by 10°C, keeping the gas flow constant, and continuing deposition for 4 minutes;

(6) The temperature of each temperature zone is maintained at 860±20℃, perform high-temperature push-off for 10 minutes, and then maintain the temperature for 2.5 minutes;

(7) The temperature of each temperature zone is maintained at 800±20°C, the temperature is cooled down for 15 minutes, and then the temperature is maintained for 6 minutes;

(8) Keep the temperature at 800±20°C, and introduce 1,300 sccm of phosphorus oxychloride and 400 sccm of oxygen for 10 minutes to form a PSG layer with high phosphorus content;

(9) The temperature of each temperature zone is maintained at 800±20°C, and 1000 sccm of oxygen is introduced for oxidation;

(10) After oxidation, fill with nitrogen gas at 2500 sccm to normal pressure; and take out the silicon wafer.

Comparative Example 1: Preparation of silicon wafer with low phosphorus content phosphosilicate glass layer

(8) Keep the temperature at 800±20°C, and pass in 800 sccm of phosphorus oxychloride and 400 sccm of oxygen for 10 minutes to form a PSG layer;

The silicon wafers prepared in Example 1 and Comparative Example 1 were characterized, and the relationship between the surface concentration of the phosphorus element and the junction depth was tested. The results are shown in Figure 1.

Figure 1 shows the relationship between the surface concentration of the phosphorus element in the silicon wafer and the junction depth. The inflection point 1 marked in Figure 1 is the highest point, generally located at a depth of 10 nm, and usually represents the surface concentration of doping. The test size is between 10 ²⁰ /cm ³ -10 ²¹ /cm ^3. Surface doping in Example 1 The concentration is greater than the surface doping concentration of Comparative Example 1.

More importantly, inflection point 2 in Figure 1 is a mutation point. The concentration gradient at inflection point 2 directly affects the subsequent sintering effect of the gate line electrode. Inflection point 2 in Comparative Example 1 is a mutation point, and the slope of the curve changes significantly. The concentration gradient Larger, the sintering process is more difficult. The slope of the curve of Example 1 changes more gently, the concentration gradient is smaller, the sintering process is easier to carry out, and therefore the required temperature is also lower.

Inflection point 3 represents the position of the PN junction. The abscissa of the inflection point 3, that is, the junction depth, is generally between 0.25 μm and 0.40 μm. A deeper diffusion junction can prevent the gate line electrode metal from penetrating into the junction area and reduce the probability of introducing electrode metal energy levels into the forbidden band. Not only can the electrode be in good contact with the silicon wafer, but it can also appropriately relax the temperature and time control during junction production. strict requirements. The ordinate where the inflection point 3 is located represents the effective doping. When the effective doping is more, the open circuit voltage and short circuit current can be increased.

Example 2

Take the sample of Example 1 and process it as follows:

(1) The preset grid line position on the surface of the silicon wafer is doped with laser, so that the phosphorus in the PSG diffuses into the surface of the silicon wafer. The laser power is set at 25W, and the frequency is set in the laser engraving parameters of the graphic sub-grid and the anti-breakage grid. Set at 220kHz, the energy factor value is set at 250kHz;

(2) Screen-print the grid electrode and sinter it. The sintering temperature is set to 780°C.

Comparative example 2

Take the sample of Comparative Example 1 and process it as follows:

(2) Screen-print the grid electrode and sinter it, and set the sintering temperature to 840°C.

Comparative example 3

Take the sample of Comparative Example 1 and process it as follows:

Comparative example 4

The sample of Example 1 was taken and processed as follows:

The solar cells prepared in the above-mentioned Example 2 and Comparative Examples 2 to 4 were characterized and their efficiency data were obtained. The results can be seen in Table 2.

Table 2: Comparison of battery efficiency data of Example 2 and Comparative Examples 2 to 4

It can be seen from the data in Table 2 that compared with Comparative Example 2 based on the method used in traditional production lines, the efficiency of Example 2 can be improved by 0.036%, mainly reflected in the short-circuit current gain of 0.009A, the fill factor gain of 0.07%, and the pass rate. An improvement of 0.59%. This is mainly because Embodiment 2 adopts a specific method of preparing the phosphosilicate glass layer, which allows the subsequent screen printing and sintering steps to be performed at a lower temperature, which is helpful for shaping the silver paste of the gate line electrode and achieving good ohmic contact. , which is conducive to improving the short-circuit current and filling factor, which is consistent with theoretical analysis.

Further, yield testing was performed on Example 2 and Comparative Example 2, and the specific test results are shown in Table 3.

Table 3: Comparison of battery yield data of Example 2 and Comparative Example 2

It can be seen from the data in Table 3 that the yield of the battery cells of Example 2 is 0.56% higher than that of Comparative Example 2, which is mainly reflected in foggy blackening, dirt and graphite boat marks. This may be mainly due to Example 2 The process helps reduce the escape of hydrogen ions during the sintering process and improves the protective and passivation effect of the silicon nitride film.

Further, the battery sheets of Example 2 and Comparative Example 2 were subjected to an ORT test (Ongoing Reliability test, that is, product reliability test or product continuity test), and the results are as shown in Table 4.

Table 4: Comparison of battery ORT test data of Example 2 and Comparative Example 2

As can be seen from Table 4, it can be found that the results of the front silver tensile test, back silver tensile force data, and curvature test data of Example 2 and Comparative Example 2 all show OK. At the same time, the curvature of Example 2 is better than that of Comparative Example 2. Since the thermal expansion coefficient of the silicon wafer is different from that of the aluminum layer in contact with the back, the shrinkage of the aluminum layer after sintering will cause the silicon wafer to deform, which is called silicon wafer warpage. , the thinner the silicon wafer and the thicker the aluminum layer, the greater the distortion of the silicon wafer, causing the curvature of the cell to exceed the predetermined requirements. The lower electric shock sintering temperature will not cause damage to the silicon wafer, and it will slow down the aluminum paste on the back. The degree of shrinkage reduces the warpage of solar cells, improves the yield rate, and extends the service life of the cells, which is conducive to the development of thinner silicon wafer technology in the future.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above embodiments only express several embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims

A method for preparing a solar cell, including the following steps:

Place the P-type doped silicon wafer in the reaction chamber, and form an N-type doped layer on the surface of the silicon wafer;

Pass a phosphorus source into the reaction chamber, control the flow rate of the phosphorus source to 1200 sccm to 1500 sccm, and react the phosphorus source with the silicon wafer to form a phosphorus silicate glass layer on the surface of the N-type doped layer ;

Using a laser to dope the portion of the silicon wafer used for the screen-printed gate line electrode, so that the phosphorus atoms in the phosphorus silicate glass layer in the laser-doped portion diffuse into the N-type doped layer;

The phosphorus silicate glass layer is removed, a gate electrode is formed on the surface of the silicon wafer at a location for silk screen printing of the gate electrode, and sintering is performed.
According to the method of manufacturing a solar cell according to claim 1, in the step of forming the phosphosilicate glass layer, the temperature in the reaction chamber is controlled to be 780°C to 820°C.
According to the method for preparing a solar cell according to claim 2, in the step of forming the phosphosilicate glass layer, the reaction time is controlled to be 12 min to 16 min.
According to the method of manufacturing a solar cell according to claim 1, in the step of forming the phosphosilicate glass layer, an oxygen source with a flow rate of 300 sccm to 500 sccm is introduced into the reaction chamber.
According to the method for preparing a solar cell according to any one of claims 1 to 4, the phosphorus source is selected from phosphorus oxychloride.
According to the method for preparing a solar cell according to any one of claims 1 to 4, during sintering, the sintering temperature is controlled to be 760°C to 800°C.
According to the method for manufacturing a solar cell according to any one of claims 1 to 4, in the step of laser doping the silicon wafer using laser doping, the power of the laser is controlled to be 15W-35W.
The method for manufacturing a solar cell according to any one of claims 1 to 4, further comprising a step of pre-oxidizing the silicon wafer by introducing an oxygen source before forming the N-type doped layer.
According to the method for preparing a solar cell according to claim 8, in the step of pre-oxidizing the silicon wafer, the flow rate of the oxygen source is 600 sccm.
According to the method for preparing a solar cell according to any one of claims 1 to 4, in the process of forming the N-type doped layer, a phosphorus source is first introduced into the reaction chamber for pre-deposition, and then the phosphorus source is introduced into the reaction chamber at 840°C. High-temperature push-knot processing is performed at a temperature of ~880°C, and low-temperature push-knot processing is performed at a temperature of 780°C ~ 820°C.
According to the method for manufacturing a solar cell according to claim 10, in the process of forming the N-type doped layer, the flow rate of the phosphorus source introduced is 600 sccm to 800 sccm.
The method for manufacturing a solar cell according to any one of claims 1 to 4, further comprising the step of further oxidizing the silicon wafer after forming the phosphosilicate glass layer.
According to the method of manufacturing a solar cell according to claim 12, in the step of further oxidizing the silicon wafer, 1000 sccm to 1200 sccm of oxygen is introduced to form silicon dioxide.
According to the method for manufacturing a solar cell according to any one of claims 1 to 4, the phosphosilicate glass layer is removed by alkali treatment.
A solar cell is prepared by a preparation method including the following steps:

Place the P-type doped silicon wafer in the reaction chamber, and form an N-type doped layer on the surface of the silicon wafer;

Pass a phosphorus source into the reaction chamber, control the flow rate of the phosphorus source to 1200 sccm to 1500 sccm, and react the phosphorus source with the silicon wafer to form a phosphorus silicate glass layer on the surface of the N-type doped layer ;

Using a laser to dope the portion of the silicon wafer used for the screen-printed gate line electrode, so that the phosphorus atoms in the phosphorus silicate glass layer in the laser-doped portion diffuse into the N-type doped layer;

The phosphorus silicate glass layer is removed, a gate electrode is formed on the surface of the silicon wafer at a location for silk screen printing of the gate electrode, and sintering is performed.
The solar cell according to claim 15, in the step of forming the phosphosilicate glass layer, the temperature in the reaction chamber is controlled to be 780°C to 820°C.
The solar cell according to claim 16, in the step of forming the phosphosilicate glass layer, the reaction time is controlled to be 12 min to 16 min.
The solar cell according to claim 15, in the step of forming the phosphosilicate glass layer, an oxygen source with a flow rate of 300 sccm to 500 sccm is introduced into the reaction chamber.
The solar cell according to any one of claims 15 to 18, wherein the phosphorus source is selected from phosphorus oxychloride.
According to the solar cell according to any one of claims 15 to 18, during sintering, the sintering temperature is controlled to be 760°C to 800°C.
The solar cell according to any one of claims 15 to 18, in the step of laser doping the silicon wafer by laser doping, the power of the laser is controlled to be 15W-35W.
The solar cell according to any one of claims 15 to 18, further comprising a step of pre-oxidizing the silicon wafer by introducing an oxygen source before forming the N-type doped layer.
The solar cell according to claim 22, in the step of pre-oxidizing the silicon wafer, the flow rate of the oxygen source is 600 sccm.
According to the solar cell according to any one of claims 15 to 18, in the process of forming the N-type doped layer, a phosphorus source is first introduced into the reaction chamber for pre-deposition, and then the temperature is maintained at 840°C to 880°C. High-temperature push-knot processing is performed at a temperature of 780°C to 820°C, and low-temperature push-knot processing is performed at a temperature of 780°C to 820°C.
According to the solar cell of claim 24, in the process of forming the N-type doped layer, the flow rate of the phosphorus source introduced is 600 sccm to 800 sccm.
The solar cell according to any one of claims 15 to 18, further comprising the step of further oxidizing the silicon wafer after forming the phosphosilicate glass layer.
The solar cell according to claim 26, in the step of further oxidizing the silicon wafer, 1000 sccm to 1200 sccm of oxygen is introduced to form silicon dioxide.
According to the method for manufacturing a solar cell according to any one of claims 15 to 18, the phosphosilicate glass layer is removed by alkali treatment.
A power generation device including the solar cell according to any one of claims 15 to 28.