CN114188348A

CN114188348A - 3D memory device and bit line structure thereof

Info

Publication number: CN114188348A
Application number: CN202111382897.5A
Authority: CN
Inventors: 石艳伟; 张权; 董金文; 华子群; 刘峻
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-06-03
Filing date: 2020-06-03
Publication date: 2022-03-15
Also published as: CN111785728B; CN111785728A

Abstract

An embodiment of the present application provides a 3D memory device and a bit line structure thereof, the bit line structure of the 3D memory device including: a top interlayer insulating layer including at least one conductive via; a plurality of bit lines on the top interlayer insulating layer; the bit line is electrically connected with the channel column of the 3D memory device through the conductive channel; the bit lines are provided with openings among the bit lines, and the openings are filled with low-K dielectrics.

Description

3D memory device and bit line structure thereof

The present application is a divisional application of a patent entitled method for fabricating a bit line of a 3D memory device, having an application date of 2020, 03/06 and an application number of 202010492816.6.

Technical Field

The present application relates to memory technology, and more particularly, to a 3D memory device and a bit line structure thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

In a 3D memory device of a NAND structure, a CMOS circuit is formed using a semiconductor substrate, and a gate stack structure and a plurality of channel pillars penetrating the gate stack structure are formed on the semiconductor substrate, and the gate stack structure and the plurality of channel pillars together form a memory cell array. The bottom end of the channel pillar is connected to the common source region and the top end is connected to a bit line through a conductive via, and a gate conductor in the gate stack is connected to a word line through a conductive via. As the integration of the 3D memory device increases, the number of word lines and bit lines increases, and the pitch of bit lines adjacent to each other decreases. Parasitic capacitance of the bit line is related to RC delay of the 3D memory device, which adversely affects read and write speed.

In order to improve the read and write speed of the 3D memory device, a conductive material may be filled in an interlayer insulating layer composed of a low-K material to form a bit line. In the case of using the low-K material, the parasitic capacitance of the bit line is reduced as the dielectric constant K of the interlayer insulating layer is reduced, and thus the RC delay of the 3D memory device may be reduced. However, the interlayer insulating layer of the low-K material introduces a new problem in that the breakdown voltage of the 3D memory device decreases as the dielectric constant K of the interlayer insulating layer decreases, resulting in deterioration of reliability of the 3D memory device. In the case where the thickness of the interlayer insulating layer is less than 7 nm, it has been difficult to achieve the requirement of the breakdown voltage of 8.5V or more.

Therefore, it is desirable to further improve the bit lines of the 3D memory device to further improve the read and write speed and reliability of the 3D memory device.

Disclosure of Invention

In view of the above, embodiments of the present application provide a 3D memory device and a bit line structure thereof.

In a first aspect, an embodiment of the present application provides a bit line structure of a 3D memory device, including:

a top interlayer insulating layer including at least one conductive via;

a plurality of bit lines on the top interlayer insulating layer; the bit line is electrically connected with the channel column of the 3D memory device through the conductive channel;

an opening is formed among the bit lines, and a low-K dielectric is filled in the opening; wherein the dielectric constant of the low-K dielectric is less than the dielectric constant of TEOS.

In some embodiments, the bit line architecture further comprises:

and a cover insulating layer on the plurality of bit lines and the top interlayer insulating layer.

In some embodiments, the cover insulating layer fills the opening; wherein the blanket insulating layer is comprised of a low-K material; the cover insulating layer filled in the opening serves as the low-K dielectric.

In some embodiments, the low-K material is a low-K oxide.

In some embodiments, the cover insulating layer closes the opening such that air in the opening acts as the low-K dielectric.

In some embodiments, there are additional levels of routing layers between the blanket insulating layer and the plurality of bit lines.

In some embodiments, the bit line architecture further comprises:

a patterned hard mask covering the bit lines for patterning to form the bit lines; the patterned hard mask is formed through a side wall process.

In some embodiments, the bit line cross-section is rectangular, and the bit line width is constant, and the bit line pitch is constant along the bit line depth direction.

In some embodiments, the bit line pitch is equal to a minimum pitch between top surfaces of the bit lines.

In some embodiments, the patterned hard mask corresponds to a shape of the bit lines, and the openings of the patterned hard mask correspond to isolations between the bit lines.

In some embodiments, the patterned hard mask is comprised of silicon nitride.

In some embodiments, the bit lines are comprised of tungsten and/or polysilicon.

In another aspect, an embodiment of the present application provides a 3D memory device, including:

the bit line structure of the 3D memory device;

a memory cell string including a channel pillar; the channel pillar is electrically connected with a bit line in the bit line structure via a conductive channel.

In some embodiments, the 3D memory device further includes:

a semiconductor substrate;

and the grid laminated structure is positioned on the semiconductor substrate and comprises a plurality of grid conductor layers and a plurality of middle interlayer insulating layers which are alternately stacked, and the top interlayer insulating layer covers the grid conductor layer at the top.

In some embodiments, the channel pillar penetrates through a plurality of gate conductor layers and a plurality of the interlayer insulating layers of the gate stack structure.

In some embodiments, the channel pillar comprises:

the tunneling device comprises a channel layer, a tunneling dielectric layer, a charge storage layer and a gate dielectric layer.

In some embodiments, the tunneling dielectric layer, the charge storage layer, and the gate dielectric layer are sandwiched between the gate conductor layer and the channel layer.

In the method for manufacturing the bit line of the 3D memory device according to the embodiment of the present application, a first hard mask is formed using a sidewall process, the first hard mask is exposed in an opening of a second hard mask, the first hard mask and the second hard mask together form a complete mask of the bit line, and the bit line is transferred into a conductive layer via a first mask stack to form the bit line. The width of the bit line formed by the manufacturing method corresponds to the film thickness of the conformal layer in the side wall process, and the space between the bit lines corresponds to the opening width in the side wall process and the film thickness of the conformal layer, so that the dense bit lines with small width and small space can be formed by controlling the opening width in the side wall process and the film thickness of the conformal layer. Since the bit line pattern is transferred using the first mask stack, the width of the bit line is substantially rectangular in shape, and the width of the bit line increases substantially constant along the depth extending downward. The pitch between bit lines adjacent to each other is substantially equal to the minimum pitch between the top surfaces of the bit lines.

According to the bit line manufacturing method, the read-write speed and the reliability of the 3D memory device can be considered at the same time. In this embodiment, the cap insulating layer is formed using, for example, a low-K oxide (dielectric constant of about 2.6) instead of TEOS oxide (dielectric constant of about 4.1). The cap insulating layer fills the openings between adjacent bit lines forming a dielectric between the bit lines. With the reduction of the bit line width and the bit line pitch, the parasitic capacitance of the bit line can be also significantly reduced by about 37% in the case of using the low-K oxide, so that the RC delay can be reduced, and the read-write speed of the 3D memory device can be improved. The fabrication method employs a hard mask pattern transfer technique that eliminates bottlenecks, and the bitline width and bitline pitch increase substantially constant along the depth of the downward extension. Even if the bit line pitch is reduced, the breakdown voltage of the 3D memory device can meet design requirements without premature breakdown, and thus the reliability of the 3D memory device can be improved.

In the bit line manufacturing method of the 3D memory device according to the preferred embodiment of the present application, using air as a dielectric between adjacent bit lines may further reduce parasitic capacitance of the bit lines, thereby further improving the read and write speed of the 3D memory device.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2a to 2c show schematic cross-sectional views of different steps of a bit line manufacturing method of a 3D memory device according to the prior art.

Fig. 3 illustrates a flowchart of a bit line fabrication method of a 3D memory device according to a first embodiment of the present application.

Fig. 4a to 4k show schematic cross-sectional views of different steps of a bit line manufacturing method of a 3D memory device according to a first embodiment of the present application.

Fig. 5 shows a schematic cross-sectional view of a last step of a bit line fabrication method of a 3D memory device according to a second embodiment of the present application.

Detailed Description

The present application will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

Numerous specific details of the present application, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

The present application may be presented in a variety of forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present application is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a Bit Line (BL), and a second terminal is connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The Gate of the first select transistor Q1 is connected to a string select line (SGD), and the Gate of the second select transistor Q2 is connected to a Source select line (SGS). The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include gate conductor layers 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductor layers 121, respectively. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling. Taking memory transistor M2 as an example, while the source line SL is grounded, the source select line SGS is biased to approximately zero volts such that select transistor Q2 corresponding to source select line SGS is turned off, and the string select line SGD is biased to a high voltage VDD such that select transistor Q1 corresponding to string select line SGD is turned on. Further, the bit line BL2 is grounded, the word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2a to 2c show schematic cross-sectional views of different steps of a bit line manufacturing method of a 3D memory device according to the prior art. For clarity, only a portion of the structure of the 3D memory device is shown in the figures.

Although the semiconductor substrate, gate stack structure and associated internal structures are not shown, it will be appreciated that a common source region is formed in the semiconductor substrate and a channel column is formed in the gate stack structure. The gate stack structure includes a plurality of gate conductor layers and a plurality of intermediate interlayer insulating layers that are alternately stacked, and a top interlayer insulating layer that covers the topmost gate conductor layer. The plurality of channel columns penetrate through the plurality of gate conductor layers of the gate stack structure. Referring to fig. 1b, the channel pillar includes, for example, a channel layer, a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer, which are sandwiched between a gate conductor layer and the channel layer, thereby forming a memory transistor. The middle interlayer insulating layer and the top interlayer insulating layer of the gate stack structure are composed of the same material, for example, silicon oxide formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) using Tetraethylorthosilicate (TEOS) as a raw material.

As shown in fig. 2a, a plurality of conductive vias 121 are formed in the top interlayer insulating layer 101 above the gate stack structure.

In this step, a photoresist mask is formed on the top interlayer insulating layer 101, and then anisotropic etching is performed to form a via hole, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. The photoresist mask is removed by dissolving or ashing in a solvent after etching. Then, the via hole is filled with a conductive material, such as tungsten and/or polysilicon, for example, using a deposition process, and then portions of the conductive material outside the via hole are removed using chemical mechanical planarization, and portions of the conductive material inside the via hole remain to form the conductive via 121.

After the conductive vias 121 are formed, an additional top interlayer insulating layer is formed to cover the conductive vias 121. The multiple top interlayer insulating layers above the gate stack structure are shown as a single top interlayer insulating layer 101 in the figure, the conductive via 121 is located inside the top interlayer insulating layer 101, the bottom end of the conductive via 121 contacts the top surface of the channel pillar, and the top end is adjacent to the upper surface of the top interlayer insulating layer 101.

As shown in fig. 2b, a plurality of openings 131 extending downward from the surface are formed in the top interlayer insulating layer 101.

In this step, a photoresist mask PR1 is formed on the top interlayer insulating layer 101, and then anisotropic etching is performed to form the opening 131. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. At least some of the openings 131 are aligned with the conductive vias 121, stopping etching at the top surfaces of the conductive vias 121 due to the selectivity of the etchant. At least some of the openings 131 are not aligned with the conductive vias 121 and extend below the top surfaces of adjacent conductive vias 121 due to over-etching. The photoresist mask PR1 is removed by dissolving or ashing in a solvent after etching.

As shown in fig. 2c, the plurality of openings 131 are filled with a conductive material to form a plurality of bit lines 122.

In this step, the plurality of openings 131 are filled with a conductive material, such as tungsten and/or polysilicon, for example, using a deposition process, and then portions of the conductive material outside the openings 131 are removed using chemical mechanical planarization, and portions of the conductive material inside the openings 131 remain to form the plurality of bit lines 122. At least some of the bit lines 122 are connected with the channel pillars via conductive vias 121. At least some of the bit lines are not connected to the conductive vias 121 and the channel pillars to serve as dummy bit lines to improve metal distribution uniformity.

Further, a capping insulating layer 124 is formed over the plurality of bit lines 122 using a deposition process, thereby completing the main structure of the 3D memory device 200. The capping insulating layer 124 separates an internal structure of the 3D memory device and an external circuit from each other, and pads connected to the bit lines 122 are formed on a surface of the capping insulating layer to provide electrical connection with the external circuit. Although not shown in the drawings, it is understood that additional levels of wiring layers and conductive vias may also be formed between the blanket insulating layer 124 and the plurality of bit lines 122.

In the above-described method of manufacturing a bit line for a 3D memory device according to the related art, the bit line is formed by filling a via hole with a conductive material, and the bit line is electrically connected to the channel pillar via the conductive via. Since the via hole and the bit line opening are formed using similar masks and anisotropic etching processes, the cross-sectional shapes of the via hole and the bit line opening are similar to each other, and the respective widths are gradually reduced as the depth extending downward increases. In the top interlayer insulating layer, connection positions of the bit lines and the conductive vias form bottle necks. The bit lines adjacent to each other are spaced apart by a minimum spacing W1 of the bottle neck, which is substantially equal to the distance between the bottom surface of a bit line and the top surface of an adjacent conductive via.

Due to the existence of the bottleneck portion, the bit line manufacturing method according to the prior art has difficulty in simultaneously considering the read-write speed and the reliability of the 3D memory device. If the thickness of the top interlayer insulating layer is directly reduced, the parasitic capacitance of the bit line may be reduced to improve the read/write speed of the 3D memory device, however, the breakdown voltage of the 3D memory device may also be deteriorated due to premature breakdown occurring at the bottle neck. For example, a top interlayer insulating layer is formed using TEOS oxide, and the breakdown voltage of the 3D memory device is less than 8.5V when the thickness of the top interlayer insulating layer is less than 7 nm. If the top interlayer insulating layer is formed using a low-K material, the parasitic capacitance of the bit line may be reduced to improve the read/write speed of the 3D memory device, however, the breakdown voltage of the 3D memory device may also be deteriorated due to premature breakdown occurring at the bottleneck portion.

Fig. 3 shows a flow chart of a method for fabricating a bit line of a 3D memory device according to a first embodiment of the present application, and fig. 4a to 4k show schematic cross-sectional views of different steps of the method for fabricating a bit line of a 3D memory device according to the first embodiment of the present application. For clarity, only a portion of the structure of the 3D memory device is shown in the figures.

In step S01, a conductive layer 122, a first mask stack 11 and a second mask stack 12 are formed on the top interlayer insulating layer 101, as shown in fig. 4 a.

The conductive layer 122 is located on the surface of the top interlayer insulating layer 101 and is in contact with the conductive via 121.

In this embodiment, the conductive layer 122 is composed of tungsten and/or polysilicon, for example, a metal layer of tungsten formed by chemical vapor deposition.

The first mask stack 11 includes mask layers 102 and 103 stacked over the conductive layer 122. In this embodiment, the mask layer 102 is composed of nitride, for example, a mask layer of silicon nitride is formed using chemical vapor deposition, and the mask layer 103 is composed of polysilicon, for example, a mask layer of polysilicon is formed using chemical vapor deposition.

The second mask stack 12 comprises mask layers 104 and 105 stacked over the first mask stack 11. In this embodiment, the mask layer 104 is comprised of, for example, spin-on-carbon (SOC) for obtaining a flat surface topography, and the mask layer 105 is comprised of, for example, an oxynitride, for example, a silicon oxynitride mask layer formed using chemical vapor deposition for providing etchant selectivity.

In step S02, a hard mask 21 of the bit line is formed in the opening 131 of the second mask stack 12 by using a sidewall process, as shown in fig. 4b to 4 e.

In this step, a photoresist mask PR1 is formed on the second mask stack 12, as shown in fig. 4 b. Then, the exposed portion of the second mask stack 12 is removed by anisotropic etching through the photoresist mask PR1 to form an opening 131. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In this etching process, the mask layer 103 of the first mask stack 11 acts as an etch stop layer, with the selectivity of the etchant, such that the opening 131 penetrates the mask layers 104 and 105 of the second mask stack 12. The opening 131 includes sidewalls that are aligned with the conductive vias 121, as shown in fig. 4 c. After the etching, the photoresist mask PR1 is removed by dissolving or ashing in a solvent.

Further, a conformal mask layer 106 is formed over the entire surface of the second mask stack 12, as shown in fig. 4 d. The mask layer 106 is comprised of an oxide, for example, atomic layer deposition is used to form a mask layer of silicon oxide. The mask layer 106 has a thickness smaller than the width and depth of the opening 131, and covers not only the surface of the second mask layer 12 but also the sidewalls and bottom surface of the opening 131.

Further, a portion of the mask layer 106 on the surface of the second mask layer 12 and a portion on the bottom surface of the opening 131 are removed by anisotropic etching, and only a portion of the mask layer 106 on the sidewall of the opening 131 remains to form the hard mask 21. Then, the mask layers 104 and 105 of the second mask stack 12 are removed using an isotropic etch. Since the sidewalls of the opening 131 are aligned with the conductive via 121, the hard mask 21 is a sidewall on the sidewalls of the opening 131, and therefore, the hard mask 21 is also aligned with the conductive via 121, as shown in fig. 4 e.

In step S03, a third mask stack 13 is formed on the first mask stack 11, as shown in fig. 4 f.

In this step, the third mask stack 13 is similar in structure to the second mask layer 12, including mask layers 107 and 108 stacked over the first mask stack 11. In this embodiment, the mask layer 107 is composed of, for example, spin-on carbon (SOC) for covering the hard mask 21 and obtaining a flat surface topography, and the mask layer 108 is composed of, for example, oxynitride for providing selectivity of an etchant by forming a mask layer of silicon oxynitride using, for example, chemical vapor deposition.

In step S04, a hard mask 22 for the bit line is formed using the third mask stack 13, as shown in fig. 4 g.

In this step, a photoresist mask PR2 is formed on the third mask stack 13. Then, the exposed portions of the third mask stack 13 are removed by anisotropic etching through the photoresist mask PR2 to form the hard mask 22. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In this etching process, the mask layer 103 of the first mask stack 11 acts as an etch stop layer. Hard mask 21 is exposed in opening 132 of hard mask 22 and hard mask 21 and hard mask 22 together comprise a complete mask for the bit line as shown in figure 4 g. After the etching, the photoresist mask PR2 is removed by dissolving or ashing in a solvent.

In step S05, the first mask stack 11 is patterned using the hard mask 21 and the hard mask 22 to form the hard mask 23 for the bit line, as shown in fig. 4h to 4 i.

In this step, the mask layer 103 in the first mask stack 11 is removed by anisotropic etching through the hard mask 21 and the hard mask 22 to form a hard mask 23, as shown in fig. 4 h. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In this etching process, the mask layer 102 of the first mask stack 11 acts as an etch stop layer. The hard mask 23 corresponds to a bit line shape, and the opening 133 of the hard mask 23 corresponds to a bit line isolation. After the etching, the hard mask 21 and the hard mask 22 are removed by selective etching.

Further, the mask layer 102 in the first mask stack 11 is removed by anisotropic etching through the hard mask 23 to form a patterned hard mask 24, as shown in fig. 4 i. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In this etching process, the conductive layer 122 serves as an etch stop layer. Patterned hard mask 24 corresponds to the bitline shapes and openings 134 of patterned hard mask 24 correspond to the bitline isolations. After the etching, the hard mask 23 is removed by selective etching.

In step S06, conductive layer 122 is patterned using patterned hard mask 24 to form bit lines, as shown in fig. 4 j.

In this step, the exposed portions of conductive layer 122 are removed by anisotropic etching through patterned hard mask 24 to form openings 135, thereby patterning the conductive layer 122 into bit lines 25, as shown in fig. 4 j. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In this etching process, the depth of the opening 135 is controlled by controlling the timing of the etching. Due to the over-etching, the opening 135 penetrates not only the conductive layer 122 but also extends into the top interlayer insulating layer 101 to a predetermined depth.

Further, a capping insulating layer 124 is formed over the patterned hard mask 24 using a deposition process, thereby completing the main structure of the 3D memory device 300. The cap insulating layer 124 fills the opening 135 to provide isolation between bit lines, as shown in fig. 4 k. The capping insulating layer 124 separates an internal structure of the 3D memory device and an external circuit from each other, and a pad connected to the bit line 25 is formed on a surface of the capping insulating layer to provide an electrical connection with the external circuit. Although not shown in the drawings, it is understood that additional levels of wiring layers and conductive vias may also be formed between the blanket insulating layer 124 and the bit lines 25.

In the above method for manufacturing a bit line of a 3D memory device according to an embodiment of the present application, a first hard mask is formed by using a sidewall process, the first hard mask is exposed in an opening of a second hard mask, the first hard mask and the second hard mask together form a complete mask of the bit line, and the complete mask is transferred into a conductive layer via a first mask stack to form the bit line. The width of the bit line formed by the manufacturing method corresponds to the film thickness of the conformal layer in the side wall process, and the space between the bit lines corresponds to the opening width in the side wall process and the film thickness of the conformal layer, so that the bit lines with small width and small space can be realized by controlling the opening width in the side wall process and the film thickness of the conformal layer. Since the bit line pattern is transferred using the first mask stack, the cross-sectional shape of the bit line is substantially rectangular, and the bit line width and bit line pitch increase substantially constant along the depth extending downward. The bit lines have a width corresponding to the film thickness of the conformal layer, and the spacing between the bit lines is substantially equal to the minimum spacing W2 between the top surfaces of the bit lines.

According to the bit line manufacturing method, the read-write speed and the reliability of the 3D memory device can be considered at the same time. In this embodiment, the cap insulating layer 124 is formed using, for example, a low-K oxide (having a dielectric constant of about 2.6) instead of TEOS oxide (having a dielectric constant of about 4.1). The cap insulating layer 124 fills the openings between adjacent bit lines forming the dielectric between the bit lines. With the reduction of the bit line width and the bit line pitch, the parasitic capacitance of the bit line can be also significantly reduced by about 37% in the case of using the low-K oxide, so that the RC delay can be reduced, and the read-write speed of the 3D memory device can be improved. The fabrication method employs a hard mask pattern transfer technique that eliminates bottlenecks, and the bitline width and bitline pitch increase substantially constant along the depth of the downward extension. Even if the bit line pitch is reduced, the breakdown voltage of the 3D memory device can meet design requirements without premature breakdown, and thus the reliability of the 3D memory device can be improved.

A bit line fabrication method of a 3D memory device according to a second embodiment of the present application includes the steps of fig. 4a to 4 j.

Further, a capping insulating layer 124 is formed over the patterned hard mask 24 using a deposition process, thereby completing the main structure of the 3D memory device 300. The insulating cover layer 124 closes only the opening 135 and provides isolation between bit lines using the opening 135 as an air gap, as shown in fig. 5. The capping insulating layer 124 separates an internal structure of the 3D memory device and an external circuit from each other, and a pad connected to the bit line 25 is formed on a surface of the capping insulating layer to provide an electrical connection with the external circuit. Although not shown in the drawings, it is understood that additional levels of wiring layers and conductive vias may also be formed between the blanket insulating layer 124 and the bit lines 25.

Compared with the first embodiment, the bit line manufacturing method according to the embodiment of the application can further improve the read-write speed and reliability of the 3D memory device. In this embodiment, the insulating cover layer 124 only closes the openings 135, so that the openings between adjacent bit lines retain air (dielectric constant of about 1) as the dielectric between the bit lines. The dielectric constant can be further reduced compared to low K oxide (dielectric constant of about 2.6). With the reduction of the bit line width and the bit line pitch, the parasitic capacitance of the bit line can be further reduced under the condition of adopting air as a dielectric, so that the RC delay can be reduced, and the read-write speed of the 3D memory device can be improved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present application are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present application. The scope of the application is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present application, and such alternatives and modifications are intended to be within the scope of the present application.

Claims

1. A bit line structure of a 3D memory device, comprising:

a top interlayer insulating layer including at least one conductive via;

the bit lines are provided with openings among the bit lines, and the openings are filled with low-K dielectrics.

2. The bit line structure of claim 1, further comprising:

3. The bit line structure of claim 2, wherein the cap insulating layer fills the opening; wherein the blanket insulating layer is comprised of a low-K material; the cover insulating layer filled in the opening serves as the low-K dielectric.

4. The bitline structure of claim 3, in which the low-K material is a low-K oxide.

5. The bitline structure of claim 2, in which the cap insulating layer closes the opening such that air in the opening acts as the low-K dielectric.

6. The bit line structure of claim 5, further comprising additional levels of routing layers between the blanket insulating layer and the plurality of bit lines.

7. The bit line structure of claim 1, further comprising:

8. The bit line structure of claim 7, wherein the bit line cross-section is rectangular, and wherein the bit line width is constant, and wherein the bit line pitch is constant along the bit line depth direction.

9. The bit line structure of claim 8, wherein the bit line pitch is equal to a minimum pitch between top surfaces of the bit lines.

10. The bitline structure of claim 7, wherein the patterned hardmask corresponds to a shape of the bitline, and wherein the openings of the patterned hardmask correspond to isolations between the bitlines.

11. The bitline structure of claim 7, wherein the patterned hardmask is comprised of silicon nitride.

12. The bitline structure of any of claims 1 to 11, wherein the bitline is comprised of tungsten and/or polysilicon.

13. A 3D memory device, comprising:

the bit line structure of any of claims 1 to 12;

14. The 3D memory device of claim 13, wherein the 3D memory device further comprises:

a semiconductor substrate;

15. The 3D memory device of claim 14, wherein the channel pillar penetrates a plurality of gate conductor layers and a plurality of the interlayer insulating layers of the gate stack structure.

16. The 3D memory device of claim 14, wherein the channel pillar comprises:

17. The 3D memory device of claim 16, wherein the tunneling dielectric layer, the charge storage layer, and the gate dielectric layer are sandwiched between the gate conductor layer and the channel layer.