CN114188333A - Semiconductor memory, manufacturing method thereof and electronic equipment - Google Patents

Semiconductor memory, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN114188333A
CN114188333A CN202111340824.XA CN202111340824A CN114188333A CN 114188333 A CN114188333 A CN 114188333A CN 202111340824 A CN202111340824 A CN 202111340824A CN 114188333 A CN114188333 A CN 114188333A
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China
Prior art keywords
array common
common source
semiconductor memory
source connection
layer
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CN202111340824.XA
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Chinese (zh)
Inventor
赵祥辉
曾臻
阳叶军
张文杰
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111340824.XA priority Critical patent/CN114188333A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention provides a semiconductor memory, a manufacturing method thereof and electronic equipment, comprising the following steps: a substrate; the control grid stacking structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation mode; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source isolating layer; the insulating filling layer covers one side, away from the substrate, of the array common source connecting layer and is filled to a groove between the adjacent array common source connecting layers, and the insulating filling layer comprises a through hole corresponding to the array common source connecting layer; and the bridge connecting line is positioned on one side of the insulating filling layer, which is far away from the substrate, and is connected with the two adjacent array common source connecting layers through the through hole.

Description

Semiconductor memory, manufacturing method thereof and electronic equipment
The present application is a divisional application of a patent entitled "semiconductor memory and method of manufacturing the same, electronic device" having an application date of 07/05/2020 and an application number of 202010377292.6.
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a semiconductor memory, a manufacturing method thereof and electronic equipment.
Background
The NAND flash memory is a nonvolatile memory product with low power consumption, light weight and good performance, and is widely applied to electronic products. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed. When a 3D NAND memory is manufactured in the prior art, the situation that a gate stack structure is damaged in the manufacturing process often occurs.
Disclosure of Invention
In view of this, the present invention provides a semiconductor memory, a manufacturing method thereof, and an electronic device, which effectively solve the technical problems in the prior art and avoid the damage to the control gate stack structure during the manufacturing of the semiconductor memory.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a semiconductor memory, comprising:
a substrate;
the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner;
the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer;
the insulating filling layer covers one side, away from the substrate, of the array common source connection layer and is filled to a groove between the adjacent array common source connection layers, and the insulating filling layer comprises a through hole corresponding to the array common source connection layer;
and the bridge connecting line is positioned on one side, away from the substrate, of the insulating filling layer and is connected with the two adjacent array common source connecting layers through the through hole.
Optionally, the insulating filling layer includes a trench at a position corresponding to the bridge connection line, and the bridge connection line is located in the corresponding trench.
Optionally, the bridge connection line and the array common source connection layer are made of the same material.
Optionally, the bridge connection line and the array common source connection layer are made of tungsten.
Optionally, the semiconductor memory is a 3D NAND memory.
Correspondingly, the invention also provides a manufacturing method of the semiconductor memory, which comprises the following steps:
providing a base, wherein the base comprises a substrate; the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer; the insulating filling layer covers one side, away from the substrate, of the array common source connecting layer and is filled to a groove between the adjacent array common source connecting layers;
forming a through hole corresponding to the array common source connection layer on the insulation filling layer;
and forming a bridge connecting line on one side of the insulating filling layer, which is far away from the substrate, wherein the bridge connecting line is connected with the bridge connecting lines of two adjacent array common source connecting layers through the through holes.
Optionally, after the forming of the through hole and before the forming of the bridge connection line, the method further includes:
and forming a groove between the through holes corresponding to the two adjacent array common source connection layers, wherein the bridge connection line is positioned in the groove.
Optionally, the bridge connection line and the array common source connection layer are made of the same material.
Optionally, the bridge connection line and the array common source connection layer are made of tungsten.
Correspondingly, the invention also provides electronic equipment which comprises the semiconductor memory.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a semiconductor memory, a manufacturing method thereof and electronic equipment, comprising the following steps: a substrate; the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer; the insulating filling layer covers one side, away from the substrate, of the array common source connection layer and is filled to a groove between the adjacent array common source connection layers, and the insulating filling layer comprises a through hole corresponding to the array common source connection layer; and the bridge connecting line is positioned on one side, away from the substrate, of the insulating filling layer and is connected with the two adjacent array common source connecting layers through the through hole.
According to the technical scheme provided by the invention, when two adjacent array common source connecting layers are electrically connected, only the through holes are formed at the positions, corresponding to the array common source connecting layers, of the insulating filling layer, and then the bridge connecting lines are formed on the insulating filling layer, and the electric connection is realized through the through holes corresponding to the two adjacent array common source connecting layers. The invention does not need to carry out large-area hole digging and other treatments on the corresponding control gate stacking structure of the insulating filling layer, and avoids the condition of damaging the control gate stacking structure when manufacturing the semiconductor memory.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present invention;
fig. 2 is a top view of a semiconductor memory according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another semiconductor memory according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for fabricating a semiconductor memory according to an embodiment of the present invention;
fig. 5 is a flowchart of another method for manufacturing a semiconductor memory according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, the NAND flash memory is a nonvolatile memory product with low power consumption, light weight, and good performance, and is widely used in electronic products. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed. When a 3D NAND memory is manufactured in the prior art, the situation that a gate stack structure is damaged in the manufacturing process often occurs.
Accordingly, embodiments of the present invention provide a semiconductor memory, a manufacturing method thereof, and an electronic device, which effectively solve the technical problems in the prior art and avoid damage to a control gate stack structure during manufacturing of the semiconductor memory.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 5.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present invention, and fig. 2 is a top view of the semiconductor memory according to the embodiment of the present invention. Wherein, the semiconductor memory includes:
a substrate 100.
A plurality of control gate stack structures 210 and a plurality of array common source partition layers 220 (array common sources) located on one side surface of the substrate 100 and alternately arranged in isolation.
An array common source connection layer 300 located on a side of the array common source blocking layer 220 facing away from the substrate 100.
An insulating filling layer 400 (insulating layer) covering one side of the array common source connection layer 300, which faces away from the substrate 100, and filling the groove (space) between the adjacent array common source connection layers 300, wherein the insulating filling layer 400 comprises a through hole 410 corresponding to the array common source connection layer 300.
And a bridge connection line 500 (bridge structure) located on a side of the insulating filling layer 400 away from the substrate 100 and connecting two adjacent array common source connection layers 300 through the through hole 410.
It should be noted that the semiconductor memory provided in the embodiment of the present invention is located on a side of the bridge connection line away from the substrate, and further includes more constituent structures of the semiconductor memory, which is the same as the prior art, and therefore redundant description is not repeated.
It can be understood that according to the technical scheme provided by the embodiment of the invention, when two adjacent array common-source connecting layers are electrically connected, only the through hole is formed at the position, corresponding to the array common-source connecting layer, of the insulating filling layer, so that the bridge connecting line is formed on the insulating filling layer, and the electrical connection is realized through the through holes corresponding to the two adjacent array common-source connecting layers. According to the embodiment of the invention, large-area hole digging and other processing are not required to be carried out on the corresponding control gate stacking structure of the insulating filling layer, so that the situation that the control gate stacking structure is damaged when a semiconductor memory is manufactured is avoided.
In an embodiment of the present invention, after the bridge connection line is prepared, other component structures may be prepared on the surface of the bridge connection line and the insulating filling layer away from the substrate. Referring to fig. 3, a schematic structural diagram of another semiconductor memory according to an embodiment of the present invention is shown, where the semiconductor memory according to the present invention includes:
a substrate 100.
A plurality of control gate stack structures 210 and a plurality of array common source blocking layers 220 located on one side surface of the substrate 100 and alternately arranged in an isolated manner.
An array common source connection layer 300 located on a side of the array common source blocking layer 220 facing away from the substrate 100.
And an insulating filling layer 400 covering one side of the array common source connection layer 300, which faces away from the substrate 100, and filling the insulating filling layer 400 to a groove between adjacent array common source connection layers 300, wherein the insulating filling layer 400 comprises a through hole 410 corresponding to the array common source connection layer 300.
And a bridge wire 500 located on one side of the insulating filling layer 400, which faces away from the substrate 100, and connecting two adjacent array common source connection layers 300 through the through hole 410.
The insulating filling layer 400 provided by the embodiment of the present invention includes trenches 420 communicating with the two corresponding through holes 410 at positions corresponding to the bridge lines 500, and the bridge lines 500 are located in the corresponding trenches 420.
It can be understood that the insulating filling layer provided by the embodiment of the invention forms a trench communicating between two through holes connected by a bridge line on the side of the insulating filling layer away from the substrate, and then the bridge line is formed in the trench, so that the height difference between the bridge line and the surface of the insulating filling layer on the side away from the substrate is reduced, and the subsequent component preparation is facilitated. Furthermore, the surface of the bridge wire, which faces away from the substrate, is flush with the surface of the insulating filling layer, which faces away from the substrate, so that the side surface is a planarized surface to further facilitate the preparation of subsequent components thereon.
In an embodiment of the invention, the bridge connection line and the array common source connection layer provided by the invention are made of the same material. Specifically, the bridge connecting line and the array common source connecting layer provided by the invention can be made of metal materials; optionally, the bridge connection line and the array common source connection layer are made of tungsten.
The insulating filling layer provided in the embodiment of the present invention may be made of an oxide material, and the array common source partition layer may be made of doped polysilicon, which is not limited in the present invention.
In addition, the shape of the through hole provided by the embodiment of the present invention may be a cylindrical through hole, a rectangular through hole, or the like, and the shape and the size of the through hole are not particularly limited.
In an embodiment of the present invention, the semiconductor memory provided by the embodiment of the present invention is a 3D NAND memory.
Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor memory, which is a flowchart of the method for manufacturing the semiconductor memory according to the embodiment of the present invention with reference to fig. 4, where the method for manufacturing the semiconductor memory includes:
s1, providing a base, wherein the base comprises a substrate; the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer; and the insulating filling layer covers one side of the array common source connecting layer, which is far away from the substrate, and is filled to the groove between the adjacent array common source connecting layers.
And S2, forming a through hole corresponding to the array common source connection layer on the insulation filling layer.
And S3, forming a bridge connecting line on one side, away from the substrate, of the insulating filling layer, wherein the bridge connecting line is connected with the bridge connecting lines of two adjacent array common source connecting layers through the through holes.
It should be noted that, in the manufacturing method provided in the embodiment of the present invention, after the bridge connection line is manufactured, the other constituent structures of the semiconductor memory need to be manufactured on the side of the semiconductor memory, which is located on the side of the bridge connection line away from the substrate, which is the same as the prior art, and therefore, redundant description is not repeated.
It can be understood that according to the technical scheme provided by the embodiment of the invention, when two adjacent array common-source connecting layers are electrically connected, only the through hole is formed at the position, corresponding to the array common-source connecting layer, of the insulating filling layer, so that the bridge connecting line is formed on the insulating filling layer, and the electrical connection is realized through the through holes corresponding to the two adjacent array common-source connecting layers. According to the embodiment of the invention, large-area hole digging and other processing are not required to be carried out on the corresponding control gate stacking structure of the insulating filling layer, so that the situation that the control gate stacking structure is damaged when a semiconductor memory is manufactured is avoided.
In an embodiment of the present invention, after the bridge connection line is prepared, other component structures may be prepared on the surface of the bridge connection line and the insulating filling layer away from the substrate. Specifically after forming the through hole and before forming the bridge connecting line, the method further includes: and forming a groove between the through holes corresponding to the two adjacent array common source connection layers, wherein the bridge connection line is positioned in the groove.
Referring to fig. 5, a flowchart of a manufacturing method of another semiconductor memory according to an embodiment of the present invention is shown, where the manufacturing method includes:
s1, providing a base, wherein the base comprises a substrate; the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer; and the insulating filling layer covers one side of the array common source connecting layer, which is far away from the substrate, and is filled to the groove between the adjacent array common source connecting layers.
And S2, forming a through hole corresponding to the array common source connection layer on the insulation filling layer.
And S21, forming a groove between the through holes corresponding to the array common source connection layers.
And S3, forming a bridge connecting line on one side, away from the substrate, of the insulating filling layer, wherein the bridge connecting line is connected with the bridge connecting lines of two adjacent array common source connecting layers through the through holes, and the bridge connecting lines are located in the grooves.
It can be understood that the insulating filling layer provided by the embodiment of the invention forms a trench communicating between two through holes connected by a bridge line on the side of the insulating filling layer away from the substrate, and then the bridge line is formed in the trench, so that the height difference between the bridge line and the surface of the insulating filling layer on the side away from the substrate is reduced, and the subsequent component preparation is facilitated. Furthermore, the surface of the bridge wire, which faces away from the substrate, is flush with the surface of the insulating filling layer, which faces away from the substrate, so that the side surface is a planarized surface to further facilitate the preparation of subsequent components thereon.
In an embodiment of the invention, the bridge connection line and the array common source connection layer provided by the invention are made of the same material. Specifically, the bridge connecting line and the array common source connecting layer provided by the invention can be made of metal materials; optionally, the bridge connection line and the array common source connection layer are made of tungsten.
The insulating filling layer provided in the embodiment of the present invention may be made of an oxide material, and the array common source partition layer may be made of doped polysilicon, which is not limited in the present invention.
In addition, the shape of the through hole provided by the embodiment of the present invention may be a cylindrical through hole, a rectangular through hole, or the like, and the shape and the size of the through hole are not particularly limited.
In an embodiment of the present invention, the semiconductor memory provided by the embodiment of the present invention is a 3D NAND memory.
Correspondingly, the embodiment of the invention also provides electronic equipment, and the electronic equipment comprises the semiconductor memory provided by any one of the embodiments.
The embodiment of the invention provides a semiconductor memory, a manufacturing method thereof and electronic equipment, wherein the semiconductor memory comprises the following steps: a substrate; the control gate stack structures and the array common source partition layers are positioned on the surface of one side of the substrate and are alternately arranged in an isolation manner; the array common source connecting layer is positioned on one side, away from the substrate, of the array common source blocking layer; the insulating filling layer covers one side, away from the substrate, of the array common source connection layer and is filled to a groove between the adjacent array common source connection layers, and the insulating filling layer comprises a through hole corresponding to the array common source connection layer; and the bridge connecting line is positioned on one side, away from the substrate, of the insulating filling layer and is connected with the two adjacent array common source connecting layers through the through hole.
As can be seen from the above, according to the technical scheme provided in the embodiment of the present invention, when two adjacent array common-source connection layers are electrically connected, only the through hole is formed at the position of the insulating filling layer corresponding to the array common-source connection layer, so that the bridge connection line is formed on the insulating filling layer, and the through holes corresponding to the two adjacent array common-source connection layers are electrically connected. According to the embodiment of the invention, large-area hole digging and other processing are not required to be carried out on the corresponding control gate stacking structure of the insulating filling layer, so that the situation that the control gate stacking structure is damaged when a semiconductor memory is manufactured is avoided.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (17)

1. A semiconductor memory, comprising:
a plurality of control gate stack structures and a plurality of array common sources arranged alternately;
an array common source connection layer on the array common source;
an insulating layer located on the array common source connection layer and at a space between adjacent array common source connection layers;
the through hole is positioned in the insulating layer and corresponds to the array common source connecting layer;
the bridging structure is positioned on one side, away from the array common source connecting layer, of the insulating layer and is connected with two adjacent array common source connecting layers through the through holes; wherein the control gate stack structure comprises a first surface and a second surface opposite to each other, the first surface being closer to the bridging structure than the second surface, an orthographic projection of the bridging structure on a plane of the first surface at least partially overlapping the control gate stack structure.
2. The semiconductor memory according to claim 1, wherein the array common source connection layer comprises a third surface and a fourth surface opposite to each other, the third surface is closer to the insulating layer than the fourth surface, and an orthographic projection of the via on a plane of the third surface overlaps with the array common source connection layer.
3. The semiconductor memory of claim 1, wherein the insulating layer is at least partially between the bridging structure and the control gate stack structure.
4. The semiconductor memory of claim 1, wherein the insulating layer includes trenches corresponding to the bridging structures, the bridging structures being located within respective trenches.
5. The semiconductor memory according to claim 1, wherein the bridge structure and the array common source connection layer are made of the same material.
6. The semiconductor memory according to claim 1, wherein the material of the bridge structure and the array common source connection layer comprises metal.
7. The semiconductor memory according to claim 6, wherein the metal comprises tungsten.
8. The semiconductor memory according to claim 1, wherein the semiconductor memory is a 3D NAND memory.
9. The semiconductor memory according to claim 1, wherein the array common-source and the array common-source connection layer are made of different materials.
10. The semiconductor memory according to claim 9, wherein the material of the array common source comprises doped polysilicon, and the material of the array common source connection layer comprises tungsten.
11. The semiconductor memory of claim 1, further comprising a substrate on a side of the control gate stack structure and the array common source away from the bridging structure.
12. The semiconductor memory according to any one of claims 1 to 11, wherein the bridging structure extends from one end of one of the array common-source connection layers to one end of the other of the array common-source connection layers in two adjacent array common-source connection layers; and in the direction extending along the bridging structure, partial structures of the array common source connection layer are staggered with the bridging structure.
13. A method for manufacturing a semiconductor memory, comprising:
providing a substrate, wherein the substrate comprises a plurality of control gate stack structures and a plurality of array common sources which are arranged alternately; an array common source connection layer on the array common source; an insulating layer located on the array common source connection layer and at a space between adjacent array common source connection layers;
forming a through hole corresponding to the array common source connection layer in the insulating layer;
forming a bridging structure; the bridging structure is positioned on one side of the insulating layer, which is far away from the array common source connecting layer, and two adjacent array common source connecting layers are connected through the through hole; the control gate stack structure comprises a first surface and a second surface opposite to each other, the first surface is closer to the bridging structure than the second surface, and an orthographic projection of the bridging structure on a plane of the first surface at least partially overlaps with the control gate stack structure.
14. The method of claim 13, further comprising, after forming the via and before forming the bridging structure:
and forming a groove between the through holes corresponding to the two adjacent array common source connection layers, wherein the bridging structure is positioned in the groove.
15. The method as claimed in claim 13, wherein the bridge structure and the array common-source connection layer are made of the same material, and the array common-source connection layer are made of different materials.
16. The method of claim 15, wherein the material of the bridge structure and the array common source connection layer comprises tungsten; and/or the presence of a gas in the gas,
the material of the array common source comprises doped polysilicon.
17. An electronic device characterized in that the electronic device comprises the semiconductor memory according to any one of claims 1 to 12.
CN202111340824.XA 2020-05-07 2020-05-07 Semiconductor memory, manufacturing method thereof and electronic equipment Pending CN114188333A (en)

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