TW201814885A - 3D capacitor and manufacturing method for the same - Google Patents

Abstract

An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.

Description

Three-dimensional capacitor and manufacturing method thereof

This invention relates to a memory device, and more particularly to a 3D array memory device including a three-dimensional (3D) capacitance therein.

The critical size of the device in the integrated circuit is reduced to the limit of the shared memory cell technology, and designers seek to stack multi-level memory cells to achieve greater storage capacity and lower cost per bit. Therefore, a variety of three-dimensional structures are developed, such as vertical channel and vertical gate NAND memory. Capacitors can be used to help reduce voltage variations and can be used to help save data in, for example, SRAM, DRAM, and flash memory during normal operation or due to unexpected power failures. In the stylization and erasing operations, the charge pump is used to provide a bias voltage to the word line/bit line to boost the voltage at the high voltage level, which requires high capacitance. However, a typical capacitor that provides a large capacitance value will occupy a large area of a predetermined footprint, which affects the expandability of the memory device.

Therefore, it is desirable to provide a capacitor including a stable large capacitance value, a small occupied area, and no increase in manufacturing cost.

The 3D capacitor includes a plurality of staggered plurality of conductive strips and a plurality of insulated plurality of conductive strips, a first terminal and a second terminal. The first terminal is connected to a plurality of conductive strips in the consecutive levels of the stacks of the first set of spaced stacks in the stack. The second terminal is connected to the plurality of conductive strips in the successive layers of the stacks in the second set of spaced stacks in the stack. The stack in the first set of spaced stacks is interdigitated in a stack in the second set of spaced stacks. The conductive strips in successive layers in the stack in the first set of spaced stacks are electrically and passively connected together and act as a first plate of the 3D capacitor, and the successive layers in the stack in the second set of spaced stacks The conductive strips are electrically and passively connected together and act as a second plate of the 3D capacitor. The inserted conductive strips are not disposed between the conductive strips in successive layers in the stack of the first set of spaced stacks. Similarly, the inserted conductive strips are not disposed between the conductive strips in successive layers in the stack of the second set of spaced stacks.

The 3D capacitor includes one or more stacks of conductive strips and insulating strips, a plurality of pillars, a first terminal and a second terminal. The plurality of pillars respectively comprise a vertical conductive film and a first insulator. The first terminal is connected to the conductive strips in one or more of the stacks. The second terminal is connected to the vertical conductive film in the plurality of pillars. The conductive strips in the one or more stacks are electrically and passively connected together and act as a first plate of the 3D capacitor, and the vertical conductive films in the plurality of columns are electrically and passively connected together And acts as the second plate of the 3D capacitor.

In one concept, a plurality of cylinders can be disposed on one or more stacked side walls.

In another concept, a plurality of cylinders can be placed through the conductive strips in a stack. In addition, the plurality of cylinders may have a staggered or honeycomb configuration.

In yet another concept, the 3D capacitor described herein effectively suppresses variable parasitic capacitance and can withstand voltages greater than 30V.

A method of manufacturing the 3D capacitor is also provided herein. A method of fabricating a 3D capacitor includes forming a plurality of stacked strips of conductive strips interleaved with the insulating strips; forming a first termination connected to the conductive strips in a continuous layer of the stack in the first set of spaced stacks of the plurality of stacks; and forming a A terminal is connected to the conductive strips in successive layers in the stack of the second set of spaced stacks in the plurality of stacks; wherein the stacks in the first set of spaced stacks are forked to the stack in the second set of spaced stacks.

A method of fabricating a 3D capacitor includes forming one or more stacks of staggered conductive strips and insulating strips; forming a plurality of pillars respectively including a vertical conductive film and a first insulator; forming a first terminal connected to the one or more stacks a conductive strip in the middle; and a vertical conductive film formed in the plurality of pillars formed by the second terminal.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

The embodiment will be described in detail below with reference to Figs. 3 to 33.

Figure 1 shows a simplified schematic of a charge pump. The charge pump is used to boost the lower input voltage Vin to a higher output voltage Vout. As illustrated in the schematic, the charge pump utilizes diodes D1-D4 to control the voltage connections to capacitors C1-C4 using opposite clocks CLK1, CLK2. In the ideal case where leakage current or other factors are not considered, when the pulse CLK1 is low, the diode D1 will charge the capacitor C1 to Vin. When the pulse CLK1 is high, the first terminal of the capacitor C1 is pushed up to 2Vin. The diode D1 is then turned off, and the diode D2 is turned on, and the capacitor C2 starts charging to 2Vin. On the next clock cycle, clock CLK1 is again low, and this time clock CLK2 is high and pushes the first terminal of capacitor C2 to 3Vin. The diode D2 is turned off and the diode D3 is turned on, and the charging capacitor C3 is 4Vin. Repeatedly, the output voltage Vout of the four-stage charge pump will be charged to 5Vin. Figure 1 is a simplified schematic diagram of a charge pump, and other charge pumps can be applied, as disclosed in U.S. Patent No. 6,366,519, the entire disclosure of which is hereby incorporated by reference in its entirety in its entirety in AND OTHER INTEGRATED CIRCUIT APPLICATIONS, inventor Hung et al.

Figure 2 illustrates a MOS capacitor, typically used in a charge pump, with an N-well (N-WELL) and an N+ doped source/drain in a P-type substrate (P-SUB). In order to have a large capacitance Cox, MOS capacitors require large-area plates such as gate (GATE) and N-type wells. The MOS capacitor must contain the parasitic capacitance Cdep caused by the N-well and the P-type substrate. The parasitic capacitance Cdep changes the voltage supplied to the N-well, which in turn causes high power consumption and results in unstable and variable capacitance.

3 is a simple block diagram of a 3D NAND memory device 100 that includes 3D memory blocks (eg, block 0 through block 3) and 3D capacitors (eg, CAP 0 through CAP 1) formed on the same substrate. The 3D capacitor can be used in a charge pump to supply the bias voltage required for the read, erase, and program operations of the memory device 100. 3D capacitors can also be used in other circuits, such as backup power supplies. Both the 3D NAND memory block and the 3D capacitor have multiple stacks and are almost compatible with many common deposition and etch steps, so the complexity and cost are not significantly improved.

Figure 4 is a perspective view of a 3D memory block applied to a NAND memory device. The memory block includes a plurality of stacks of conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 interleaved with insulating strips 1121, 1122, 1123, 1124, and 1125. The conductive strips 1103, 1104, 1105, and 1106 function as word lines (WL), and the conductive strips 1102 function as auxiliary gates (AGs). The conductive strip 1107 in the even stack acts as the gate of the ground select line (GSL) transistor. Similarly, the conductive strips 1107 in the odd stack act as the gates of a tandem select line (SSL) transistor. The post includes a vertical semiconductor/conductive film (e.g., 80a, 80b) disposed between the stack of adjacent conductive strips and a first insulator 69. The first insulator 69 functions as a data storage structure including a barrier layer 1130, a charge trapping layer 1131 such as hafnium oxide, a charge trapping layer 1131 such as tantalum nitride, and a tunneling layer 1132 such as hafnium oxide. A plurality of series of memory cell lines are located at the intersection between the pillars and the conductive strips (WL) 1103-1106.

The reference line structure and the bit line structure are disposed above the stack. A reference line structure, such as a section of reference lines 2031, 2034 in the first patterned conductive layer, may be disposed over a ground select line (GSL) in an even stack of conductive strips and connected to the active pillar at contact SL. A bit line structure, such as a segment of bit lines 2060, 2061, 2062 in the second patterned conductive layer, may be orthogonally disposed over the even and odd stacks of the conductive strips and through the inter-levels at the contact BL Inter-level connectors 2035, 2036, 2037 are attached to the cylinder.

Conductive strips of different levels (e.g., 1102, 1103, 1104, 1105, 1106, and 1107) are respectively connected to corresponding metal lines in the first patterned conductor layer above the stack through a step contact structure (not shown) at the landing pad area. Therefore, different levels of conductive strips in the same stack are not connected together.

Fig. 5 is a perspective view of a 3D capacitor according to the first embodiment. The 3D capacitor includes a plurality of stacks of conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 staggered across the insulating strips 1121, 1122, 1123, 1124, and 1125. a first terminal of the 3D capacitor is connected to the conductive strips of the plurality of consecutive stacks of the first set of spaced stacks (eg, even stacks) of the stacks, whereby the first set of spaced stacks The conductive strips are electrically and passively connected together and act as a first plate of the 3D capacitor. a second terminal of the 3D capacitor is connected to the conductive strips of the successive layers of the stacks of the second set of spaced stacks (eg, odd stacks) of the stacks, whereby the conductive strips in the second set of spaced stacks Electrically and passively connected together and function as a second plate of the 3D capacitor. The first terminal is insulated from the second terminal. The stacks in the first set of spaced stacks are interdigitated in a stack in the second set of spaced stacks. The second terminal is not connected to the conductive strips in the first set of spaced stacks.

In this example, the conductive strips connected to the first terminal include all of the conductive strips from the lowest level to the highest level, with no intervening conductive strips connected to the second terminal therebetween. Similarly, the conductive strips connected to the second terminal include all of the conductive strips from the lowest level to the highest level with no intervening conductive strips connected to the first terminal therebetween. In other examples, the conductive strips may include conductive strips of intermediate levels, such as conductive strips 1103 to 1106 of continuous layers, or conductive strips 1104 to 1106 of successive layers, with no intervening conductive strips therebetween. In still other examples, the conductive strips can include any level of conductive strips in the same stack, rather than a continuous level of conductive strips.

Figure 5A is an enlarged view of the 3D capacitor of Figure 5. In this example, the first insulator 69 is formed on the opposite side between the right side of the conductive strips 1105-E, 1106-E and the left side of the conductive strips 1105-0, 1106-O. The second insulator 3010 is disposed between the first insulators 69 on the opposite side. Conductive strips 1105-E and 1106-E are connected to the first terminal of the 3D capacitor and act as the first plate of the 3D capacitor. There is no conductive strip connected between the conductive strips 1105-E and 1106-E to the second terminal. Conductive strips 1105-O and 1106-O are connected to the second terminal of the 3D capacitor and act as a second plate of the 3D capacitor. There is no conductive strip connected between the conductive strips 1105-O and 1106-O to the first terminal. The dielectric of the 3D capacitor includes a first insulator 69 on the opposite side and a second insulator 3010 therebetween. Therefore, the capacitor C1 is formed between the bus bars 1106-E and 1106-O. Similarly, capacitor C2 is formed between conductive strips 1105-E and 1105-O. Assuming that the total thickness of the conductive strip is H μm, the length of the conductive strip is L μm, the distance between the first plate and the second plate is D, and the number of cells is N, then the total capacitance can be C = ε ₀ × ε × H × L × N / D is roughly estimated, where ε ₀ is the dielectric constant in vacuum, and ε is the dielectric constant of the first insulator and the second insulator.

Fig. 6 is a perspective view of a 3D capacitor according to the second embodiment. Most of the reference symbols used in FIG. 5 are applied to the following figures and will not be described again. The difference between the capacitance of FIG. 6 and the capacitance of FIG. 5 is that the first terminal of the 3D capacitor is connected to the conductive strip in each stack of the one or more stacks, and the second terminal of the 3D capacitor is connected to the one a plurality of columns on the sidewalls of the stack in the stack or more. In this example, the 3D capacitor includes a plurality of stacks of a plurality of conductive strips interleaved with a plurality of insulating strips, and the pillars respectively include a vertical conductive film (eg, 80a, 80b) and a first insulator 69. The conductive film 1140C is over the top of the stack in the plurality of stacks and over the first insulator 69 on the sidewalls. The conductive strips in the plurality of stacks are electrically and passively connected together to the first terminal of the 3D capacitor and function as the first plate of the 3D capacitor. The first terminal is insulated from the second terminal. Vertical conductive films (e.g., 80a, 80b) in the pillars adjacent the stack are electrically and passively connected together and function as a second plate of the capacitor. The first insulator 69 acts as a dielectric of the 3D capacitor. A fill structure 3060 is disposed adjacent the cylinder between the stacks, where holes may be formed.

In this example, the conductive strips of successive layers in the stack connected to the first terminal include conductive strips from the lowest level to the highest level, with no intervening conductive strips connected to the second terminal therebetween. In other examples, the conductive strips connected to the first terminal may include conductive strips of intermediate levels, such as from conductive strips 1103 to conductive strips 1106, with no intervening conductive strips connected thereto to the second terminal. In still other examples, the conductive strips connected to the first terminal may comprise conductive strips of any level in the same stack, rather than conductive strips of successive layers.

Figure 6A is an enlarged view of the 3D capacitor of Figure 6. In this example, the first insulator 69 is formed on the opposite side between the right side of the conductive strips 1105-E, 1106-E and the left side of the conductive strips 1105-0, 1106-O. Vertical conductive films (e.g., 80a, 80b) are formed over the first insulator 69 on the opposite side between adjacent stacks. The fill structure 3060 is disposed between vertical conductive films (eg, 80a, 80b) on opposite sides of the stack in the plurality of stacks. The conductive strips 1105-E, 1106-E, 1105-O, and 1106-O are electrically and passively connected to the first terminal of the 3D capacitor and function as a first plate of the 3D capacitor. Between the conductive strips 1105-E and 1106-E, and between the conductive strips 1105-O and 1106-O, no inserted conductive strips are provided. The vertical conductive films 80a and 80b are electrically and passively connected to the second terminal of the 3D capacitor and function as a second plate of the 3D capacitor. The first insulator acts as a dielectric of the 3D capacitor. Therefore, capacitors C1 - C4 are formed between the vertical conductive films 80a, 80b and the conductive strips 1106-E, 1105-E, 1106-O, and 1106-O, respectively. Assuming that the total thickness of the conductive strip is H μm, the length of the conductive strip is L μm, the distance between the first plate and the second plate is D _ONO , and the number of cells is N, then the total capacitance can be C = ε ₀ × ε × 2 (H × L) × N / D _ONO is roughly estimated, where ε ₀ is the dielectric constant in vacuum, and ε is the dielectric constant of the first insulator (ONO). The capacitance of Figure 6 contains at least twice the capacitance compared to the capacitance of Figure 5.

Fig. 7 is a perspective view of a 3D capacitor according to the third embodiment. The difference between the capacitance of FIG. 7 and the capacitance of FIG. 6 is that a plurality of column systems are disposed through the conductive strips, and the plurality of columns have a staggered or honeycomb configuration. The 3D capacitor includes one or more stacks of a plurality of conductive strips interleaved with a plurality of insulating strips, and the plurality of pillars respectively comprise a vertical conductive film and a first insulator 69. The first terminal of the 3D capacitor is connected to the Conductive strips in more than one stack, whereby the conductive strips are electrically and passively connected together and act as a first plate of the 3D capacitor. The second terminal of the 3D capacitor is connected to the vertical conductive film in the plurality of pillars, whereby the vertical conductive film is electrically and passively connected together and functions as a second plate of the 3D capacitor. The first terminal is insulated from the second terminal. The filling structure 3160 is disposed in each of the plurality of cylinders.

The number and position of the cylinders can be applied as needed, and can be different from those described in Figures 6 and 7. For the sake of brevity, only one of the plurality of stacks is shown in FIG.

In this example, the conductive strips connected to successive layers in one or more of the first terminals include conductive strips from the lowest level to the highest level, with no insertions connected to the second terminal therebetween Conductive strips. In other examples, the conductive strips connected to the first terminal may include conductive strips of intermediate levels, such as from conductive strips 1103 to conductive strips 1106, with no intervening conductive strips connected thereto to the second terminal. In still other examples, the conductive strips connected to the first terminal may comprise conductive strips of any level in the same stack, rather than conductive strips of successive layers.

Fig. 7A is an enlarged view showing the capacitance of the 3D of Fig. 7. In this example, the section of the cylinder has a circle with a radius R. The conductive strips 1105, 1106 are electrically and passively connected together to the first terminal of the 3D capacitor and function as a first plate of the 3D capacitor. The conductive strips connected to the first terminal are not disposed between the conductive strips 1105, 1106. The vertical conductive film 80 is electrically and passively connected to the second terminal of the 3D capacitor and functions as a second plate of the 3D capacitor. The first insulator acts as a dielectric of the 3D capacitor. Therefore, the capacitor C1 is formed between the bus bar 1106 and the vertical conductive film 80. Similarly, a capacitor C2 is formed between the bus bar 1105 and the conductive film 80. Assuming that the total thickness of the conductive strip is H μm, the radius of the cylinder is R μm, and the number of cylinders is N, then the total capacitance can be roughly estimated by C = ε ₀ × ε × (H × 2πR) × N, where ε ₀ The dielectric constant in vacuum and the dielectric constant of ε-based first insulator (ONO). In other examples, the cylinders can have other shapes, such as square and elliptical, and the cylinders can have other configurations.

Figure 8 is a simplified schematic diagram of the charge pump using the 3D capacitor. In this example, the four-stage charge pump contains 3D capacitors 3DCAP1, 3DCAP2, 3DCAP3, and 3DCAP4. In other examples, the charge pump uses a 3D capacitor and places it at the output to provide a boosted voltage. As described, the first terminal of the 3D capacitor is coupled to the first node of the charge pump and the second terminal of the 3D capacitor is coupled to the second node of the charge pump. A. 3D memory block

Figures 9 through 17 illustrate examples of manufacturing processes for 3D memory blocks.

Figure 9 illustrates the process of etching a plurality of layers and stopping at the insulating layer 1101 to define the steps after stacking. To form the structure shown in Fig. 9, a plurality of conductive layers interleaved with the insulating layer are deposited over the insulating layer 1101 on a substrate (not shown). After forming the plurality of layers, pattern etching is performed to form a plurality of stacks 1110 of conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 interleaved with insulating strips 1121, 1122, 1123, 1124, 1125, and 1108. , 1111, 1112 and 1113.

The conductive layer may be formed using the same conductive material of an n-type or p-type heavily doped polysilicon or epitaxial single crystal germanium. In this example, a topmost layer of tantalum nitride that can be used to provide tensile stress is deposited over the plurality of layers. When they are etched into high aspect ratio and narrow lines, this layer improves the uniformity of the stack and slows the bend. The layer of insulating material may comprise cerium oxide deposited by various conventional methods. The layer of insulating material may also include other insulating materials, as well as combinations of insulating materials. In this example, except for the top layer, all of the insulating layers are made of the same material, such as yttrium oxide. In other examples, different layers may be used for different layers to meet specific design goals.

In still other examples, the conductive strip 1102 that acts on the auxiliary gate can use a region doped in the substrate beneath the active pillar or use other techniques.

Stacking a conductive strip comprising at least a bottom level of the auxiliary gate (AG), a plurality of intermediate strips acting as a word line (WL), and a top layer of conductive strips acting as gates of the SSL/GLS transistor . The plurality of intermediate levels of the stack may include N levels ranging from 0 to N-1.

Figure 10 illustrates the steps after forming the first insulator 69 over and over the top and side walls of the plurality of stacks such that the first insulator 69 contacts the sidewalls of the plurality of conductive strips in the stack. The first insulator 69 of the data storage structure of the functional memory block includes a tunneling layer 1132, a charge trapping layer 1131, and a barrier layer 1130.

The tunneling layer 1132 can comprise, for example, yttrium oxide formed using LPCVD, having a thickness of about 20 Å to 60 Å, such as 40 Å. Other tunneling materials and structures can be used, such as a composite tunneling structure. The composite tunneling structure includes a cerium oxide layer having a thickness of less than 2 nm, a cerium nitride layer having a thickness of less than 3 nm, and a cerium oxide layer having a thickness of less than 4 nm. In one embodiment, the composite tunneling structure is composed of an ultra-thin yttrium oxide layer O ₁ (for example, ≤ 15 Å), an ultra-thin tantalum nitride layer N ₁ (for example, ≤ 30 Å), and an ultra-thin yttrium oxide layer O ₂ (for example, ≤ 35 Å). It causes an increase in the valence band energy level of about 2.6 eV at an offset of 15 Å or less from the interface with the semiconductor body. The O2 region has a lower valence band (higher tunneling barrier) and a higher conduction band energy level, which can be N at a second offset from the interface (eg, about 30 Å to 45 Å). _{The 1} layer is isolated from the charge trapping layer. After the second position to the level of effective tunneling tunneling barrier. Since the second position is at a large distance from the interface, the electric field sufficient to cause the tunnel to tunnel increases the energy level of the valence band. Therefore, the special tunneling dielectric still has the ability to prevent leakage when operating at low electric field, because the O ₂ layer does not affect the electric field-assisted hole tunneling. These layers can be conformally deposited, for example, using low pressure chemical vapor deposition (LPCVD).

The charge trap layer 1131 may include tantalum nitride formed, for example, using LPCVD, having a thickness of about 40 Å to 90 Å, for example, about 70 Å. Other charge trapping materials and structures can be used, including, for example, oxynitride strontium (Si _x O _y N _z ), cerium-rich nitrides, cerium-rich oxides, capture layers comprising buried nanoparticles, and the like.

Barrier layer 1130 can comprise cerium oxide formed by wet milling of nitrides by LPCVD or other wet tube oxidation process, having a thickness of from about 50 Å to about 130 Å, such as about 90 Å. Other barrier dielectrics can include high-k materials, such as 150 Å alumina.

The deposition technique used to form the multilayer data storage structure can be implemented in a general LPCVD process. On the other hand, atomic layer deposition (ALD) or other suitable machine can be used for these films. The gate dielectric layer in the area of the SSL and GSL layers can have a different composition than the data storage structure.

The data storage structure is known as oxide-nitride-oxide (ONO), oxide-nitride-oxide-nitride-oxide (ONONO), yttrium-oxide-nitride-telluride-矽 ( SONOS), energy-gap engineering 矽-oxide-nitride-oxide-矽 (BE-SONOS), tantalum nitride-alumina-tantalum nitride-tantalum oxide-tantalum (TANOS) and metal-high-k energy Graft-oxide-nitride-oxide-矽 (MA BE-SONOS).

11 is a view showing a process after the semiconductor film 1140 is formed over the first insulator 69 on the stack and has a surface conformal to the first insulator 69. The semiconductor film 1140 may have a thickness of about 10 nm or less. As illustrated, in a region between the stacks (eg, 1141), the semiconductor film 1140 extends to the bottom of the region (eg, 1141) between the stacks and over the first insulator 69. An oxidized thin layer (not shown) can be formed by short oxidation of the semiconductor film 1140. The semiconductor film 1140 includes a semiconductor employed by the choice of material and doping concentration, such as germanium, doping concentrations such as undoped or lightly doped. In the memory block, the semiconductor film 1140 acts as a channel region of the memory cell at least in a region between adjacent stacks in the plurality of stacks.

Fig. 12 is a view showing a step after the step of performing a region (e.g., 1141 of Fig. 10) between the stacks on the inner side surface of the semiconductor film 1140 filled with an insulating material. When the filling step is performed, a protrusion may be formed on the top of the inner side surface of the semiconductor film 1140. When two adjacent projectiles are in close proximity or joined together, holes or voids 1161 may be formed such that the area between the stacks cannot be completely filled with insulating material. After the filling step, an etch back or planarization step such as chemical mechanical polishing may be performed to expose the top surface of the semiconductor film 1140. In the illustrated example, the fill structure 1160 includes holes (e.g., 1161) in regions adjacent the conductive strips at the intermediate and bottom levels, and includes fill portions in regions adjacent the conductive strips at the top level. The hole 1161 encloses a gas, such as a gas from an atmosphere in the chamber during formation, which may be referred to as "air" in this description.

In other examples, the insulating material may completely fill the area such that the filling structure 1160 between the stacks is filled with a solid insulator, such as tantalum oxide, a low-k dielectric material, or other suitable insulator.

In still other examples, the holes may extend to the top of the area between the stacks.

A fill structure 1160 comprising holes or solid insulators can reduce capacitive coupling between opposite sidewalls of the semiconductor film 1140 in the active pillar.

Figure 13 illustrates the steps of the process after performing the pillar reduction etching. The pillar reduction etching includes etching openings between the stacks in the plurality of stacks to form a plurality of insulating structures 2000, 2001, 2002, 2003, 2004 and 2005. In this example, the opening is extended to expose the insulating layer 1101. The result of the cylinder cut etch is to form a vertical channel structure that is placed between an even stack (eg, 2011-E) and an odd stack (eg, 2011-O). In this example, the insulation structure 2002 is disposed between the stack 2011-E and the stack 2011-O. The vertical channel structure includes even and odd vertical semiconductor films having outer and inner surfaces. The outer surface is disposed on the data storage structure and contacts the data storage structure, the data storage structure being on the side walls of the even and odd stacks of the 3D array forming the memory cells. The inner surface is interleaved with an insulating structure (e.g., 2000, 2001, 2002, 2003, 2004, and 2005). In this example, the insulating structure includes an insulating material and a hole. The vertical semiconductor film of the vertical channel structure may have a thickness of 10 nm or less.

As depicted in Fig. 12, the vertical channel structures are arranged in a honeycomb configuration such that the rows of vertical channel structures are offset from adjacent columns in the column direction. This honeycomb configuration facilitates forming the upper bit lines at a tighter pitch. Insulating fillers (not shown) are supplied into the openings between the vertical channel structures.

After the pillars are etched, the semiconductor film 1140 is continuously over the top of the stack and connected to the vertical semiconductor film for use as a vertical channel structure for the pillars. In Fig. 13, a portion 1140-O of the semiconductor film 1140 is over the odd stack 2011-O and is continuously along the top of the stack 2011-O. The portion 1140-O of the semiconductor film 1140 is connected to the vertical channel structure on the left side of the insulating structure 2002, the vertical channel structure on the right side of the insulating structure 2000, and the vertical channel structure on the right side of the insulating structure 2001. Portions 1140-E of semiconductor film 1140 are over even stack 2011-E and are continuous along the top of stack 2011-E. In this example, portion 1140-E of semiconductor film 1140 is connected to the vertical channel structure on the right side of insulating structure 2002, the vertical channel structure on the left side of insulating structure 2003, and the vertical channel structure on the left side of insulating structure 2004.

Figure 14 illustrates the steps after the patterning etch is performed to separate the remaining semiconductor film 1140 on top of the stack into a plurality of portions for the purpose of forming an array connection. After the patterned etch, the semiconductor film 1140 is divided into portions 2070 and 2071 over the even stack, and portions 2073, 2074, 2075, 2077, 2078, and 2079 over the odd stack. Portions 2070 and 2071 connect the pillars on the common source side of the NAND string together and provide a landing region of the inner layer connector to connect to the common source line. Portions 2073, 2074, 2075, 2077, 2078, and 2079 are separated and provide a landing zone that forms an interconnected inner layer connector to the bit line.

Figure 15 illustrates the formation of an array of inner layer connectors 2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027 through the inner layer of dielectric (not shown) and landing at corresponding portions 2073, 2074, 2075, Structure after 2077, 2078 and 2079. The process can include forming a layer of an inner dielectric, such as yttrium oxide on top of the array, having a thickness of, for example, about 100 nm to 500 nm, then forming a via through the inner dielectric and exposing portions 2073, 2074, 2075 Landing areas of 2077, 2078 and 2079. A conductive material compatible with the semiconductor film is deposited to fill the via holes, thereby forming an inner layer connector. The inner layer connector may comprise a polysilicon plug. The inner layer connectors 2020 and 2024 are electrically connected to portions 2070 and 2071 which are continuous with the vertical channel structure on the GSL side of the cylinder. The inner layer connectors 2021, 2022, 2023, 2025, 2026, and 2027 are respectively electrically connected to the portions 2073, 2074, 2075, 2077, 2078, and 2079, and the portions 2073, 2074, 2075, 2077, 2078, and 2079 are cylindrical. The part on the SSL side.

Figure 16 illustrates the structure after forming a first patterned conductor layer comprising reference lines (e.g., 2030, 2034) and inter-layer connectors (e.g., 2031, 2032, 2033, 2035, 2036, and 2037). Reference line 2034 electrically contacts inner layer connector 2024 with other inner layer connectors (not shown) disposed over the same stack and is connected to the vertical channel structure on the GSL side of the NAND string. As such, the reference line 2034 acts as a local shared source line and provides a connection to the overall common source line.

The reference line may be a section of the reference line, and the section of the reference line and the inter-layer connector may be formed of a previously deposited metal layer during fabrication.

In this example, the inter-layer connectors 2035, 2036, and 2037 are aligned above the inner layer connectors 2025, 2026, and 2027, respectively, and are in electrical contact with the inner layer connectors 2025, 2026, and 2027. The inter-level connection system is connected to the vertical channel film on the SSL side of the NAND string and provides independent connections to the bit lines.

The reference and inter-layer connectors may comprise tungsten or other electrically conductive material such as copper, cobalt telluride, tungsten antimonide, other metallic materials, or combinations thereof, and formed in the same hierarchy.

Figure 17 illustrates the structure after the second patterned conductor layer is provided over the first patterned conductor layer. The second patterned conductor layer includes a plurality of bit lines (eg, 2060, 2061, and 2062), and the bit lines have at least an extension. The extension is formed in the forming step of the bit line and extends downward. The bit line can be a segment of a bit line. For example, bit line 2060 includes extensions 2041 and 2045; bit line 2061 includes extensions 2043 and 2047; and bit line 2062 includes extensions 2042 and 2046. The extension can include a fin. The second patterned conductor layer is formed in a dual damascene process. As shown in FIG. 17, the portion 2070 of the semiconductor film including the vertical semiconductor film on the GSL side of the NAND string in the column is connected to the first layer by an inner layer connector (for example, 2020 in FIG. 15). A reference line 2030 in the patterned conductor hierarchy. Similarly, a portion 2071 of a semiconductor film including a vertical semiconductor film on the GSL side of the NAND string in the pillar is connected to the first patterned conductor layer by an inner layer connector (for example, 2024 of FIG. 15). Reference line 2034. Reference lines 2030 and 2034 connect a plurality of inner layer connectors along respective columns and are operable as a common source line. Portions 2073 and 2077 of the semiconductor film including the vertical semiconductor film structure on the SSL side of the NAND string in the column are connected to the extensions 2041, 2045 of the bit line 2060 by the inter-layer connectors. The portions 2075 and 2079 of the semiconductor film including the vertical semiconductor film on the SSL side of the NAND string in the column are connected to the extensions 2043, 2047 of the bit line 2061 by the inter-layer connectors. The portions 2074 and 2078 of the semiconductor film including the vertical semiconductor film structure on the SSL side of the NAND string in the column are connected to the extensions 2042, 2046 of the bit line 2062 by the inter-layer connectors. In this example, the memory block is a three-dimensional vertical channel (3GVC) structure, as described in U.S. Patent Application Serial No. 14/861,377, the disclosure of which is incorporated herein in This is fully incorporated herein by reference.

In other examples, the memory block can be applied with a three-dimensional vertical gate (3DVG) structure, as described in U.S. Patent No. 8,208,279 B2, entitled INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD, inventor HT Lue This is fully incorporated herein by reference. In a 3DVG memory array, the conductive strips in the plurality of stacks comprise bit lines, and the vertical conductive film comprises word lines.

Figure 17 depicts a circuit path 2069 for the current of the U-type NAND string, which is connected between reference line 2034 and bit line 2060. The structure shows a plurality of cylinders between the stacks of conductive strips. The pillars each include a vertical semiconductor film having an outer side surface and an inner side surface. The outer side surface is disposed on the tunneling layer 1132 of the first insulator 69 on the adjacent stacked sidewalls in the plurality of stacks. The memory cell lines are connected in series to form a current path from the higher end to the lower end of the vertical semiconductor film on the GSL side, and from the lower end to the higher end of the vertical semiconductor film on the SSL side. B. 3D capacitor of the first embodiment

Most of the process steps of the 3D memory block can be applied to the fabrication of the 3D capacitor of the first embodiment such that a number of deposition and etching steps can be shared and implemented in the memory block and the capacitor region. Therefore, in order to avoid redundancy, only the differences will be explained. The 3D capacitor example of the first embodiment can be formed using the processes described above with reference to FIGS. 9 to 12, followed by the process described below with reference to FIGS. 18 to 21.

Figure 18 illustrates the steps after the trench etch of the structure of Figure 12 to remove the fill structure between the plurality of stacks (e.g., 1160 of Figure 12) and remove the vertical semiconductor film in the process. As illustrated, the trench etch stops at the tunneling layer 1132 to form trenches 3000, 3001 and 3002 between the stacks. In this example, the first insulator 69 on the sidewalls of the plurality of stacks is not etched away, and the remaining semiconductor film 1140 is only on top of the plurality of stacks. In other examples, the trench etch removes the vertical semiconductor film on the sidewalls of the stack from the vertical first insulator leaving its portion on top of the stack.

Figure 19 is a diagram showing the structure after the step of filling the trenches on the inner side surface of the tunneling layer 1132 between the stacks (e.g., 3000, 3001, and 3002 of Fig. 18) with an insulating material in the process. When the filling step is performed, a protrusion may be formed on the top of the inner side surface of the second ruthenium oxide layer 1132. When two adjacent projectiles are in close proximity or joined together, holes or voids 3011 may be formed such that the trenches between the stacks are not completely filled with insulating material. After the filling step, an etch back or planarization step such as chemical mechanical polishing may be performed to expose the top surface of the semiconductor film 1140. In the illustrated example, the second insulator 3010 includes a hole 3011 adjacent the conductive strip at the intermediate and bottom levels and includes a filled portion adjacent the conductive strip at the top level. The holes 3011 enclose a gas, such as a gas from an atmosphere in the chamber during formation, which may be referred to as "air" in this description.

In other examples, the insulating material can completely fill the trench such that the second insulator 3010 is filled with a solid insulator, such as hafnium oxide, a low-k dielectric material, or other suitable insulator.

In still other examples, the holes may extend to the top of the area between the stacks.

Figure 20 is a top view showing the structure of Figure 19. In this example, the odd stacks 3111, 3113, 3115, and 3117 extend from the landing pad region 3013 on the left side, and the even stacks 3112, 3114, and 3116 extend from the landing pad region 3012 on the right side. Semiconductor film 1140 is on top of a plurality of stacks and is not on landing pad regions 3012 and 3013. The odd stacks 3111, 3113, 3115, and 3117 refer to the fork even stacks 3112, 3114, and 3116, and are separated from the even stacks 3112, 3114, and 3116 by a second insulator 3010. As described above, the first terminal is connected to the continuous level of conductive strips in the stack in the first set of spaced stacks, the stack in the first set of spaced stacks is, for example, even stacks 3112, 3114 and 3116, and the second terminal is connected to the second set The strips of successive levels in the stack in the stack are stacked, and the stacks in the second set of spaced stacks are, for example, odd stacks 3111, 3113, 3115, and 3117. In this example, the conductive strips in the even stack act as the first plate of the 3D capacitor, the conductive strips in the odd stack act as the second plate of the 3D capacitor, and the first insulator and the second insulator act together as a 3D capacitor. Dielectric.

The landing pad area 3012 on the right includes a contact area 3014 on the right side, and the contact area 3014 includes a plurality of contact plugs connected to corresponding conductive strips. Similarly, the landing pad area 3013 on the left includes a contact area 3015 on the left side, and the contact area 3015 includes a plurality of contact connections to corresponding conductive strips.

Figure 21 is a simplified cross-sectional view of the contact area 3014 on the right side of Figure 20 along the line AA'. In this example, contact plugs 3020, 3021, 3022, 3023, 3024, and 3025 land on strips 1102, 1103, 1104, 1105, 1106, and 1107, respectively, to configure a stepped configuration. The intermediate connector 3026 can be disposed in the first patterned conductor layer and contacts each of the plurality of contact plugs 3020, 3021, 3022, 3023, 3024, and 3025 such that the stack extends from the right landing pad region (ie, even stack) The conductive strips are electrically and passively connected together to an intermediate connector 3026 disposed in the first patterned conductor layer. The intermediate connector 3026 is connected to the first terminal of the 3D capacitor, that is, to the first node of the charge pump (shown in FIG. 8). Thus, the conductive strips in the even stack (eg, 3012, 3014, and 3016 of FIG. 20) are electrically and passively connected to the contact plugs 3020, 3021, 3022, 3023, 3024, and 3025 through the intermediate connector 3026. The first terminal of the 3D capacitor.

Similarly, the contact area on the left side (3015 of Fig. 20) includes a plurality of contact plugs respectively landing on corresponding conductive strips disposed in the stepped structure as shown in Fig. 21. A second intermediate connector (not shown) contacts each of the plurality of contact plugs such that the conductive strips in the stack (ie, odd stacks) extending from the landing pad region on the left are electrically and passively connected together to the second intermediate Connector. The second intermediate connector may be disposed in the second patterned conductor layer such that the first intermediate connector is not in electrical contact with the second intermediate connector. The second intermediate connection system is connected to the second terminal of the 3D capacitor, that is, to the second node of the charge pump (shown in FIG. 8). As such, the conductive strips in the odd stack (eg, 3011, 3013, 3015, and 3017 of FIG. 20) are electrically and passively coupled to the second terminal of the 3D capacitor through the second intermediate connector and the contact plug. C. The 3D capacitor of the second embodiment

Most of the process steps of the 3D memory array can be applied to the fabrication of the 3D capacitor of the second embodiment such that a number of deposition and etching steps can be shared and implemented in the memory and capacitance regions. Therefore, in order to avoid redundancy, only the differences will be explained. The 3D capacitor example of the second embodiment can be formed using the processes described above with reference to FIGS. 9 to 10, followed by the process described below with reference to FIGS. 22 to 25.

Figure 22 illustrates the structure of the process after forming a conductive film having a surface conformal to a first insulator on a plurality of stacks, thereby forming a plurality of pillars. The conductive film 1140C may be a doped semiconductor or a conductor to have a low resistance. In the example of a semiconductor in which the conductive film 1140C is doped, it can be formed with the semiconductor film 1140 in the memory block described with reference to FIG. 12, and then impurities are added to the semiconductor to improve conductivity. In other examples, the doped semiconductor can be formed in situ with impurities. In still other examples, the semiconductor film 1140 is further subjected to a metal deuteration process to form a vaporized layer such as tungsten telluride, cobalt telluride, and titanium telluride, which can reduce electrical resistance. In other examples, the conductive film 1140C can be a metal such as tungsten, copper, titanium, other metallic materials, or a combination thereof. The conductive film 1140C has a plurality of vertical conductive films between the stacks acting as one plate of the 3D capacitor. Therefore, when the resistance of the plate of the capacitor is lower, the capacitance value of the capacitor is larger.

Fig. 23 is a view showing the structure of the process after the step of filling the region between the stacks with an insulating material (e.g., 1141 of Fig. 22). The filling step applied in the memory block as described with reference to Fig. 12 is also applied to the capacitor. A fill structure 3060 is thus formed which is similar to the fill structure 1060 of FIG.

Fig. 24 is a view showing the structure after the step of forming the inner layer connecting body (e.g., 3030, 3031) and the inter-layer connecting body (e.g., 3032, 3033) on the conductive film 1140C on the top of the stack. In this example, the step of forming the inner layer connection body (for example, 3030, 3031) on the conductive film 1140C can be performed in the step described with reference to FIG. 15, and an inter-layer connection body is formed on the inner layer connection body (for example, 3032). The steps of 3033) can be performed in the steps described with reference to FIG. As shown, the inter-layer connectors (eg, 3032, 3033) are electrically and passively connected together in the second patterned conductor layer, whereby the second terminal of the 3D capacitor is connected to be disposed between adjacent stacks. A vertical conductive film in a plurality of cylinders. The first terminal of the 3D capacitor is connected to the conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 in the respective stacks by referring to the intermediate connector and the step contact structure described in FIG.

Fig. 25 is a top view showing the structure of Fig. 24. In this example, the odd stacks 3111, 3113, 3115, and 3117 extend from the landing pad region 3013 on the left side, and the even stacks 3112, 3114, and 3116 extend from the landing pad region 3012 on the right side. Conductive film 1140C is above stacks 3111, 3112, 3113, 3114, 3115, 3116, and 3117, but not above landing pad regions 3012 and 3013. A fill structure 3060 is disposed between the vertical conductive films on opposite sides of the stack. The stacks have a forked configuration. The conductive strips in the even stack are electrically and passively connected to the first terminal of the 3D capacitor, that is, to the first node of the charge pump, or other circuitry, through the contact region 3014 on the right side. Furthermore, the conductive strips in the odd stack are electrically and passively connected to the first terminal through the contact area 3015. Thus, the conductive strips in a plurality of stacked (ie, odd and even stacks) act as the first plate of the 3D capacitor. In this example, the contact plugs in contact regions 3014 and 3015 are connected in the first patterned conductor layer. In another aspect, the vertical conductive film in the plurality of pillars is electrically and passively connected to the second terminal of the 3D capacitor through a plurality of connectors, that is, to the second node of the charge pump, or other circuit, Thereby, the vertical conductive film acts as a second plate of the 3D capacitor. In this example, a plurality of inter-layer connection systems are connected in the second patterned conductor layer.

Fig. 26 is a view showing a variation of the 3D capacitance of the second embodiment. In this example, the area between the stacks (e.g., 1141 of Figure 22) is filled with a conductive film 1140C such that the entire top surface of the illustrated structure is electrically conductive. Therefore, it provides more space to include intermediate and inter-level connectors, and eliminates the problem of misalignment when the connectors are disposed on the filling structure 3060 between the stacks. D. 3D capacitor of the third embodiment

27 to 31 are diagrams showing an example of a manufacturing flow of the 3D capacitor of the third embodiment.

Figure 27 illustrates a plurality of openings formed through the stack of conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 interleaved with the insulating strips 1121, 1122, 1123, 1124, 1125, and 1108, wherein the opening is configured The structure after the step of twisted or honeycomb pattern. To form the structure shown in Fig. 28, a plurality of staggered conductive layers and insulating layers are deposited over the insulating layer 1101 on a substrate (not shown). After forming the plurality of layers, a patterning etch is performed that stops at the insulating layer 1101 to form a plurality of openings through the conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 in the one or more stacks (eg, 3101, 3102 and 3103). For the sake of brevity, only one stack is shown in Figure 27. The step of forming the plurality of openings can be performed by the step of forming a plurality of stacks in the memory block.

In the process of Fig. 28, a structure is formed in which the first insulator 69 and the conductive film 1140C cover a plurality of openings to form a plurality of pillars contacting the sidewalls of the bus bar. The first insulator 69 and the conductive film 1140C do not completely fill the opening, leaving areas in the opening (eg, 3104, 3105, and 3106). The first insulator 69 can be formed by the steps described with reference to FIG. 10, and the conductive film 1140C can be formed by referring to the steps described in FIG.

Fig. 29 is a view showing the structure after the formation step of the region filled with the insulating material (e.g., 3104, 3105, and 3106 in Fig. 28) in the process. The filling step performed in the memory block as described with reference to Fig. 11 is also applied to the capacitance described herein. As such, a fill structure 3160 is formed that is similar to fill structure 1060 of FIG.

Figure 30 is a diagram showing the structure after forming the inner layer connecting body (e.g., 3030, 3031) and the inter-layer connecting body (e.g., 3032, 3033) on the conductive film 1140C above the top of the stack in the process. In this example, the inner layer connectors (e.g., 3030, 3031) can be formed in the steps described with reference to Fig. 15, and the inter-layer connectors 3032, 3033 can be formed in the steps described with reference to Fig. 16. As shown, the inter-layer connectors (eg, 3032, 3033) are electrically and passively connected together in a second patterned conductor layer through which the second terminal of the 3D capacitor is connected to a plurality of layers disposed in the stack. A vertical conductive film in a cylinder. The first terminal of the 3D capacitor is connected to the conductive strips 1102, 1103, 1104, 1105, 1106, and 1107 in the stack by referring to the intermediate connector and the step contact structure described in FIG.

Figure 31 is a top view showing the structure of Figure 30. In this example, the stack includes a landing pad area 3012 on the right side and a landing pad area 3013 on the left side. In other examples, the landing pad area 3012 on the right side can be selectively eliminated so that more posts can be formed to increase capacitance. The conductive film 1140C is over a plurality of openings in the stack and can selectively cover the regions 3016 of the land pad region 3013 such that more connections to the second terminal can be formed. The plurality of cylinders and the filling structure (eg, 3160) in the cylinder have a staggered or honeycombed configuration in the stack. The conductive strips in the stack are electrically and passively connected to the first terminal of the 3D capacitor through the contact region 3014 on the right side of the landing pad region 3012 on the right side and the contact region 3015 on the left side in the landing pad region 3013 on the left side, that is, Connect to the first node or other circuit of the charge pump. As such, the conductive strip acts as the first plate of the 3D capacitor. In this example, the contact plugs in contact regions 3014 and 3015 are connected in the first patterned conductor layer. In another aspect, the vertical conductive film in the plurality of pillars is electrically and passively connected to the second terminal of the 3D capacitor through the plurality of connectors, that is, the second node or other circuit connected to the charge pump. This vertical conductive film acts as a second plate of the 3D capacitor. In this example, a plurality of inter-layer connection systems are connected in the second patterned conductor layer.

Fig. 32 is a diagram showing a variation of one of the 3D capacitors of the third embodiment. In this example, the area in the opening in the stack (e.g., 3104, 3105, and 3106 of Figure 28) is filled with a conductive film 1140C such that the entire top surface of the depicted structure is electrically conductive. Therefore, this variation provides more space to include intermediate and inter-level connectors, and eliminates misalignment problems when the connectors are placed on the filling structure 3160 in the cylinder.

Figure 33 is a simplified wafer block diagram of an integrated circuit 901 including a 3D NAND flash memory. The integrated circuit 901 includes a memory array 960 that includes one or more of the 3D memory blocks described herein on the integrated circuit substrate.

The SSL/GSL decoder 940 is coupled to a plurality of SSL/GSL lines 945 disposed in the memory array 960. The even/odd level decoder 950 is coupled to a plurality of even/odd digital lines 955. The overall bit line row decoder 970 is coupled to a plurality of overall bit lines 965 arranged along the column in the memory array 960 to read data from the memory array 960 and write data to the memory array 960. . The overall bit line is set to bit lines 2060-2062 having extensions 2041-2043, 2045-2046 as shown in FIG. The address is supplied from the control logic 910 to the decoder 970, the decoder 940, and the decoder 950 at the bus 930. In this example, the sense amplifier and the stylized buffer circuit 980 are coupled to the row decoder 970 via the first data line 975. The stylized buffer in circuit 980 can store code for multi-level programming, or a value for the power of the code to indicate the stylized or disabled state of the selected bit line. Row decoder 970 can include circuitry for selectively supplying stylized and inhibited voltages to bit lines in the memory in response to data values in the stylized buffer.

The sensed data from the sense amplifier/stylized buffer circuit 980 is supplied to the multi-level data buffer 990 through the second data line 985 and then coupled to the input/output circuit 991 via the data path 993. In addition, in this example, the input data is provided to a multi-level data buffer 990 for supporting multi-level programming operations on separate sides of separate dual gate cells in the array.

The input/output circuit 991 drives the data to the destination outside the integrated circuit 901. The input/output data and the control signal are removed through the data bus 905 between the input/output circuit 991, the input/output port on the control logic 910 and the integrated circuit 901, or other internal or external to the integrated circuit 901. Data sources, such as general purpose programs or special purpose application circuits, or combinations of modules that provide 3D memory blocks and on-wafer system functions supported by 3D capacitor block 960.

In the example shown in FIG. 33, control logic 910 enables the charge pump and uses the charge pump to generate positive and negative voltages for reading, erasing, and stylizing operations, and the control application passes through block 920. Voltage supplies generated or provided in, such as read, erase, verify, and program bias. The control logic 910 is coupled to the multi-level data buffer 990 and the 3D memory block and the 3D capacitor block 960. Control logic 910 includes logic to control multi-level stylized operations. In an embodiment supporting a U-shaped vertical NAND structure as described herein, the logic installed is used to perform the method: for example, using a word line layer decoder to select a layer of memory cells in the array; for example by selecting an even or odd side a word line structure to select one side of the vertical channel structure in the selected layer; for example, by using an SSL switch and a GSL switch on the vertical channel structure column to select a vertical channel structure in a selected column in the array And using a bit line circuit coupled to the overall bit line of the page buffer of the vertical channel structure of the selected column to store charge on the selected side of the vertical channel structure in one or more selected rows in the array The charge trapping side of the selection layer is used to represent the data.

In some embodiments, the logic is installed, for example by controlling the even and odd digital line layer decoders, to select one of the even and odd digital line structures of the fingers in the selected layer of the array to select layers and select side.

In some embodiments, the logic is installed to store multiple levels of charge to represent more than one bit of data in the charge trapping layer in the selected layer on the selection side. In this way, the selected cell line in the selected frustum of the vertical channel structure in the array stores more than two bits, including more than one bit on each side cell.

Control logic 910 can use known special purpose logic circuits. In other embodiments, the control logic includes a general purpose program that can be applied to the same integrated circuit that executes a computer program to control the operation of the device. In still other embodiments, the control logic can apply a combination of special purpose logic circuitry to a general purpose program.

The memory cell threshold voltage VT is established by establishing a multi-stylized hierarchy corresponding to the amount of stored charge, and the 3D memory block and the 3D capacitance block 960 can include a charge trapping memory cell configured to store a plurality of bits in each cell. . As mentioned above, embodiments of a single bit per cell can include the structures described herein.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

69‧‧‧First insulator
80, 80a, 80b‧‧‧ conductive film
100‧‧‧ memory device
901‧‧‧Integrated circuit
905‧‧‧Input/output data
910‧‧‧ Controller
920‧‧‧ Bias configuration, 3D charge pump block
930‧‧‧ address
940‧‧‧SSL/GSL column decoder
945‧‧‧SSL/GSL line
950‧‧‧ even/odd level decoder
955‧‧‧ even/odd digital lines
960‧‧‧3D memory block and 3D capacitor block
965‧‧‧ overall bit line
970‧‧‧Overall bit line decoder
975‧‧‧First data line
980‧‧‧Sense Amplifier/Stylized Buffer
985‧‧‧Second data line
990‧‧‧Multi-level data buffer
991‧‧‧Input/Output Circuit
993‧‧‧data path
1101‧‧‧Insulation
1105-E, 1105-O, 1106-E, 1106-O‧‧‧ Conductive strips
1102, 1103, 1104, 1105, 1106, 1107‧‧‧ Conductive strips
1108, 1121, 1122, 1123, 1124, 1125‧‧‧ insulation strips
1110, 1111, 1112, 1113‧‧‧ stacking
1130‧‧‧Block
1131‧‧‧ Charge trapping layer
1132‧‧‧ Tunneling
1140‧‧‧Semiconductor film
1140C‧‧‧Electrical film
1140-O, 1140-E‧‧‧ part of the semiconductor film
1141‧‧‧A region between stacks
1160‧‧‧filled structure
1161‧‧‧ holes
2000, 2001, 2002, 2003, 2004, 2005‧‧‧ ‧ insulation structure
2011-O‧‧‧ odd stacking
2011-E‧‧‧ even stack
2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027‧‧‧ inner layer connectors
2030, 2031, 2034‧‧‧ reference line
2032, 2033, 2035, 2036, 2037‧ ‧ inter-sector connectors
2041, 2042, 2043, 2045, 2046, 2047‧‧‧ extensions
2060, 2061, 2062‧‧‧ bit line
2069‧‧‧Circuit path
2070, 2071, 2073, 2074, 2075, 2077, 2078, 2079‧‧ ‧ part of the semiconductor film
3000, 3001, 3002‧‧‧ trench
3010‧‧‧Second insulator
3011‧‧‧ hole
3012, 3013‧‧‧ Landing pad area
3014‧‧‧Contact area on the right
3015‧‧‧Contact area on the right
3016‧‧‧ even stack
3017‧‧‧ odd stack
3020, 3021, 3022, 3023, 3024, 3025‧‧‧ contact plugs
3026‧‧‧Intermediate connector
3030, 3031‧‧‧ Inner layer connectors
3032, 3033‧‧ ‧ inter-sector connectors
3060‧‧‧filled structure
3121, 3102, 3103‧‧‧ openings
3104, 3105, 3106‧‧‧ areas in the opening
3111, 3113, 3115, 3117‧‧‧ odd stack
3112, 3114, 3116‧‧‧ even stack
3160‧‧‧filled structure
3DCAP1, 3DCAP2, 3DCAP3, 3DCAP4‧‧3D capacitors
AG‧‧‧Auxiliary gate
C1, C2, C3, C4‧‧‧ capacitors
CAP 0, CAP 13D‧‧‧ capacitor
CLK1, CLK2‧‧‧ clock
Cdep‧‧‧ parasitic capacitance
Cox‧‧‧ capacitor
D‧‧‧Distance between the first plate and the second plate
D1, D2, D3, D4‧‧‧ diodes
D _ONO ‧‧‧The distance between the first plate and the second plate
GATE‧‧‧ gate
GSL‧‧‧ Grounding selection line
L‧‧‧ Length of conductive strip
N+‧‧‧N+ doped source/drain
N-WELL‧‧‧N well
P-SUB‧‧‧P type substrate
R‧‧‧ Radius
SSL‧‧‧ tandem selection line
Vin‧‧‧Input voltage
Vout‧‧‧ output voltage
WL‧‧‧ character line

Figure 1 is a simplified schematic diagram of a prior art charge pump. Figure 2 illustrates a prior art MOS capacitor with parasitic capacitance. Figure 3 is a block diagram of a 3D NAND memory device 100 including the 3D memory block and capacitor. Figure 4 is a perspective view of a 3D memory block. 5 to 5A are perspective views of the 3D capacitor according to the first embodiment. 6 to 6A are perspective views of the 3D capacitor according to the second embodiment. 7 to 7A are perspective views of the 3D capacitor according to the third embodiment. Figure 8 is a simplified schematic diagram of the charge pump using the 3D capacitor. Figures 9 through 17 illustrate perspective views of the structure during the manufacturing process of the 3D memory block. Figures 18 through 21 are additional structural perspective views of the 3D capacitor fabrication step in the first embodiment, which is accompanied by a 3D memory block process. Figures 22 through 25 are additional structural perspective views of the 3D capacitor fabrication step in the second embodiment, which is accompanied by a 3D memory block process. Fig. 26 is a diagram showing a variation of the 3D capacitance in the second embodiment. Figures 27 to 31 are additional structural perspective views during the 3D capacitor fabrication step in the third embodiment, which is accompanied by a 3D memory block process. . Fig. 32 is a diagram showing a variation of the 3D capacitance in the third embodiment. Figure 33 is a block diagram of an integrated circuit including the 3D memory block and the 3D capacitor.

Claims (9)

A three-dimensional (3D) capacitor includes: a plurality of stacks of a plurality of conductive strips interleaved with a plurality of insulating strips; a first terminal connected to a plurality of the stacks in a first set of spaced stacks of the stacks a conductive strip; and a second terminal connected to the plurality of conductive strips in the stack of the second set of spaced stacks in the stack. The 3D capacitor of claim 1, wherein the stacks of the first set of spaced stacks are interdigitated in the stacks of the second set of spaced stacks. A 3D capacitor includes: one or more stacks of a plurality of conductive strips interleaved with a plurality of insulating strips; a plurality of pillars respectively including a vertical conductive film and a first insulator; a first terminal connected to the The plurality of conductive strips in the stack; and a second terminal connected to the vertical conductive films in the pillars. The 3D capacitor of claim 3, wherein the pillars have a staggered or honeycomb configuration. A 3D capacitor comprising: a plurality of stacks of a plurality of conductive strips interleaved with a plurality of insulating strips; a first terminal connected to a plurality of conductive strips of a continuous layer of the one or more stacks of the stacks; A second terminal is insulated from the first terminal. A method of manufacturing a 3D capacitor, comprising: forming a plurality of stacks of a plurality of conductive strips interleaved with a plurality of insulating strips; forming a first terminal of the 3D capacitor, the first terminal being connected to one or more of the stacks a plurality of conductive strips of a continuous layer in the stack; and a second terminal forming the 3D capacitor, the second terminal being insulated from the first terminal. The method of manufacturing a 3D capacitor according to claim 6, wherein the forming the second terminal comprises connecting a plurality of conductive strips of successive layers in the plurality of stacks. The method for manufacturing a 3D capacitor according to claim 7, wherein the stacks of the conductive strips connected to the continuous layer of the second terminal are forked to include the continuous layers connected to the first terminal. The one or more stacks of conductive strips. The method of manufacturing a 3D capacitor according to claim 6, wherein the forming the second terminal comprises forming a plurality of cylinders having a staggered or honeycomb configuration.