CN114173470A - Differential wiring arrangement structure - Google Patents
Differential wiring arrangement structure Download PDFInfo
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- CN114173470A CN114173470A CN202111274609.4A CN202111274609A CN114173470A CN 114173470 A CN114173470 A CN 114173470A CN 202111274609 A CN202111274609 A CN 202111274609A CN 114173470 A CN114173470 A CN 114173470A
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- 238000010586 diagram Methods 0.000 description 10
- 238000013461 design Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
Abstract
The invention discloses a differential wiring arrangement structure which comprises a differential wire group formed by at least three differential pairs, wherein each differential pair of each differential wire group is in central symmetry distribution, each differential pair comprises a P-type pin and an N-type pin, wires are respectively led out from the P-type pin and the N-type pin, differential signals are transmitted through the two wires, and backflow ground holes are arranged on the outer side of the differential wire group. The differential routing arrangement structure adopts a central symmetry arrangement form, different differential pairs can share the same backflow ground hole, the backflow ground hole does not need to be independently configured for each differential pair, and the backflow ground holes are shared, so that the arrangement density of the differential routing is improved.
Description
Technical Field
The invention relates to the field of signal transmission, in particular to a differential routing arrangement structure.
Background
The differential signal is a signal with two equal values and opposite phases sent by the driving end, and the receiving end judges the logic state, namely 0 or 1, by comparing the difference value of the two voltages. The pair of traces that carry the differential signals are referred to as differential traces. Compared with a common single-ended signal wire, the most obvious advantages of differential signals are represented by the following three aspects:
the anti-interference capability is strong: because the coupling between two differential wirings is good, when there is noise interference outside, the two wirings are coupled almost at the same time, and the receiving end only concerns the difference value of the two signals, so the outside common mode noise can be completely offset.
Can effectively inhibit EMI (Electromagnetic Interference): because the polarities of the two signals are opposite, the electromagnetic fields radiated by the two signals can be mutually cancelled, and the tighter the coupling is, the less electromagnetic energy is released to the outside.
The time sequence positioning is accurate: because the switching change of the differential signal is positioned at the intersection point of the two signals, and the common single-ended signal is not judged by depending on high and low threshold voltages, the influence of the process and the temperature is small, the error on the time sequence can be reduced, and the circuit is more suitable for circuits with low-amplitude signals.
In recent years, the server and the communication product are continuously pursuing high-density miniaturized design, and the requirements on the density of the chip and the PCB are higher and higher, and simultaneously, the requirements on the design of the signal integrity are higher and higher along with the increasing of the signal rate. The traditional via hole arrangement mode is difficult to consider high density and high electrical performance, fig. 1 is a typical differential line via hole arrangement diagram in the prior art, two via holes surrounded by an oval frame are a pair of PN pins, each pair of PN pins is arranged and distributed along a linear type, each pair of PN pins in two adjacent rows are distributed in a staggered manner, and a transmission line is led out from a staggered space. The arrangement mode has the advantages that independent backflow holes exist around the through holes, the through hole pitch is large, interference among the through holes is small, and the electrical performance is good; the disadvantage is that the occupied space is large, and the design is not friendly to high density.
For those skilled in the art, how to increase the arrangement density of the differential traces is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a differential routing arrangement structure, wherein the arrangement form shares partial backflow ground holes, which is beneficial to improving the density, and the specific scheme is as follows:
a differential routing arrangement structure comprises a differential line group formed by at least three differential pairs, wherein each differential pair of each differential line group is in central symmetry distribution, each differential pair comprises a P-type pin and an N-type pin, and wires are respectively led out from the P-type pin and the N-type pin;
and the outer side of the differential line group is provided with a backflow ground hole, and two adjacent differentials share the same backflow ground hole.
Optionally, the symmetry center of the set of differential lines is provided with a return ground via shared by the respective differential pairs in the set.
Optionally, the differential line group is composed of six differential pairs.
Optionally, the outer pin of one of the differential pairs is arranged on a connecting line of the inner pins of two adjacent differential pairs.
Optionally, the pitch of the inner pin and the outer pin in one differential pair is equal to the pitch of the inner pins of two adjacent differential pairs.
Optionally, the lateral spacing between adjacent vias is 30-50 mils.
Optionally, there is a common differential pair between two adjacent differential line groups.
Optionally, the leads led out from the same differential pair are led out side by side to avoid via holes formed in the PCB.
The core of the invention is to provide a differential routing arrangement structure, which comprises a differential wire group formed by at least three differential pairs, wherein each differential pair of each differential wire group is centrosymmetrically distributed, each differential pair comprises a P-type pin and an N-type pin, wires are respectively led out from the P-type pin and the N-type pin, differential signals are transmitted through the two wires, and the outer side of the differential wire group is provided with a backflow ground hole. The differential routing arrangement structure adopts a central symmetry arrangement form, different differential pairs can share the same backflow ground hole, the backflow ground hole does not need to be independently configured for each differential pair, and the backflow ground holes are shared, so that the arrangement density of the differential routing is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a typical prior art differential line via layout diagram;
fig. 2 is a schematic view of a specific arrangement of the differential routing arrangement of the present invention;
FIG. 3 is a schematic diagram of an arrangement in which two differential line sets are mated with each other;
fig. 4 is a schematic layout structure diagram of a third embodiment of a differential routing arrangement according to the present invention;
fig. 5 is a schematic diagram of the wire arrangement shown in fig. 2.
Detailed Description
The core of the invention is to provide a differential routing arrangement structure, and the arrangement form shares part of backflow ground holes, thereby being beneficial to improving the density.
In order to make those skilled in the art better understand the technical solution of the present invention, the differential routing structure of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention provides a differential wiring arrangement structure which comprises a differential wiring group formed by at least three differential pairs, wherein each differential pair of each differential wiring group is in central symmetry distribution, each differential pair comprises a P-type pin and an N-type pin, the P-type pin and the N-type pin are respectively positioned at through holes formed in a PCB, wires are respectively led out from the P-type pin and the N-type pin, and the two wires form a differential wiring for transmitting a group of differential signals.
The outer side of the differential line group is provided with a backflow ground hole, the outer side is the side far away from the symmetry axis, the side close to the symmetry axis is used as the inner side, a plurality of through holes are preset on the PCB, the P-type pin and the N-type pin of one differential pair occupy two of the through holes, and the adjacent through holes on the outer side of the differential pair are used as the backflow ground hole.
Because each differential pair of the differential routing arrangement structure adopts a central symmetry arrangement mode, two adjacent differential pairs can share part of the same backflow ground holes, so that the backflow ground holes do not need to be configured for each differential pair independently, and two or more differential pairs can share the same backflow ground holes, the wiring density is improved, and the overall volume is reduced.
On the basis of the above scheme, as shown in fig. 2, a schematic diagram of a specific arrangement manner of the differential routing layout structure of the present invention is shown; two solid circles respectively surrounded by six ellipses with the number of 1-6 are a P-type pin and an N-type pin of a differential pair, the solid circles not surrounded by the ellipses are backflow ground holes, and the hollow circles can be defined as low-speed signal holes, ground backflow holes or other types of holes according to actual design.
In the invention, the backflow ground hole shared by each differential pair in the group is arranged at the symmetric center of the differential line group, the backflow ground hole is positioned at the symmetric center of the differential line group, namely the backflow ground hole is positioned at the inner side of each differential pair in the differential line group, and the backflow ground hole is respectively arranged at the inner side and the outer side of each differential pair.
Preferably, the differential line set provided by the invention is composed of six differential pairs, and six pins close to the symmetry axis in each differential pair are respectively positioned at six vertex angles of a regular hexagon. Gnd0 in fig. 2 indicates a return ground hole located at the inner center of symmetry, and the arrow indicates sharing by six pins adjacent to it; gnd1 indicates a return ground hole located at an outer position and the arrow indicates common use by three pins adjacent to it.
The outer pin of one differential pair is arranged on the connecting line of the inner pins of two adjacent differential pairs; it should be noted that, for two pins of the same differential pair, one pin close to the symmetry center is an inner pin, and the other pin relatively far from the symmetry center is an outer pin; as shown by the dotted line on the lower right side of fig. 2, two pins of the differential pair indicated by the ellipse 3 are connected, and the inner pin of the differential pair indicated by the ellipse 2 adjacent to the two pins is distributed on the extension line of the connection line.
The pitch of the inner pin and the outer pin in one differential pair is equal to the pitch of the inner pins of two adjacent differential pairs, and as shown by the dotted line on the lower right side of fig. 2, when the pitch d1 of two pins in ellipse 3 is equal to the pitch d2 between the inner pin of ellipse 3 and the inner pin of ellipse 2, three of the vias on the PCB board are located at the three vertices of an equilateral triangle. With this arrangement, the included angle between two adjacent differential pairs is 60 degrees, i.e., the included angle α shown in fig. 2 is 60 degrees.
Since the inner hole is positioned right in the middle of the adjacent differential via holes, the position is a position for magnetic lines of force of the two via holes of the differential pair to offset, and the influence from the adjacent differential pair can be reduced to the maximum extent. Referring to fig. 2, the inner pin corresponding to ellipse 3 is located on the centerline of the outer pin and the inner pin of ellipse 2, and the magnetic properties of the P-type pin and the N-type pin are opposite to each other to achieve cancellation.
The lateral spacing between adjacent vias is 30-50 mils, i.e., the distance between d1 and d2 in FIG. 2 is 30-50 mils.
On the basis of any one of the above technical solutions and their combination, two adjacent differential line groups of the present invention have a common differential pair, and as shown in fig. 3, the present invention is a schematic diagram of an arrangement manner in which two differential line groups are matched with each other, where two differential line groups have a common differential pair, that is, a differential pair at a vertical intersection of two double-headed arrows in the diagram, and by adopting such an arrangement form, the overall arrangement density can be further improved.
It should be noted that, for the four pins indicated by the bidirectional arrows in fig. 3, since only one reflow ground hole is located in the center, and the other vias have two reflow ground holes for reflow, the signal quality of the network where the four vias are located needs to be focused during the test.
Fig. 4 is a schematic view of an arrangement structure of a third embodiment of a differential routing arrangement structure according to the present invention; the embodiment is equivalent to that on the basis of the layout shown in fig. 3, the differential pairs surrounded by the dashed oval frames are added, the differential pairs are equivalent to the differential line groups adjacent to the two complete differential line groups in the diagram, but due to insufficient space, the differential line group where the dashed oval frame is located is incomplete, and is still the adjacent differential line group sharing the differential pair, so that the space utilization rate can be further improved, and the wiring density can be improved.
Shown in conjunction with fig. 5, is a schematic diagram of the wire arrangement of the arrangement shown in fig. 2; the leads led out from the same differential pair are led out side by side outwards, the leads are tightly attached to the surface of the PCB, all via holes formed in the PCB are avoided, the leads are not overlapped with the via holes, and the two leads led out from the same differential pair are tightly attached to each other, so that the two leads are ensured not to pass through the two sides of the same via hole.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A differential wiring arrangement structure is characterized by comprising a differential line group formed by at least three differential pairs, wherein each differential pair of each differential line group is centrosymmetrically distributed, each differential pair comprises a P-type pin and an N-type pin, and wires are respectively led out from the P-type pin and the N-type pin;
and the outer side of the differential line group is provided with a backflow ground hole, and two adjacent differentials share the same backflow ground hole.
2. A differential routing arrangement according to claim 1, wherein the symmetry center of the set of differential lines is provided with a return ground via shared by each differential pair in the set.
3. A differential routing arrangement according to claim 2, wherein the set of differential lines consists of six differential pairs.
4. A differential routing arrangement according to claim 3, wherein the outer pin of one of the differential pairs is disposed on a connection line of the inner pins of two adjacent differential pairs.
5. The differential routing arrangement of claim 4, wherein the pitch of the inner pins and the outer pins of one differential pair is equal to the pitch of the inner pins of two adjacent differential pairs.
6. The differential routing arrangement according to claim 5, wherein a lateral spacing between adjacent vias is 30-50 mils.
7. A differential routing arrangement according to any one of claims 1 to 6, wherein there is a common differential pair for two adjacent differential line groups.
8. The differential trace arrangement according to claim 7, wherein the wires from the same differential pair are routed side-by-side and outward to avoid vias formed in the PCB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111274609.4A CN114173470B (en) | 2021-10-29 | 2021-10-29 | Differential wiring arrangement structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111274609.4A CN114173470B (en) | 2021-10-29 | 2021-10-29 | Differential wiring arrangement structure |
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| Publication Number | Publication Date |
|---|---|
| CN114173470A true CN114173470A (en) | 2022-03-11 |
| CN114173470B CN114173470B (en) | 2024-02-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111274609.4A Active CN114173470B (en) | 2021-10-29 | 2021-10-29 | Differential wiring arrangement structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117293110A (en) * | 2023-11-24 | 2023-12-26 | 湖北芯擎科技有限公司 | Pin arrangement structure and high-speed differential signal chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159080A (en) * | 2003-11-27 | 2005-06-16 | Kyocera Corp | Wiring board |
| US20050202722A1 (en) * | 2004-02-13 | 2005-09-15 | Regnier Kent E. | Preferential via exit structures with triad configuration for printed circuit boards |
| EP1841298A2 (en) * | 2004-02-13 | 2007-10-03 | Molex Incorporated | Plated vias exit structure for printed circuit board |
| US20110203843A1 (en) * | 2006-10-13 | 2011-08-25 | Taras Kushta | Multilayer substrate |
| CN203015284U (en) * | 2012-12-21 | 2013-06-19 | 广州兴森快捷电路科技有限公司 | High-speed PCB differential via-hole structure |
| US20180177043A1 (en) * | 2016-12-15 | 2018-06-21 | Advanced Micro Devices, Inc. | Circuit board with return path separated low crosstalk via transition structure |
| CN109076700A (en) * | 2016-03-08 | 2018-12-21 | 安费诺公司 | For high speed, the backboard encapsulation part of high density electrical connector |
| US10522949B1 (en) * | 2018-08-08 | 2019-12-31 | Qualcomm Incorporated | Optimized pin pattern for high speed input/output |
-
2021
- 2021-10-29 CN CN202111274609.4A patent/CN114173470B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159080A (en) * | 2003-11-27 | 2005-06-16 | Kyocera Corp | Wiring board |
| US20050202722A1 (en) * | 2004-02-13 | 2005-09-15 | Regnier Kent E. | Preferential via exit structures with triad configuration for printed circuit boards |
| EP1841298A2 (en) * | 2004-02-13 | 2007-10-03 | Molex Incorporated | Plated vias exit structure for printed circuit board |
| US20110203843A1 (en) * | 2006-10-13 | 2011-08-25 | Taras Kushta | Multilayer substrate |
| CN203015284U (en) * | 2012-12-21 | 2013-06-19 | 广州兴森快捷电路科技有限公司 | High-speed PCB differential via-hole structure |
| CN109076700A (en) * | 2016-03-08 | 2018-12-21 | 安费诺公司 | For high speed, the backboard encapsulation part of high density electrical connector |
| US20180177043A1 (en) * | 2016-12-15 | 2018-06-21 | Advanced Micro Devices, Inc. | Circuit board with return path separated low crosstalk via transition structure |
| US10522949B1 (en) * | 2018-08-08 | 2019-12-31 | Qualcomm Incorporated | Optimized pin pattern for high speed input/output |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117293110A (en) * | 2023-11-24 | 2023-12-26 | 湖北芯擎科技有限公司 | Pin arrangement structure and high-speed differential signal chip |
| CN117293110B (en) * | 2023-11-24 | 2024-02-09 | 湖北芯擎科技有限公司 | Pin arrangement structure and high-speed differential signal chip |
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| Publication number | Publication date |
|---|---|
| CN114173470B (en) | 2024-02-09 |
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