CN112420648B - Solder ball arrangement unit and packaged chip - Google Patents
Solder ball arrangement unit and packaged chip Download PDFInfo
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- CN112420648B CN112420648B CN202011183946.8A CN202011183946A CN112420648B CN 112420648 B CN112420648 B CN 112420648B CN 202011183946 A CN202011183946 A CN 202011183946A CN 112420648 B CN112420648 B CN 112420648B
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- solder ball
- signal
- signal solder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
The invention provides a solder ball arrangement unit and a packaged chip, wherein the solder ball arrangement unit comprises: first signal solder ball pair and second signal solder ball pair of vertical arrangement and enclose and locate first signal solder ball pair with a plurality of ground connection solder balls of second signal solder ball pair, first signal solder ball pair includes two first signal solder balls along first direction interval setting, second signal solder ball pair all includes two second signal solder balls along perpendicular first direction interval setting, first signal solder ball falls into two along the projection of first direction in the interval between the second difference signal solder ball. Through the mode, crosstalk among the solder ball arrangement units in the packaged chip is small, the signal transmission speed is increased, the density of solder balls in the prepared chip is improved, the area of the chip is small, and the preparation of a micro chip is facilitated.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a solder ball arrangement unit and a packaged chip.
Background
The package is used as a connecting carrier of a silicon chip and a PCB, plays a role in signal transmission and is an important component of a chip. With the development of serial communication technology, single channel rates have reached 112 Gbps; and the system capacity is getting larger and larger, a plurality of serial channels are inevitably integrated in a single chip. Multiple high-rate serial channels, which are transmitted within a package, can have a problem of cross-talk between the channels.
The main solder ball arrangements in the industry are shown in fig. 1 and 2: wherein TXP in fig. 1 and 2 is a positive receive port, TXN is a negative receive port, RXP is a positive transmit port, RXN is a negative transmit port, and VSS is a ground port. Each port pin is connected with a corresponding solder ball. It can be seen that, and as the rate increases, the industry typically reduces the effects of crosstalk by extending the distance between the serializer transmission and reception, adding one or more rows of solder balls, increasing the number of solder balls to increase the size of the package, and requiring greater isolation, more solder balls.
The above existing solutions have TXP and TXN and RXP and RXN between the serializer channels arranged in parallel, which has larger crosstalk, but will enlarge the chip area if the spacing is opened in the manner of increasing the spacing of the solder balls. This results in an integrated chip that cannot be miniaturized, however, if a small pitch solder ball arrangement is used, the physical distance between the channels of the receive port (TX) and the transmit port (RX) is reduced, and the crosstalk is degraded.
Disclosure of Invention
Based on the structure, the invention provides a solder ball arrangement unit and a packaged chip, so that the crosstalk among channels is reduced, and the miniaturization of a multi-channel integrated chip is ensured.
The invention provides a solder ball arrangement unit, which comprises:
a first signal solder ball pair and a second signal solder ball pair which are vertically arranged and a plurality of grounding solder balls which are arranged around the first signal solder ball pair and the second signal solder ball pair,
the first signal solder ball pair comprises two first signal solder balls arranged at intervals along a first direction, the second signal solder ball pair comprises two second signal solder balls arranged at intervals along a vertical first direction, and the projection of the first signal solder balls along the first direction falls into two intervals between the second differential signal solder balls.
Preferably, 6 grounding solder balls are arranged around the first signal solder ball and the second signal solder ball, and are respectively arranged on two sides of the first signal solder ball pair and the second signal solder ball pair.
Preferably, in the first direction perpendicular to the first direction, two sides of the first signal solder ball are symmetrically provided with one grounding solder ball, and two sides of the second signal solder ball pair are symmetrically provided with one grounding solder ball.
Preferably, 9 grounding solder balls are arranged around the first signal solder ball and the second signal solder ball, and are respectively arranged on two sides of the first signal solder ball pair and the second signal solder ball pair and between the first signal solder ball pair and the second signal solder ball pair.
Preferably, in the vertical first direction, two sides of the first signal solder ball are symmetrically provided with a grounding solder ball, two sides of the second signal solder ball pair are symmetrically provided with a grounding solder ball,
three grounding welding balls are arranged between the first signal welding ball pair and the second signal welding ball pair, and the three grounding welding balls are arranged at intervals along the first direction.
Preferably, the distance between adjacent solder balls is equal.
Preferably, the distance between the adjacent solder balls is 0.3mm or more.
The invention also provides a chip comprising:
a substrate;
the solder ball arrangement unit comprises the solder ball arrangement units.
Preferably, a plurality of grounding solder balls are shared between adjacent solder ball arrangement units.
The invention has the beneficial effects that the invention provides a solder ball arrangement unit and a packaged chip, wherein the solder ball arrangement unit comprises: first signal solder ball pair and the second signal solder ball pair of vertical arrangement and enclose and locate first signal solder ball pair with a plurality of ground connection solder balls of second signal solder ball pair, first signal solder ball pair includes two first signal solder balls along first direction interval setting, second signal solder ball pair all includes two second signal solder balls along perpendicular first direction interval setting, the projection of first signal solder ball along first direction falls into two in the interval between the differential signal solder ball of second. Through the mode, crosstalk among the solder ball arrangement units in the packaged chip is small, the signal transmission speed is increased, the density of solder balls in the prepared chip is improved, the area of the chip is small, and the preparation of a micro chip is facilitated.
Drawings
FIG. 1 is a schematic diagram of a first structure of a solder ball arrangement of a chip in the prior art;
FIG. 2 is a schematic diagram of a second structure of a solder ball arrangement of a chip in the prior art;
fig. 3 is a schematic diagram of a first structure of a solder ball arrangement unit according to an embodiment of the invention;
fig. 4 is a schematic diagram of a second structure of the solder ball arrangement unit according to the embodiment of the invention;
fig. 5 is a cross-talk loss curve of the chip 1 and the chip 3 in the three-dimensional electromagnetic field simulation software according to the embodiment of the present invention.
Fig. 6 is a cross-talk loss curve of the chip 2 and the chip 4 in the three-dimensional electromagnetic field simulation software according to the embodiment of the present invention.
Fig. 7 is a cross-talk loss curve of the chip 2 and the chip 3 according to the embodiment of the present invention under three-dimensional electromagnetic field simulation software.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Fig. 1-2 are schematic diagrams of two solder ball arrangements of a chip in the prior art, where the chip in fig. 1 has a small volume but the solder ball arrangement is likely to cause large inter-channel crosstalk, and fig. 2 adds a row of grounding solder balls between receiving and transmitting to reduce inter-channel crosstalk but the chip has a large volume, so that it is difficult to obtain a micro integrated chip.
Referring to fig. 3 and 4, fig. 3 and 4 are schematic structural views of two solder ball arrangement units on a packaged chip, respectively. The packaged chip comprises a substrate and a plurality of solder balls arranged on the substrate, and the plurality of solder balls form a plurality of solder ball arrangement units 1. Each solder ball arrangement unit 1 includes a first signal solder ball pair 11 and a second signal solder ball pair 12 which are vertically arranged, and a plurality of ground solder balls 13 which are arranged around the first signal solder ball pair 11 and the second signal solder ball pair 12.
A plurality of serial signal channels are integrated in the packaged chip, each serial signal channel comprises a transmitting end and a receiving end, the transmitting end and the receiving end respectively comprise a positive port and a negative port, namely each signal channel comprises a positive transmitting port, a negative transmitting port and a positive receiving port, and each serial signal channel corresponds to each solder ball arrangement unit 1. The signal solder ball pairs correspond to the upper ends, and each signal solder ball of the signal solder ball pairs corresponds to a pin of the port and is used for transmitting differential signals. If the first signal solder ball pair 11 corresponds to the transmitting terminal for transmitting signals, the second signal solder ball pair 12 corresponds to the receiving terminal for receiving signals (the reverse is also true). The first signal solder balls 11a1 and 11a2 correspond to positive and negative emitting ports (or negative and positive ports), respectively, and the second signal solder balls 12b1 and 12b2 correspond to positive and negative receiving ports (or negative and positive ports), respectively. The corresponding ends of the two pairs of signal solder balls can be reversed.
The first signal solder ball pair 11 includes two first signal solder balls 11a1 and 11a2 spaced apart in a first direction, the second signal solder ball pair 12 includes two second signal solder balls 12b1 and 12b2 spaced apart in a vertical first direction, and a projection of the first signal solder balls 11a1 and 11a2 in the first direction falls into a space between the two second signal solder balls 12b1 and 12b2, so that an intersection point of a straight line of the first signal solder ball pair 11 and a straight line of the second signal solder ball pair 12 is located between the second signal solder balls 12b1 and 12b 2. Preferably, the interval between the adjacent solder balls should be set to be greater than or equal to 0.3 mm.
Preferably, if a plurality of serial signal channels are integrated in the packaged chip and the packaged chip has a plurality of solder ball arrangement units 1, adjacent solder ball arrangement units 1 can share part of the ground solder balls 13, so that the number of the ground solder balls 13 is reduced, the area of the packaged chip is reduced, and the miniaturization of the packaged chip is facilitated.
In the solder ball arrangement unit 1 of the present invention, two pairs of signal solder ball pairs intersect vertically, and the positive port and the negative port of the first signal solder ball pair 11 to the second signal solder ball pair 12 have equal crosstalk magnitude but opposite phases, so that the crosstalks at the corresponding ends of the second signal solder ball pair 12 cancel each other out, thereby achieving the purpose of reducing crosstalk. Meanwhile, multiple rows of grounding solder balls are not required to be added between the ports, and the density of the solder balls in the prepared packaged chip is improved, so that the area of the packaged chip is small, and the preparation of a microchip is facilitated.
Example one
Referring to fig. 3, fig. 3 is a schematic view of a first structure of a solder ball arrangement unit according to an embodiment of the invention. The solder ball arrangement unit 1 includes a first signal solder ball pair 11, a second signal solder ball pair 12, and 6 ground solder balls 13 that are enclosed around the first signal solder balls 11a1 and 11a2 and the second signal solder balls 12b1 and 12b 2. In the embodiment of the present invention, the first signal solder ball pair 11 and the second signal solder ball pair 12 are vertically disposed to form an inverted T shape, and the 6 ground solder balls 13 are respectively disposed on two sides of the first signal solder ball pair 11 and the second signal solder ball pair 12 and are symmetrically disposed. Specifically, three rows are respectively arranged in the vertical first direction at intervals, one grounding solder ball c is symmetrically arranged on each of two sides of the first signal solder balls 11a1 and 11a2, and one grounding solder ball c is symmetrically arranged on each of two sides of the second signal solder ball pair 12. That is, in the vertical first direction, the first row is arranged as the ground solder ball c-the first signal solder ball 11a 1-the ground solder ball c; the second row is arranged as a ground solder ball c-the first signal solder ball 11a 2-the ground solder ball c (the arrangement order of the two first signal solder balls 11a1 and 11a2 in the same row is changeable, i.e. the first row is the first signal solder ball 11a2, the second row is the first signal solder ball 11a1, and-represents the space, and the same meaning is also given below); the third column is arranged as a ground solder ball c-the second signal solder ball 12b 1-the second signal solder ball 12b 2-the ground solder ball c (the two second signal solder balls 12b1 and 12b2 are replaceable in the same row order). The spacing between adjacent solder balls is equal. Preferably, the projections of the first signal solder balls 11a1 and 11a2 in the first direction fall in the middle of the interval between the second signal solder balls 12b1 and 12b 2.
Example two
Referring to fig. 4, fig. 4 is a schematic diagram of a second structure of the solder ball arrangement unit according to the embodiment of the invention. The solder ball arrangement unit 1 includes a first signal solder ball pair 11, a second signal solder ball pair 12, and 9 ground solder balls 13 that are enclosed around the first signal solder balls 11a1 and 11a2 and the second signal solder balls 12b1 and 12b 2. In the embodiment of the present invention, the first signal solder ball pair 11 and the second signal solder ball pair 12 are vertically disposed to form an inverted T shape, and the 9 ground solder balls 13 are respectively disposed on both sides of the first signal solder ball pair 11 and the second signal solder ball pair 12 and between the first signal solder ball pair 11 and the second signal solder ball pair 12 and are symmetrically disposed. Specifically, in the vertical first direction, two sides of the first signal solder balls 11a1 and 11a2 are symmetrically provided with a grounding solder ball c respectively, two sides of the second signal solder ball pair 12 are symmetrically provided with a grounding solder ball c respectively, and a row of grounding solder balls 13 is arranged between the first signal solder ball pair 11 and the second signal solder ball pair 12, that is, in the vertical first direction, four rows are provided, and the first row is arranged as a grounding solder ball c-a first signal solder ball 11a 1-a grounding solder ball c; the second row is arranged as a grounding solder ball c-the first signal solder ball 11a 2-the grounding solder ball c (the arrangement order of the two first signal solder balls 11a1 and 11a2 in the same row is changeable, i.e. the first row is the first signal solder ball 11a2, and the second row is the first signal solder ball 11a 1); the third row is arranged as a grounding solder ball c-a grounding solder ball c; the fourth row is arranged as a ground solder ball c-the second signal solder ball 12b 1-the second signal solder ball 12b 2-the ground solder ball c (the two second signal solder balls 12b1 and 12b2 are replaceable in the same row order). The spacing between adjacent solder balls is equal. Preferably, the projection of the first signal solder balls 11a1 and 11a2 in the first direction falls at the midpoint of the space between the second signal solder balls 12b1 and 12b2 (the two solder balls are replaceable in sequence, and-represent the space, hereinafter-also have the same meaning).
Results of Performance testing
The prior art of fig. 1 is taken as comparative example one, the resulting chip is denoted chip 1, the prior art of fig. 2 is taken as comparative example two, the resulting chip is denoted chip 2, the chip obtained in example one is denoted chip 3, and the chip obtained in example two is denoted chip 4. Under conditions consistent with other conditions of chips 1, 2, 3, and 4, such as thickness, pore size, and the like. And (3) comparing the crosstalk between the differential signal pairs of the chips by adopting three-dimensional electromagnetic field simulation. Please refer to fig. 5-7, which are cross-talk loss curves of the chip according to the embodiment of the present invention under the three-dimensional electromagnetic field simulation software. In the figure, conventional 1 denotes chip 1, conventional 2 denotes chip 2, inventory 1 denotes chip 3, and inventory 2 denotes chip 4.
From the cross talk in the frequency domain, the cross talk of the chips 3 and 4 obtained in the first and second embodiments of the present invention is much reduced compared with the cross talk of the chips 1 and 2 obtained in the prior art.
And considering the Noise of the whole frequency band, comparing the sizes of the Crosstalk of different arrangements under different baud rates by adopting Integrated Crosstalk Noise (ICN). Specifically, referring to table 1, table 1 shows the integrated crosstalk noise of the chips with different arrangements.
TABLE 1
Therefore, the chips 3 and 4 obtained in the first and second embodiments of the present invention have significant benefits in crosstalk and space (ground solder ball to signal solder ball ratio), and especially, the effects of increased transmission rate and increased density on printed circuit board design and package crosstalk are more significant.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (5)
1. A solder ball arrangement unit, comprising: the first signal solder ball pair and the second signal solder ball pair are vertically arranged, and a plurality of grounding solder balls are arranged around the first signal solder ball pair and the second signal solder ball pair, the first signal solder ball pair comprises two first signal solder balls arranged at intervals along a first direction, the second signal solder ball pair comprises two second signal solder balls arranged at intervals along the first direction, and the projection of the first signal solder balls along the first direction falls into the interval between the two second signal solder balls; 9 grounding solder balls are arranged around the first signal solder ball and the second signal solder ball and are respectively arranged on two sides of the first signal solder ball pair and the second signal solder ball pair and between the first signal solder ball pair and the second signal solder ball pair; in a first direction perpendicular to the first direction, two sides of the first signal solder ball are symmetrically provided with a grounding solder ball, two sides of the second signal solder ball pair are symmetrically provided with a grounding solder ball, three grounding solder balls are arranged between the first signal solder ball pair and the second signal solder ball pair, and the three grounding solder balls are arranged at intervals along the first direction.
2. The solder ball arrangement unit according to claim 1, wherein distances between adjacent solder balls are equal.
3. The solder ball arrangement unit according to claim 1, wherein a distance between adjacent solder balls is 0.3mm or more.
4. A chip, comprising: a substrate; a plurality of solder ball arrangement units disposed on the substrate, the solder ball arrangement units comprising the solder ball arrangement unit of any one of claims 1-3.
5. The chip of claim 4, wherein a plurality of ground solder balls are shared between adjacent solder ball placement units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011183946.8A CN112420648B (en) | 2020-10-29 | 2020-10-29 | Solder ball arrangement unit and packaged chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011183946.8A CN112420648B (en) | 2020-10-29 | 2020-10-29 | Solder ball arrangement unit and packaged chip |
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| CN112420648A CN112420648A (en) | 2021-02-26 |
| CN112420648B true CN112420648B (en) | 2022-08-16 |
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| CN114449762B (en) * | 2021-12-24 | 2023-08-25 | 苏州浪潮智能科技有限公司 | Method, device, equipment and medium for optimizing BGA chip pin distribution diagram |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1174407A (en) * | 1997-08-29 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device |
| JP4746770B2 (en) * | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US6933596B2 (en) * | 2003-07-01 | 2005-08-23 | Northrop Grumman Corporation | Ultra wideband BGA |
| US7207807B2 (en) * | 2004-12-02 | 2007-04-24 | Tyco Electronics Corporation | Noise canceling differential connector and footprint |
| US9089060B1 (en) * | 2010-10-19 | 2015-07-21 | Marvell Israel (M.I.S.L.) Ltd. | Ball-out for differential signals |
| JP2014138015A (en) * | 2013-01-15 | 2014-07-28 | Fujitsu Ltd | Printed board and method for manufacturing printed board |
| US9544992B2 (en) * | 2013-01-29 | 2017-01-10 | Fci Americas Technology Llc | PCB having offset differential signal routing |
| US9554454B2 (en) * | 2014-12-17 | 2017-01-24 | Intel Corporation | Devices and methods to reduce differential signal pair crosstalk |
| CN109600906A (en) * | 2017-09-30 | 2019-04-09 | 中航光电科技股份有限公司 | A kind of connector and signal transmission unit |
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