CN114167829B - Clock synchronization test method and device - Google Patents
Clock synchronization test method and device Download PDFInfo
- Publication number
- CN114167829B CN114167829B CN202111470228.3A CN202111470228A CN114167829B CN 114167829 B CN114167829 B CN 114167829B CN 202111470228 A CN202111470228 A CN 202111470228A CN 114167829 B CN114167829 B CN 114167829B
- Authority
- CN
- China
- Prior art keywords
- tested
- clock synchronization
- current time
- equipment
- synchronization server
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010998 test method Methods 0.000 title abstract description 9
- 238000012360 testing method Methods 0.000 claims abstract description 31
- 230000002159 abnormal effect Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 24
- 238000013515 script Methods 0.000 claims description 11
- 238000012986 modification Methods 0.000 claims description 6
- 230000004048 modification Effects 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 description 13
- 238000004891 communication Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 238000004590 computer program Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001364 causal effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005316 response function Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/33—Director till display
- G05B2219/33273—DCS distributed, decentralised controlsystem, multiprocessor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Electric Clocks (AREA)
Abstract
The embodiment of the application discloses a clock synchronization test method and a clock synchronization test device, which are used for improving the clock synchronization test efficiency of a distributed system so as to better ensure the correct operation of the distributed system. Modifying the current time of a clock synchronization server and the current time of equipment to be tested, and acquiring whether the current time of the equipment to be tested is consistent with the current time of the clock synchronization server or not after the current time of the clock synchronization server starts to be designated for a long time; and obtaining an output signal of the equipment to be tested so as to judge whether the output signal of the equipment to be tested is abnormal.
Description
Technical Field
The application relates to the technical field of industrial control, in particular to a clock synchronization test method and device.
Background
The distributed control system (distributed control system, DCS) is a typical distributed control system, and each controller cooperates to monitor and control the production process through a control network.
Clock synchronization is one of core technologies of a distributed system, and maintains a globally consistent physical or logical clock through clock synchronization, so that messages, events and time-related behaviors of all nodes in the system are globally consistent interpreted, namely, an identical observation reference point is ensured, and the fact that the messages sent and received by the nodes have correct causal relationship in time logic is ensured. How to improve the testing efficiency of the clock synchronization of the distributed system so as to better ensure the correct operation of the distributed system is a concern.
Disclosure of Invention
The embodiment of the application provides a clock synchronization test method and a clock synchronization test device, which can improve the test efficiency of the clock synchronization of a distributed system and better ensure the correct operation of the distributed system.
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:
the first aspect of the present application provides a clock synchronization test method, including:
And modifying the current time of the clock synchronization server and the current time of the equipment to be tested, and acquiring whether the current time of the equipment to be tested is consistent with the current time of the clock synchronization server after the current time of the clock synchronization server starts to be designated for a long time.
And obtaining an output signal of the equipment to be tested so as to judge whether the output signal of the equipment to be tested is abnormal.
In a possible implementation manner of the first aspect, the method further includes: and acquiring an event sequence record signal in one device to be tested and SOE signals among different devices to be tested. And acquiring a synchronous result of the equipment to be tested based on the event sequence record signal in the equipment to be tested and SOE signals among different equipment to be tested.
In a possible implementation manner of the first aspect, modifying the current time of the clock synchronization server and the current time of the device to be tested includes: when the first condition is met, the current time of the clock synchronization server and the current time of the device to be tested are modified.
In a possible implementation manner of the first aspect, the first condition includes that a current time of the clock synchronization server is within a preset time period.
A second aspect of the present application provides a clock synchronization test apparatus, comprising: the modifying module is used for modifying the current time of the clock synchronization server and the current time of the equipment to be tested, and acquiring whether the current time of the equipment to be tested is consistent with the current time of the clock synchronization server or not through the first acquiring module after the current time of the clock synchronization server starts a first duration. The judging module is used for acquiring the output signal of the equipment to be tested and judging whether the output signal of the equipment to be tested is abnormal or not.
In a possible implementation manner of the second aspect, the device further includes a second acquisition module, where the second acquisition module is configured to read an event sequence record signal in one device to be tested and an SOE signal between different devices to be tested. The first acquisition module is specifically configured to: and acquiring a synchronous result of the equipment to be tested based on the event sequence record signal in the equipment to be tested and SOE signals among different equipment to be tested.
In a possible implementation manner of the second aspect, the modification module is specifically configured to: when the first condition is met, the current time of the clock synchronization server and the current time of the device to be tested are modified.
In a possible implementation manner of the second aspect, the first condition includes that the current time of the clock synchronization server is within a preset time period.
A third aspect of the present application provides a clock synchronization test apparatus, comprising: a memory for storing computer readable instructions. Also included is a processor coupled to the memory for executing computer readable instructions in the memory to perform a method as described in the first aspect or any one of the possible implementations of the first aspect.
A fourth aspect of the application provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of any of the above aspects.
In a fifth aspect of the application, a computer program product or computer program is provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method of any of the above aspects.
From the above technical solutions, the embodiment of the present application has the following advantages: the scripts/tools of the clock synchronization server and the equipment to be tested can be modified, so that the current time of the clock synchronization server, the current time of the equipment to be tested and the time required by waiting for synchronization can be modified at any time according to requirements, and whether the time of the equipment to be tested and the time of the clock synchronization server are synchronous or not can be checked as soon as possible. After the clock synchronization test is carried out on the equipment to be tested and the clock synchronization server, whether the output signal of the equipment to be tested is abnormal or not is further detected, so that whether the equipment to be tested can operate correctly or not can be judged as soon as possible.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a clock synchronization test method according to an embodiment of the present application;
FIG. 2 is a flowchart of another clock synchronization testing method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a clock synchronization system according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a clock synchronization testing device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of another clock synchronization testing apparatus according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a clock synchronization test method and device, which are used for improving the clock synchronization efficiency of a distributed system and better ensuring the correct operation of the distributed system.
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "includes" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
In order to better understand the technical solution provided by the embodiments of the present application, the following first describes a study idea of the solution provided by the embodiments of the present application:
In a control system, clock synchronization is a basic and important function, and the time of each part of the system is unified through clock synchronization, so that the time consistency of various records and operations is ensured. In conventional testing, it is manually operated: modifying the time of the clock synchronization server, waiting for the arrival of a time synchronization period, and then checking the deviation of the time of the device to be tested and the clock synchronization server to acquire whether the time of the device to be tested and the time of the clock synchronization server are synchronous. This method has at least the following drawbacks:
(1) Time consuming, typically clock synchronization times are specified to be 5 minutes and more, so the process of the above-described test scheme needs to wait.
(2) The manual setting is needed, the unattended operation is impossible, and the manual test is boring.
(3) The time modification points cannot be inserted accurately manually, for example, the time modification cannot be inserted accurately in the middle of the multi-packet clock synchronization packet.
In order to solve the above technical problems, the applicant thinks that the scripts/tools of the clock synchronization server and the device to be tested can be modified, so that the current time of the clock synchronization server and the current time of the device to be tested can be modified at any time according to the requirement. In one possible implementation, the length of time required to wait for synchronization may also be modified as needed to see if the time of the device under test and the clock synchronization server are synchronized as soon as possible. In addition, different use cases can be further injected into the script of the clock synchronization server, and the system is indicated to automatically perform synchronization detection at fixed time through the use cases, for example, whether the equipment to be tested is synchronous with the time of the synchronization server or not is automatically detected at a primordial day or a weekend, manual participation is not needed, and the efficiency of synchronization test is greatly improved.
In addition, the applicant discovers through a large number of real clock synchronization scenes that after the equipment to be tested and the clock synchronization server complete clock synchronization in some scenes, the output signals of the equipment to be tested are abnormal, so that the normal operation of the equipment to be tested and the upstream and downstream equipment of the equipment to be tested is affected. The applicant finds out the problem and aims at the problem, and further thinks that after the device to be tested and the clock synchronization server perform clock synchronization test, the applicant needs to further detect whether the output signal of the device to be tested is abnormal or not so as to judge whether the device to be tested can operate correctly as soon as possible.
Based on the above study thought, the following specifically describes the scheme provided by the embodiment of the application:
Referring to fig. 1, fig. 1 is a flowchart of a clock synchronization testing method according to an embodiment of the application.
As shown in fig. 1, the method for testing clock synchronization according to the embodiment of the present application may be applied to the system for testing clock synchronization shown in fig. 3, where the system includes a clock synchronization server and a device to be tested. In the embodiment of the present application, the device to be tested is sometimes referred to as a controller, a control station or a site, which have the same meaning, and the description thereof will not be repeated.
As shown in fig. 1, the clock synchronization test method provided in the embodiment of the application includes the following steps:
101. And modifying the current time of the clock synchronization server and the current time of the equipment to be tested, and acquiring whether the current time of the equipment to be tested is consistent with the current time of the clock synchronization server or not after the current time of the clock synchronization server starts to be designated for a long time.
The current time of the clock synchronization server and the current time of the device to be tested are modified by modifying the script. In the embodiment of the present application, the script is also referred to as a tool, and both refer to the same meaning. Where the tool may be deployed on a clock synchronization server or on other devices. In a possible embodiment, the first time period may also be modified according to a modification script, where the first time period is used to represent a time period for waiting for the clock synchronization server and the device to be tested to synchronize, i.e. the time period required for waiting for synchronization as mentioned above.
The embodiment of the application allows the user to actively modify the current time of the clock synchronization server and the current time of the equipment to be tested according to the requirements, and in a possible implementation manner, the time required for waiting for synchronization can be modified so as to shorten the time required for clock synchronization and improve the efficiency of clock synchronization.
In a possible implementation manner, different use cases can be injected into the script, for example, different use cases are added to indicate whether the device to be tested is synchronous with the time of the synchronous server or not at the time of the primordial denier or the weekend or at a certain time point/section (such as certain special time points: 3:59, 2021.12.31, leap years, etc.), and by adopting the mode, the clock synchronous detection is automatically carried out without manual participation, so that the efficiency of synchronous test is greatly improved. In addition, it should be noted that, the embodiment of the present application is not limited to the manner of adding the use cases, and may be written in the script directly in a code manner, for example, as a time list, called by the code or written in a file (for example, excel) by the code, and read by the script for use. In this way, the requirements for manual testers are much smaller, and only the writing time in the document is needed according to the format.
Since it is generally required to transmit a plurality of synchronization service data packets between the synchronization server and the device to be tested to achieve high-precision clock synchronization, in one possible implementation, the clock synchronization service data packets may be monitored by a tool, and in the middle of a transmission time interval of any two data packets in the multi-packet data packets, the current time of the clock synchronization server and the current time of the device to be tested are modified, so that after the current time of the clock synchronization server starts for a first duration, the tool obtains whether the current time of the device to be tested and the current time of the clock synchronization server are consistent.
102. And obtaining an output signal of the equipment to be tested so as to judge whether the output signal of the equipment to be tested is abnormal.
According to the research thought, the applicant discovers through a large number of real clock synchronization scenes, and under some scenes, after clock synchronization is completed by the equipment to be tested and the clock synchronization server, output signals of the equipment to be tested can jump, so that normal operation of the equipment to be tested and upstream and downstream equipment of the equipment to be tested is affected. Based on the problem, after clock synchronization detection is performed, the scheme provided by the embodiment of the application also needs to judge whether the output signal of the device to be tested is abnormal. In one possible implementation manner, whether the output signal of the device to be tested is abnormal or not may be determined, for example, whether the output signal of the device to be tested is hopped or not may be determined, for example, whether a function related to time is abnormal, for example, whether a real-time response function is abnormal, whether a function related to a timer is abnormal or not, and so on may be determined. Specifically, the timer with long time timing can jump, fall back, advance or the like when the time of the controller changes. And checking whether the corresponding time-related functions can jump, fall back and the like after the controller is synchronized to other times by the clock synchronization server. It should be noted that, before, during and after the synchronization of the whole clock, whether the output signal of the device to be tested is abnormal is continuously and automatically observed.
In one possible implementation manner, the input signal of the device to be tested may be further obtained to determine whether the input signal of the device to be tested is abnormal.
In one possible implementation manner, in order to achieve a higher-precision test effect, a tool is used to read an event sequence record (sequence of event, SOE) signal in one device to be tested and SOE signals between different devices to be tested so as to obtain a synchronization result of the devices to be tested, and specifically, the time synchronization result in one device to be tested and between the different devices to be tested is compared according to the SOE signals. For a better understanding of this embodiment, the SOE signal is first described:
the SOE signal generally represents an accident state of an event process or a device, and the recorded result is mainly used for accident cause analysis, especially for analysis of the sequence of each event, so that compared with the general switching value measurement, the SOE module is not only capable of measuring the occurrence of the event, but also accurately reflecting the sequence of the event. The SOE signal is still actually a switching signal (only 2 states: ON, OFF). After the SOE measures the change of each signal state, the time of the change of the signal state is synchronously recorded, the generation and disappearance records of each event are marked with a 'time stamp', and then the record is sent to the controller for processing and is stored in the history record of the SOE.
Since there are typically multiple SOE modules (sometimes referred to herein as SOE cards) in a system and may be distributed among different process control stations, it is desirable that all SOE modules within the system maintain strict clock synchronization in order to ensure accuracy of event time recording. Clock synchronization errors can have a direct impact on the time value differences of event records.
Referring to fig. 2, a high-precision SOE signal source transmits high-precision synchronous or asynchronous pulse signals to a plurality of SOE modules. The tool reads the SOE signal accuracy in the station and the SOE signal accuracy between stations to determine the result of clock synchronization. In one possible implementation mode, a multi-path programmable pulse generator is adopted, each tested channel is connected to each output channel of the generator respectively, a group of pulses with the interval between paths being 0s are generated by the generator, and the method ensures that the time interval error of the channel output of the pulse generator is lower than 1/10-1/5 of the clock synchronization error.
Fig. 3 is a schematic diagram of an architecture of a clock synchronization system according to an embodiment of the present application. As shown in fig. 3, one or more clock synchronization servers may be included in the system, with one of the clock synchronization servers acting as a master clock synchronization server and the other clock synchronization servers acting as alternative clock synchronization servers, where the master synchronization server fails to provide normal operation, such as when a failure occurs, the alternative clock synchronization server is used to replace the master synchronization server to operate, it being understood that only one master synchronization server is present in the system. In addition, a plurality of controllers, i.e., devices to be tested, are included in the system. Each controller is connected with one SOE module, and the input of each SOE module is connected with a high-precision SOE source. The operation of each device shown in fig. 3 is described in fig. 1, and a detailed description thereof is not repeated here.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The names of messages or information interacted between the various devices in the embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.
The method for clock synchronization test provided by the embodiment of the application is introduced above, and the clock synchronization test device provided by the embodiment of the application is introduced below.
Fig. 4 is a schematic structural diagram of a clock synchronization testing device according to an embodiment of the present application.
As shown in fig. 4, a clock synchronization test device includes:
The modifying module 401 is configured to modify the current time of the clock synchronization server and the current time of the device to be tested, and after the current time of the clock synchronization server starts for a first duration, obtain, through the first obtaining module 402, whether the current time of the device to be tested and the current time of the clock synchronization server are consistent.
The judging module 403 obtains the output signal of the device to be tested, and judges whether the output signal of the device to be tested is abnormal.
In a possible embodiment, the method further includes a second acquisition module 404, where the second acquisition module 404 is configured to read a sequential event record signal in one device to be tested and a SOE signal between different devices to be tested.
The first obtaining module 402 is specifically configured to: and acquiring a synchronous result of the equipment to be tested based on the event sequence record signal in the equipment to be tested and SOE signals among different equipment to be tested.
In one possible implementation, the modification module 401 is specifically configured to: when the first condition is met, the current time of the clock synchronization server and the current time of the device to be tested are modified.
In one possible embodiment, the first condition includes that the current time of the clock synchronization server is within a preset time period.
Fig. 5 is a schematic hardware structure diagram of a clock synchronization testing apparatus according to an embodiment of the present application. Comprising the following steps: the communication interface 501 and the processor 502 may also include a memory 503.
The communication interface 501 may use any transceiver-like means for communicating with other devices or communication networks, such as ethernet, radio access network (radio access network, RAN), wireless local area network (wireless local area networks, WLAN), etc.
The processor 502 includes, but is not limited to, one or more of a central processing unit (central processing unit, CPU), a network processor (network processor, NP), an application-specific integrated circuit (ASIC), or a programmable logic device (programmable logic device, PLD). The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. The processor 502 is responsible for communication lines 504 and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 503 may be used to store data used by processor 502 in performing operations.
The memory 503 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (ELECTRICALLY ER server able programmable read-only memory, EEPROM), a compact disc (compact disc read-only memory) or other optical storage, optical storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be implemented on its own and coupled to the processor 502 via communication line 504. Memory 503 may also be integrated with processor 502. If the memory 503 and the processor 502 are separate devices, the memory 503 and the processor 502 may be connected, for example, the memory 503 and the processor 502 may communicate via a communication line. The communication interface 501 and the processor 502 may communicate through a communication line, and the communication interface 501 may also be directly connected to the processor 502.
Communication line 504 may include any number of interconnected buses and bridges, with communication line 504 linking together various circuits, including one or more processors 502, represented by processor 502, and memory, represented by memory 503. Communication line 504 may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., as are well known in the art and, therefore, will not be described further herein.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk Solid STATE DISK (SSD)), etc.
Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program to instruct related hardware, the program may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, etc.
The method for clock synchronization test and related equipment provided by the embodiment of the application are described in detail, and specific examples are applied to illustrate the principle and implementation of the application, and the description of the above examples is only used for helping to understand the method and core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (6)
1. A method for clock synchronization testing, comprising:
Modifying the current time of the clock synchronization server and the current time of the device to be tested by modifying the clock synchronization server and the script/tool of the device to be tested;
After the current time of the clock synchronization server starts to be designated for a long time, the current time of the equipment to be tested and the current time of the clock synchronization server are obtained, and whether the current time of the equipment to be tested and the current time of the clock synchronization server are consistent or not is judged;
acquiring an output signal of the equipment to be tested so as to judge whether the output signal of the equipment to be tested is abnormal;
The method further comprises the steps of: acquiring SOE signals of event sequence records in one device to be tested and SOE signals among different devices to be tested; and acquiring a synchronization result of the equipment to be tested based on the event sequence record signal in the equipment to be tested and SOE signals among different equipment to be tested.
2. The method of claim 1, wherein modifying the current time of the clock synchronization server and the current time of the device under test comprises:
And when the first condition is detected to be met, modifying the current time of the clock synchronization server and the current time of the equipment to be tested, wherein the first condition comprises that the current time of the clock synchronization server is in a preset time period.
3. A clock synchronization testing apparatus, comprising:
The system comprises a modifying module, a first acquiring module and a second acquiring module, wherein the modifying module is used for modifying the current time of a clock synchronization server and the current time of equipment to be tested by modifying scripts/tools of the clock synchronization server and the equipment to be tested, acquiring the current time of the equipment to be tested and the current time of the clock synchronization server by the first acquiring module after the current time of the clock synchronization server begins to specify a first duration, and judging whether the current time of the equipment to be tested and the current time of the clock synchronization server are consistent;
The judging module is used for acquiring the output signal of the equipment to be tested and judging whether the output signal of the equipment to be tested is abnormal or not;
The device also comprises a second acquisition module, wherein the second acquisition module is used for reading an SOE signal of an event sequence record in the equipment to be tested and SOE signals among different equipment to be tested; the first obtaining module is specifically configured to: and acquiring a synchronization result of the equipment to be tested based on the event sequence record signal in the equipment to be tested and SOE signals among different equipment to be tested.
4. The apparatus according to claim 3, wherein the modification module is specifically configured to:
And when the first condition is met, modifying the current time of the clock synchronization server and the current time of the equipment to be tested, wherein the first condition comprises that the current time of the clock synchronization server is in a preset time period.
5. A computer device, the computer device comprising a processor and a memory:
the memory is used for storing program codes; the processor is configured to perform the method of any one of claims 1 to 2 according to instructions in the program code.
6. A computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of any of the preceding claims 1 to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111470228.3A CN114167829B (en) | 2021-12-03 | 2021-12-03 | Clock synchronization test method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111470228.3A CN114167829B (en) | 2021-12-03 | 2021-12-03 | Clock synchronization test method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114167829A CN114167829A (en) | 2022-03-11 |
| CN114167829B true CN114167829B (en) | 2024-05-14 |
Family
ID=80482897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111470228.3A Active CN114167829B (en) | 2021-12-03 | 2021-12-03 | Clock synchronization test method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114167829B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114779883B (en) * | 2022-05-17 | 2024-03-19 | 西安易朴通讯技术有限公司 | System clock synchronization method, device, system and storage medium |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030041608A (en) * | 2001-11-20 | 2003-05-27 | 엘지전자 주식회사 | Apparatus and method for self test and frequency shift detection in network synchronization system |
| CN1801023A (en) * | 2005-11-14 | 2006-07-12 | 杨卫民 | Multi-event sequential recording and testing system |
| KR100856079B1 (en) * | 2007-02-28 | 2008-09-02 | (주)디지털프론티어 | Semiconductor tester |
| CN102097049A (en) * | 2011-03-14 | 2011-06-15 | 昆山精讯电子技术有限公司 | Signal self-adaption device and method for liquid crystal module testing |
| CN102204099A (en) * | 2011-04-13 | 2011-09-28 | 华为技术有限公司 | Resetting device |
| CN105515708A (en) * | 2015-12-07 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | FC network based clock synchronization precision testing device and method |
| CN106712922A (en) * | 2015-11-12 | 2017-05-24 | 上海远景数字信息技术有限公司 | High-precision clock signal test system and high-precision clock signal test method |
| CN109274366A (en) * | 2018-09-26 | 2019-01-25 | 云南电网有限责任公司电力科学研究院 | The clock test instrument and clock test methodology of distribution terminal |
| CN110248374A (en) * | 2019-06-28 | 2019-09-17 | 京信通信系统（中国）有限公司 | Clock synchronous test system, method, apparatus and the storage medium of base station |
| CN110673589A (en) * | 2019-10-21 | 2020-01-10 | 浙江中控技术股份有限公司 | Clock synchronization test method and device |
| CN110969082A (en) * | 2019-10-28 | 2020-04-07 | 中国信息通信研究院 | Clock synchronization test inspection method and system |
| CN111694699A (en) * | 2020-05-23 | 2020-09-22 | 苏州浪潮智能科技有限公司 | Method and device for testing server BMC (baseboard management controller) automatic synchronization RTC (real time clock) |
| CN211928046U (en) * | 2019-12-11 | 2020-11-13 | 武汉显明科技有限公司 | Automatic distribution's power distribution terminal tester of simulation main website of distribution |
-
2021
- 2021-12-03 CN CN202111470228.3A patent/CN114167829B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030041608A (en) * | 2001-11-20 | 2003-05-27 | 엘지전자 주식회사 | Apparatus and method for self test and frequency shift detection in network synchronization system |
| CN1801023A (en) * | 2005-11-14 | 2006-07-12 | 杨卫民 | Multi-event sequential recording and testing system |
| KR100856079B1 (en) * | 2007-02-28 | 2008-09-02 | (주)디지털프론티어 | Semiconductor tester |
| CN102097049A (en) * | 2011-03-14 | 2011-06-15 | 昆山精讯电子技术有限公司 | Signal self-adaption device and method for liquid crystal module testing |
| CN102204099A (en) * | 2011-04-13 | 2011-09-28 | 华为技术有限公司 | Resetting device |
| CN106712922A (en) * | 2015-11-12 | 2017-05-24 | 上海远景数字信息技术有限公司 | High-precision clock signal test system and high-precision clock signal test method |
| CN105515708A (en) * | 2015-12-07 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | FC network based clock synchronization precision testing device and method |
| CN109274366A (en) * | 2018-09-26 | 2019-01-25 | 云南电网有限责任公司电力科学研究院 | The clock test instrument and clock test methodology of distribution terminal |
| CN110248374A (en) * | 2019-06-28 | 2019-09-17 | 京信通信系统（中国）有限公司 | Clock synchronous test system, method, apparatus and the storage medium of base station |
| CN110673589A (en) * | 2019-10-21 | 2020-01-10 | 浙江中控技术股份有限公司 | Clock synchronization test method and device |
| CN110969082A (en) * | 2019-10-28 | 2020-04-07 | 中国信息通信研究院 | Clock synchronization test inspection method and system |
| CN211928046U (en) * | 2019-12-11 | 2020-11-13 | 武汉显明科技有限公司 | Automatic distribution's power distribution terminal tester of simulation main website of distribution |
| CN111694699A (en) * | 2020-05-23 | 2020-09-22 | 苏州浪潮智能科技有限公司 | Method and device for testing server BMC (baseboard management controller) automatic synchronization RTC (real time clock) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114167829A (en) | 2022-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107222362B (en) | Automatic test platform for finished vehicle CAN network and optimization method thereof | |
| JP4856429B2 (en) | On-chip circuit for bus inspection | |
| CN102169846B (en) | Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer | |
| US7814387B2 (en) | Circuit state scan-chain, data collection system and emulation and verification method | |
| CN111385047A (en) | Time synchronization method and electronic equipment | |
| CN105515893B (en) | Method for determining position of sampling point | |
| CN114167829B (en) | Clock synchronization test method and device | |
| CN116802510A (en) | System, method and apparatus for high speed input/output margin testing | |
| CN113110370B (en) | Test system and method | |
| JP4417955B2 (en) | Test method by event format for timing related defect verification of integrated circuits | |
| CN110928795A (en) | Stability test method and device for upgrading storage system | |
| CN116362176A (en) | Circuit simulation verification method, verification device, electronic device and readable storage medium | |
| CN112398672A (en) | Message detection method and device | |
| US8942300B1 (en) | Integrated digitizer system with streaming interface | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN115470132A (en) | Test method, device, equipment and medium for automatic driving data recording system | |
| CN109375606A (en) | A kind of algorithm library test method | |
| US11150292B1 (en) | Voltage spike detector and system for detecting voltage spikes in semiconductor devices | |
| CN112054939A (en) | Precision testing method and device for high-precision clock synchronization | |
| CN115629929B (en) | Memory error detection method, system and equipment | |
| CN216486551U (en) | Automatic data recording equipment and system | |
| CN117233581B (en) | Chip testing method, device, equipment and medium | |
| EP0780037A2 (en) | A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing | |
| CN116112344B (en) | Method, equipment and medium for detecting machine room fault network equipment | |
| CN114697235B (en) | EtherCAT communication test method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |