CN114153762B - Serdes multi-rate dynamic reconfiguration system and field programmable gate array - Google Patents
Serdes multi-rate dynamic reconfiguration system and field programmable gate array Download PDFInfo
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Abstract
The invention provides a Serdes multi-rate dynamic reconfiguration system and a field programmable gate array, wherein the system comprises an I2C slave module, a register read-write module, a clock supply module and a plurality of conversion modules; the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output end of the clock supply module is respectively connected with the clock signal input end of the conversion module; the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port. The invention also provides a field programmable gate array. The invention reduces the development complexity and the design difficulty, reduces the development risk and improves the reliability, thereby playing a role in saving the cost.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a Serdes multi-rate dynamic reconfiguration system and a field programmable gate array.
Background
With the advent of the high-speed information age, there has been a growing demand for the operation and data transmission speeds of various electronic products. To give people a better application experience in the information age, circuit designers have proposed various implementations for high-speed interface transmission of data. High-speed circuit transmission techniques have been rapidly developed from initial multi-channel parallel data transmission to higher-speed serial data transmission. Among them, the high-speed serdes serial interface transmission technology derived from signal transmission in the communication field is the serial transmission technology with the highest transmission speed and the highest data stability at present, and is being widely applied to various fields. Wherein Serdes: (serializer/deserializer).
In the field of programmable logic chips, since the interior of an FPGA chip contains abundant logic resources, the data transmission and receiving quantity is very large, and therefore, the high-speed serdes serial interface transmission technology is widely applied to the design of FPGA programmable logic circuits. The Serdes IP provided by Xilinx, altera and Lattice of each large programmable chip manufacturer is only aimed at one rate, and does not support multiple rate adaptation. The high-speed ip of the FPGA does not support the problem of dynamic reconfiguration, and a plurality of serdes are required to be used or a plurality of FPGA images are required to be designed to realize different speeds, so that a chip with higher configuration is required to be adopted, and the cost of design hardware is increased; designing multiple images may result in increased complexity in the upper software design or may not meet customer requirements at all.
Disclosure of Invention
In order to solve the technical problems, the invention provides a Serdes multi-rate dynamic reconfiguration system and a field programmable gate array, which can realize Serdes multi-rate dynamic reconfiguration, reduce development complexity and design difficulty, reduce development risk and improve reliability, thereby playing a role in saving cost.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the Serdes multi-rate dynamic reconfiguration system comprises an I2C slave module, a register read-write module, a clock supply module and a plurality of conversion modules;
the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output ends of the clock supply modules are respectively connected with the clock signal input ends of the conversion modules;
the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port.
Further, the system also comprises a MAC module;
the I2C slave module receives an instruction for dynamic reconfiguration of the rate, and enables a rate switching register, wherein the rate switching register is used for switching the rate under the manual control of the GMII module and the STM16 module; and then adapting different speed interfaces through the MAC module.
Further, the I2C slave module receives a command for dynamically reconfiguring the rate, closes manual control of the GMII module and the STM16 module, dynamically reconfigure the conversion module in a polling mode and adapts different rate interfaces through the MAC module.
Further, after the MAC module performs the adaptation of interfaces with different rates, the link process of the interface between the MAC module and the opposite terminal is completed, and the uplink control module is informed of the current interface working rate through a register after the link is completed; the uplink control module is used for sending out a command for dynamically reconfiguring the speed.
Further, the conversion module comprises a physical coding sublayer and a physical medium adaptation layer;
the physical coding sublayer is used for realizing parallel signal frame header detection, data coding and decoding and data clock domain conversion; the physical medium adaptation layer is used for realizing parallel-serial conversion and serial-parallel conversion, signal de-emphasis, pre-emphasis and polarity inversion.
Further, the clock supply module is connected with the first reference clock signal and the second reference clock signal, and provides reference frequency for the conversion module through the first phase-locked loop; the first phase-locked loop comprises a QPLL0 and a QPLL1, and the switching of the clock switching signal is dynamically reconfigured through the DRP interface.
Further, the output end of the register read-write module is connected with the input end of the clock supply module through a DRP interface.
Furthermore, the first reference clock signal and the second reference clock signal are also connected with the output end of the second phase-locked loop; the second phase-locked loop provides different frequency point reference frequencies for each rate serdes;
and the input end of the second phase-locked loop is connected with the crystal oscillator.
The invention also provides a field programmable gate array, which comprises a PS side and a PL side of the field programmable gate array chip; the PS side and the PL side are in communication connection through an I2C bus;
the PL side comprises the Serdes multi-rate dynamic reconfiguration system;
the PS side is an operating system of the PL side; and the PS side is in communication connection with the uplink control module.
Furthermore, the field programmable gate array chip selects a Zynq7015 chip of Xilinx.
The effects provided in the summary of the invention are merely effects of embodiments, not all effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
the invention provides a Serdes multi-rate dynamic reconfiguration system and a field programmable gate array, wherein the system comprises an I2C slave module, a register read-write module, a clock supply module and a plurality of conversion modules; the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output end of the clock supply module is respectively connected with the clock signal input end of the conversion module; the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port. Based on the Serdes multi-rate dynamic reconfiguration system, the invention also provides a field programmable gate array. According to the invention, the CPU can realize multi-rate dynamic reconfiguration of the port by dynamically reconfiguring the gt_common and the gt_channel. The CPU dynamically rearranges the parameters of the gt_common and the gt_channel in a timing way, and then the port link state after the training configuration can realize multi-rate self-adaptive adjustment. The CPU operation can be completed in the FPGA, so that development complexity and design difficulty are reduced, development risk is reduced, reliability is improved, and cost is saved.
Drawings
FIG. 1 is a schematic diagram of a hardware connection of a Serdes multi-rate dynamic reconfiguration system according to embodiment 1 of the present invention;
FIG. 2 is a schematic diagram illustrating connection of a conversion module in embodiment 1 of the present invention;
FIG. 3 is a block diagram of a high-speed bank clock architecture according to embodiment 1 of the present invention;
fig. 4 is a block diagram of a serdes multi-rate dynamic reconfiguration in embodiment 1 of the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present invention.
Example 1
The embodiment 1 of the invention provides a Serdes multi-rate dynamic reconfiguration system, and researches a dynamic reconfiguration scheme of a high-speed IP, so that development difficulty and risk can be reduced, operation cost can be reduced, and the aim of improving economic benefit can be achieved.
FIG. 1 is a schematic diagram of a hardware connection of a Serdes multi-rate dynamic reconfiguration system according to embodiment 1 of the present invention;
wherein: serdes: (serializer/deserializer);
the FPGA is a (Field Programmable Gate Array) field programmable gate array;
GMII (Gigabit Medium Independent Interface) gigabit media independent interface;
1000BASE-X (Serial Peripheral Interface) fiber-optic gigabit ethernet;
STM16 (Synchronous transfer Moudule) synchronous transmission module;
DPLL: (Digital Phase Locked Loop) a digital phase-locked loop;
PMA: (Physical media adaptation layer) a physical media adaptation layer;
PCS: (Physical coding sublayer) a physical coding sublayer;
MAC: (Media access control layer) Medium Access control layer
CDR: (clock data recovery) clock data recovery;
DDR: (Double Data Rate SDRAM) a double rate synchronous dynamic random access memory;
PS: (Processing System) a processing system;
PL: (Programmable Logic) programmable logic.
Wherein the FPGA adopts a Zynq7015 chip of Xilinx, the chip adopts a 28nm technology, the maximum speed is supported by serdes at 6.25Gbps, and the total bandwidth of the chip serdes is 25Gbps.
The dynamic memory DDR is in communication connection with the PS of the FPGA and is used for running boot and kernel use; the first optical module and the second optical module are mounted on a PL side high speed bank of Zynq, and design rates are set to be 1Gbps and 2.5Gbps due to chip serdes bandwidth limitation. The DPLL is a digital phase-locked loop, mainly providing different frequency point reference frequencies for each rate serdes.
A phase locked loop is a phase feedback control system in which the controlled output voltage change is discrete rather than continuous, as the error control signal is a discrete digital signal rather than an analog voltage; in addition, the loop component is also realized by a digital circuit, so that the phase-locked loop is called an all-digital phase-locked loop (DPLL for short).
Fig. 4 is a block diagram of a serdes multi-rate dynamic reconfiguration in embodiment 1 of the present invention, that is, through an implementation architecture of a plside inside zynq, the system includes a 2C slave module, a register read-write module, a clock supply module, and a plurality of conversion modules;
the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output end of the clock supply module is respectively connected with the clock signal input end of the conversion module;
the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port.
The clock supply module is a gt_common module, and the conversion module is a gt_channel module. The gt_common module mainly provides a reference clock for the gt_channel module. The gt_channel module mainly realizes high-speed serial interface parallel-serial conversion, serial-parallel conversion and clock domain conversion.
The GMII module calls the ip of the 1000M base-x of the Xilinx, and the system also comprises an MAC module;
the I2C slave module receives an instruction for dynamic reconfiguration of the rate, and enables a rate switching register, wherein the rate switching register is used for switching the rate under the manual control of the GMII module and the STM16 module; and then adapting different speed interfaces through the MAC module.
I2C receives the instruction of dynamic reconfiguration of the rate from the module, closes the manual control of the GMII module and the STM16 module, adopts a polling mode to dynamically reconfigure the conversion module and adapts different rate interfaces through the MAC module
In the invention, the dynamic reconfiguration process enables manual control of the GMII module and the STM16 rate switching register through the I2C interface by upper software, the FPGA completes the configuration of different rate parameters of the gt_channel, and the mac layer performs the adaptation of different rate interfaces to complete the high-speed port communication. In addition, the module also supports an automatic adaptation process, the upper software closes a manual control register through an I2C interface, enables the automatic adaptation register, and the FPGA dynamically re-adapts different rates of a gt_channel layer and a mac layer in a training mode to finish a link process of an opposite interface, and informs a CPU of the current interface working rate through the register after the link is finished.
FIG. 2 is a schematic diagram illustrating connection of a conversion module in embodiment 1 of the present invention; gt_channel comprises PCS (physical coding sublayer) and PMA (physical medium adaptation layer) modules. The PMA mainly implements parallel-to-serial conversion and serial-to-parallel conversion, signal de-emphasis, pre-emphasis, polarity inversion, etc. PCS mainly realizes parallel signal frame header detection, data encoding and decoding, data clock domain conversion and the like.
In the application, an MAC layer sends an Ethernet message and STM16 frames to a Physical Coding Sublayer (PCS) through an FPGA sending interface, and then sends the message to an optical module through 8B/10B coding, clock domain conversion, scrambling process, parallel-serial conversion, pre-emphasis/de-emphasis process and other processes; the receiving process comprises pre-emphasis/de-emphasis, out-of-band management, clock recovery, serial-parallel conversion, data alignment, data decoding, data clock domain conversion, reaching the FPGA receiving interface, and processing by the MAC layer to complete data negotiation and the like.
The clock supply module is connected with a first reference clock signal and a second reference clock signal, and provides reference frequency for the conversion module through the first phase-locked loop; the first phase-locked loop includes QPLL0 and QPLL1, and the switching of the clock switching signal is dynamically reconfigured by the DRP interface.
The output end of the register read-write module is connected with the input end of the clock supply module through a DRP interface.
The first reference clock signal and the second reference clock signal are also connected with the output end of the second phase-locked loop; the second phase-locked loop provides different frequency point reference frequencies for each rate serdes;
the input end of the second phase-locked loop is connected with the crystal oscillator. In example 1 of the present invention, two crystal oscillators connected to the DPLL are shown in FIG. 1, with frequencies of 19.44MHz and 25MHz, respectively.
FIG. 3 is a block diagram of a high-speed bank clock architecture according to embodiment 1 of the present invention; there are two sets of reference clock inputs mgt _clk0 and mgt _clk1 in the high speed bank clock architecture block diagram presented in fig. 3. There are four sets of serdes on the high speed bank, each set of serdes having a cpll pll, and a set of gt_common, which contains 2 QPLL pll phase-locked loops. Dynamic reconfiguration the dynamic reconfiguration of gt_common mode is used to provide the required frequency for gt_channel.
As can be seen from the above graph, the high-speed bank is composed of 4 groups of high-speed channels, each group of channels is provided with a cpll phase-locked loop, the linear speed is 1.6 GHz-3.3 GHz, and the phase-locked loop can be used for providing a reference clock; higher line rate designs require the use of a QPLL phase locked loop to provide the reference clock. The QPLL phase-locked loop comprises two groups of phase-locked loops QPLL0 and QPLL1, and the clock switching can be dynamically reconfigured by the DRP interface. CPLL phase locked loops are used in the design to provide the reference clock.
The serdes multi-rate dynamic reconfiguration system provided by the embodiment 1 of the invention consists of a GMII module, an i2c_slave module, a cpu_if module, a gt_common module and a gt_channel module. The CPU can realize the multi-rate dynamic reconfiguration of the ports by dynamically reconfiguring the gt_common and the gt_channel. The CPU dynamically reconfigures the parameters of the gt_common and the gt_channel at regular time, and then judges the link state of the configured port so as to realize multi-rate self-adaptive adjustment. The CPU operation can be completed in the FPGA, so that development complexity and design difficulty are reduced, development risk is reduced, reliability is improved, and cost is saved.
In addition, the invention can be used in the project of single-port multi-rate requirement, the serdes does not use dynamic reconfiguration to support 4 rates at most (limited by CPLL, the maximum linear rate is below 6.25 Gbps), and the high speed supports 2 rates at most (QPLL 0/1 provides clocks). The scheme can also be used to realize that the single port supports different service switching when the port needs to support different plane services. In addition, the scheme can also be used for realizing 10Gbps/25Gbps constant-speed rate switching on the intelligent network card.
Example 2
Based on the Serdes multi-rate dynamic reconfiguration system provided by the embodiment 1 of the invention, the embodiment 2 of the invention also provides a field programmable gate array, which comprises a PS side and a PL side of the field programmable gate array chip; the PS side and the PL side are in communication connection through an I2C bus;
the PL side comprises a Serdes multi-rate dynamic reconfiguration system;
the PS side is an operating system of the PL side; and the PS side is in communication connection with the uplink control module.
The field programmable gate array chip selects the Zynq7015 chip of Xilinx.
PS is a field programmable gate array (Processing System) processing system;
PL field programmable gate array (Programmable Logic) programmable logic. Multi-rate dynamic reconfiguration of the present application is achieved by implementing the reconfiguration in programmable logic.
The uplink control module is a CPU, and the CPU can realize multi-rate dynamic reconfiguration of the ports by dynamically reconfiguring the gt_common and the gt_channel. The CPU dynamically reconfigures the parameters of the gt_common and the gt_channel at regular time, and then judges the link state of the configured port so as to realize multi-rate self-adaptive adjustment.
The CPU operation can also be completed in the FPGA, namely through the PS side of the field programmable gate array, namely an operating system.
The PL side includes a Serdes multi-rate dynamic reconfiguration system for implementing multi-rate dynamic reconfiguration. Namely, through the implementation architecture of the PL side in the zynq, the system comprises a 2C slave module, a register read-write module, a clock supply module and a plurality of conversion modules;
the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output end of the clock supply module is respectively connected with the clock signal input end of the conversion module;
the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port.
The clock supply module is a gt_common module, and the conversion module is a gt_channel module. The gt_common module mainly provides a reference clock for the gt_channel module. The gt_channel module mainly realizes high-speed serial interface parallel-serial conversion, serial-parallel conversion and clock domain conversion.
The GMII module calls the ip of the 1000M base-x of the Xilinx, and the system also comprises an MAC module;
the I2C slave module receives an instruction for dynamic reconfiguration of the rate, and enables a rate switching register, wherein the rate switching register is used for switching the rate under the manual control of the GMII module and the STM16 module; and then adapting different speed interfaces through the MAC module.
I2C receives the instruction of dynamic reconfiguration of the rate from the module, closes the manual control of the GMII module and the STM16 module, adopts a polling mode to dynamically reconfigure the conversion module and adapts different rate interfaces through the MAC module
In the invention, the dynamic reconfiguration process enables manual control of the GMII module and the STM16 rate switching register through the I2C interface by upper software, the FPGA completes the configuration of different rate parameters of the gt_channel, and the mac layer performs the adaptation of different rate interfaces to complete the high-speed port communication. In addition, the module also supports an automatic adaptation process, the upper software closes a manual control register through an I2C interface, enables the automatic adaptation register, and the FPGA dynamically re-adapts different rates of a gt_channel layer and a mac layer in a training mode to finish a link process of an opposite interface, and informs a CPU of the current interface working rate through the register after the link is finished.
FIG. 2 is a schematic diagram illustrating connection of a conversion module in embodiment 1 of the present invention; gt_channel comprises PCS (physical coding sublayer) and PMA (physical medium adaptation layer) modules. The PMA mainly implements parallel-to-serial conversion and serial-to-parallel conversion, signal de-emphasis, pre-emphasis, polarity inversion, etc. PCS mainly realizes parallel signal frame header detection, data encoding and decoding, data clock domain conversion and the like.
In the application, an MAC layer sends an Ethernet message and STM16 frames to a Physical Coding Sublayer (PCS) through an FPGA sending interface, and then sends the message to an optical module through 8B/10B coding, clock domain conversion, scrambling process, parallel-serial conversion, pre-emphasis/de-emphasis process and other processes; the receiving process comprises pre-emphasis/de-emphasis, out-of-band management, clock recovery, serial-parallel conversion, data alignment, data decoding, data clock domain conversion, reaching the FPGA receiving interface, and processing by the MAC layer to complete data negotiation and the like.
The clock supply module is connected with a first reference clock signal and a second reference clock signal, and provides reference frequency for the conversion module through the first phase-locked loop; the first phase-locked loop includes QPLL0 and QPLL1, and the switching of the clock switching signal is dynamically reconfigured by the DRP interface.
The output end of the register read-write module is connected with the input end of the clock supply module through a DRP interface.
The first reference clock signal and the second reference clock signal are also connected with the output end of the second phase-locked loop; the second phase-locked loop provides different frequency point reference frequencies for each rate serdes;
the input end of the second phase-locked loop is connected with the crystal oscillator. In example 1 of the present invention, two crystal oscillators connected to the DPLL are shown in FIG. 1, with frequencies of 19.44MHz and 25MHz, respectively.
FIG. 3 is a block diagram of a high-speed bank clock architecture according to embodiment 1 of the present invention; there are two sets of reference clock inputs mgt _clk0 and mgt _clk1 in the high speed bank clock architecture block diagram presented in fig. 3. There are four sets of serdes on the high speed bank, each set of serdes having a cpll pll, and a set of gt_common, which contains 2 QPLL pll phase-locked loops. Dynamic reconfiguration the dynamic reconfiguration of gt_common mode is used to provide the required frequency for gt_channel.
As can be seen from the above graph, the high-speed bank is composed of 4 groups of high-speed channels, each group of channels is provided with a cpll phase-locked loop, the linear speed is 1.6 GHz-3.3 GHz, and the phase-locked loop can be used for providing a reference clock; higher line rate designs require the use of a QPLL phase locked loop to provide the reference clock. The QPLL phase-locked loop comprises two groups of phase-locked loops QPLL0 and QPLL1, and the clock switching can be dynamically reconfigured by the DRP interface. CPLL phase locked loops are used in the design to provide the reference clock.
The field programmable gate array provided by the embodiment 2 of the invention reduces development complexity and design difficulty, reduces development risk and improves reliability, thereby playing a role in saving cost.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.
While the specific embodiments of the present invention have been described above with reference to the drawings, the scope of the present invention is not limited thereto. Other modifications and variations to the present invention will be apparent to those of skill in the art upon review of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or variations which can be made by the person skilled in the art without the need of creative efforts are still within the protection scope of the invention.
Claims (6)
1. The Serdes multi-rate dynamic reconfiguration system is characterized by comprising an I2C slave module, a register read-write module, a clock supply module and a plurality of conversion modules;
the output end of the I2C slave module is connected with the input end of the clock supply module through the register read-write module; the output ends of the clock supply modules are respectively connected with the clock signal input ends of the conversion modules;
the I2C slave module is used for receiving a command of dynamic rate reconfiguration, and the register read-write module enables the clock supply module to provide a clock reference signal with preset frequency; the conversion module is used for receiving the reference clock signal provided by the clock supply module, realizing the parallel-serial conversion, the serial-parallel conversion and the clock domain conversion of the high-speed serial interface, and further realizing the multi-power dynamic reconfiguration of the port;
the system also includes a MAC module; the I2C slave module receives an instruction for dynamic reconfiguration of the rate, and enables a rate switching register, wherein the rate switching register is used for switching the rate under the manual control of the GMII module and the STM16 module; then, adapting interfaces with different rates through the MAC module;
the I2C slave module receives a speed dynamic reconfiguration instruction, closes manual control of the GMII module and the STM16 module, adopts a polling mode to dynamically reconfigure the conversion module and adapts different speed interfaces through the MAC module;
after the MAC module performs the adaptation of interfaces with different rates, the link process of the interface between the MAC module and the opposite end is completed, and the uplink control module is informed of the current interface working rate through a register after the link is completed; the uplink control module is used for sending out a command for dynamically reconfiguring the speed;
the clock supply module is connected with a first reference clock signal and a second reference clock signal, and provides reference frequency for the conversion module through the first phase-locked loop; the first phase-locked loop comprises a QPLL0 and a QPLL1, and the switching of the clock switching signal is dynamically reconfigured through the DRP interface.
2. The Serdes multi-rate dynamic reconfiguration system according to claim 1, wherein the conversion module includes a physical coding sublayer and a physical medium adaptation layer;
the physical coding sublayer is used for realizing parallel signal frame header detection, data coding and decoding and data clock domain conversion; the physical medium adaptation layer is used for realizing parallel-serial conversion and serial-parallel conversion, signal de-emphasis, pre-emphasis and polarity inversion.
3. The Serdes multi-rate dynamic reconfiguration system according to claim 1, wherein an output of the register read-write module is connected to an input of the clock supply module through a DRP interface.
4. The Serdes multi-rate dynamic reconfiguration system according to claim 1, wherein the first reference clock signal and the second reference clock signal are each further coupled to a second phase-locked loop output; the second phase-locked loop provides different frequency point reference frequencies for each rate serdes;
and the input end of the second phase-locked loop is connected with the crystal oscillator.
5. A field programmable gate array comprising a PS side and a PL side of a field programmable gate array chip; the PS side and the PL side are in communication connection through an I2C bus;
the PL side comprising the Serdes multi-rate dynamic reconfiguration system of any one of claims 1 to 4;
the PS side is an operating system of the PL side; and the PS side is in communication connection with the uplink control module.
6. The field programmable gate array of claim 5, wherein said field programmable gate array chip is a Zynq7015 chip of Xilinx.
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