CN116346141A - High-speed serializer/deserializer driver device based on phase-locked loop - Google Patents

High-speed serializer/deserializer driver device based on phase-locked loop Download PDF

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CN116346141A
CN116346141A CN202310313094.7A CN202310313094A CN116346141A CN 116346141 A CN116346141 A CN 116346141A CN 202310313094 A CN202310313094 A CN 202310313094A CN 116346141 A CN116346141 A CN 116346141A
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clock
phase
locked loop
frequency
deserializer
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郑文
彭梦晓
赵偲
王洲烽
吕成龙
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Taiyuan University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention relates to the field of information communication, and discloses a high-speed serializer/deserializer driver device based on a phase-locked loop, a receiver and a transmitter; the transmitter includes: the parallel data is input into the shift register when an externally added clock arrives, the parallel data is encoded by the encoding circuit and then sent to the shift register to be serially output, the phase-locked loop is used for outputting a first control clock for controlling the encoding circuit and a second control clock for controlling the shift register according to a reference clock, the first control clock is a clock with the same frequency and the same phase as the reference clock, and the second control clock is a ten-time frequency clock of the reference clock; in the receiver, an adaptive continuous time linear equalizer is arranged in the PMA layer for compensating signal distortion due to high frequency attenuation in the physical channel. The invention has high transmission quality and low power consumption, can be applied to internal connection comprising a workstation, a server and video transmission equipment, and is also suitable for optical fiber transmission.

Description

High-speed serializer/deserializer driver device based on phase-locked loop
Technical Field
The present invention relates to the field of information communication, and more particularly, to a high-speed serializer/deserializer driver apparatus based on a phase-locked loop.
Background
With the continuous development of technology, the rise of technologies such as big data, cloud computing, artificial intelligence and the like promotes the appearance of ultra-large data centers and the requirements for data transmission become higher. The conventional parallel data communication has not been suitable for the new generation of high-speed transmission requirements because of the need for a plurality of pins and the mutual crosstalk and clock synchronization problems between the parallel transmission lines, and the high-speed serial communication is becoming the mainstream communication mode. In the age of big data, in order to realize scalable storage, the use of databases for distributed storage is becoming a mainstream trend, and data transmission between databases requires ultra-high-speed serial communication, and transmission inside a data center mainly involves cable and cable transmission, whichever transmission requires high-speed wired serial communication.
SerDes is an abbreviation of serializer/deserializer, and the SerDes technology mainly converts a low-speed parallel data signal into a high-speed serial data signal and completes high-speed transmission of data by converting the high-speed serial data signal into the low-speed parallel signal.
At present, the SerDes technology has become a common important serial communication mode because of the characteristics of high transmission rate and low cost, wherein the SerDes technology has been widely applied in the field of I/0 communication, and the physical layers of high-speed interfaces such as SRIO, rapidIO and PCI-Express all use the SerDes interface. With the rapid development of SerDes technology, a high-speed serial port based on the SerDes technology is becoming a standard I/0 interface commonly used in the chip industry, and at present, in many middle and high-grade FPGA chips, high-speed SerDes channels are usually integrated to support various high-speed serial port communications, however, the conventional high-speed SerDes technology still has the problems of information loss caused by low transmission quality, so that a high-speed serializer/deserializer (SerDes) driver with high transmission quality and low power consumption needs to be provided.
Disclosure of Invention
The invention overcomes the defects existing in the prior art, and solves the technical problems that: a high-speed serializer/deserializer driver apparatus based on a phase-locked loop is provided to improve the transmission quality of SerDes.
In order to solve the technical problems, the invention adopts the following technical scheme: a phase locked loop based high speed serializer/deserializer driver apparatus comprising: a receiver and a transmitter;
the transmitter includes: the parallel data is input into the shift register when an externally added clock arrives, the parallel data is encoded by the encoding circuit and then sent to the shift register for serial output, the phase-locked loop is used for outputting a first control clock and a second control clock according to a reference clock, the first control clock is a clock with the same frequency and the same phase as the reference clock and is used for controlling the encoding circuit, and the second control clock is a ten-time frequency clock of the reference clock and is used for controlling the shift register to realize high-speed serial shift output of the data;
the receiver includes: a PMA layer and a PCS layer, in which an adaptive continuous time linear equalizer is provided for compensating signal distortion due to high frequency attenuation in a physical channel.
The phase-locked loop comprises a phase frequency detector, a charge pump, a voltage-controlled oscillator and a mode frequency detector;
and the external reference clock outputs ten times of frequency signals after passing through the phase frequency detector, the charge pump and the voltage-controlled oscillator, and outputs clocks with the same frequency and phase as the reference clock after passing through the phase frequency detector and the mode frequency-tenth device.
The voltage-controlled oscillator is of a four-stage differential ring oscillator structure.
The charge pump adopts a common mode feedback circuit with a differential structure, and comprises two pairs of charge-discharge current switches.
The high-speed serializer/deserializer driver device based on the phase-locked loop comprises two parallel clocks: PMA parallel clock domain XCLK and PCS parallel clock domain RXUSRCLK.
In the receiver, channel binding realizes the speed and phase consistency of the PMA parallel clock domain XCLK and the PCS parallel clock domain RXUSRCLK.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention provides a high-speed serializer/deserializer driver device based on a phase-locked loop, which adopts a full-differential four-stage ring oscillator and a charge pump in a transmitter, and a digital-analog hybrid high-speed point-to-point serial communication transmitting application-specific integrated circuit is designed and subjected to piece-casting test by self, wherein the highest transmission rate is 400Mbps, the power consumption is less than 400mW, and the embedded high-performance phase-locked loop has normal functions. The chip can be applied to internal connection comprising a workstation, a server and video transmission equipment, and is also applicable to optical fiber transmission.
(2) The self-adaptive continuous time linear equalizer with effective power is adopted in the receiver, so that signal distortion caused by high-frequency attenuation in a physical channel can be effectively compensated, and besides, on the basis that data can be correctly received, the speed is consistent, and the phase difference between two clock domains is solved.
Drawings
FIG. 1 is a schematic block diagram of a chip transmitter in accordance with the present invention;
FIG. 2 is a diagram of the internal phase lock loop of the chip transmitter of the present invention;
FIG. 3 is a block diagram of a voltage controlled oscillator of an internal circuit of a phase locked loop in a chip transmitter according to the present invention;
FIG. 4 is a circuit diagram of a single stage delay cell within a phase locked loop in a chip transmitter in accordance with the present invention;
FIG. 5 is a circuit diagram of a key portion of a charge pump within a PLL of a chip transmitter according to the present invention;
FIG. 6 is a block diagram of an equalizer in a chip receiver according to the present invention;
FIG. 7 is a diagram of the clock domain in the high speed serializer/deserializer;
FIG. 8 is a flowchart of the channel bonding sequence in the chip receiver of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a high-speed serializer/deserializer driver device based on a phase-locked loop, which comprises the following components: a receiver and a transmitter; the transmitter is responsible for serially converting multiple paths of low-speed parallel data into one path of high-speed serial data, transmitting the one path of high-speed serial data through a driver with high bandwidth and high linearity, transmitting the one path of high-speed serial data to the receiving end through a channel, and the receiver is responsible for converting received analog signals into digital signals and then deserializing the digital signals into multiple paths of low-speed parallel signals.
As shown in fig. 1, in this embodiment, the transmitter includes: the parallel data is input into the shift register when an external clock arrives, the parallel data is encoded by the encoding circuit and then transmitted to the shift register for serial output, the phase-locked loop is used for outputting a first control clock and a second control clock according to a reference clock, the first control clock is a clock with the same frequency and the same phase as the reference clock and used for controlling the encoding circuit, and the first control clock is a ten-time frequency clock of the reference clock and used for controlling the shift register to realize high-speed serial shift output of the data.
Specifically, in this embodiment, the transmitting path converts a low-speed parallel signal into a high-speed serial signal, and then sends the serial signal after operation processing such as encoding and emphasis, and includes the following steps:
step 2.1: the parallel data is input to the input shift register when an external clock (reference clock) arrives;
step 2.2: encoding and encoding into 10B codes by an 8B/10B encoding circuit, and serially outputting the 10B codes through a shift register;
step 2.3: the phase-locked loop outputs two control clocks according to the reference clock, wherein one clock is the same frequency and phase as the reference clock and is used for controlling the coding circuit; the other is a ten-times frequency clock of the reference frequency, which is used for controlling the data high-speed serial shift output.
As shown in fig. 2, in this example, the phase-locked loop adopts a charge pump phase-locked loop structure, and a charge pump and a frequency-tenth device are added on the traditional phase-locked loop structure, wherein the charge pump can effectively reduce the high-frequency noise of the control voltage of the voltage-controlled oscillator, and the frequency-tenth device makes the signal loss small and the transmission quality high. Specifically, the pll structure is composed of five parts, namely a Charge Pump (CP), a phase frequency detector (Phase Frequence Detecor, PFD), a voltage controlled oscillator (Voltage Controlled Oscillator, VCO), a Low-pass Filter (LPF), and a frequency divider (decade divider), where the output of the VCO is collected and divided by the frequency divider, and a reference clock is applied to the phase detector, and the phase detector compares the frequency differences of the two signals and outputs a dc pulse voltage to the Charge pump to control the VCO to change its frequency, so that the output of the VCO is stabilized at a certain desired value after a short period of time.
Specifically, the output frequency of an ideal voltage controlled oscillator is a linear function of its input voltage:
ω out (t)＝ω 0 +K vco u c (t)；(1)
wherein omega out (t) represents the output frequency, u c (t) is the input voltage, ω 0 The representation corresponds to u c Intercept at (t) =0, K vco The "gain" or "sensitivity" (in rad/(s.V)) of the circuit is indicated.
In this embodiment, the vco adopts a four-stage differential ring oscillator structure, i.e., is composed of four variable delay units, as shown in fig. 3. VCP, VCN are differential control voltages, CLKV1, CLKVO are differential high frequency outputs. The output cathode VO (-) of the first variable delay unit is connected with the input cathode VI (+) of the second variable delay unit, the output cathode VO (+) of the first variable delay unit is connected with the input cathode VI (-) of the second variable delay unit, and the second, third and fourth variable delay units are the same as the first variable delay unit, except that the output cathode VO (-) of the fourth variable delay unit is connected with the input cathode VI (-) of the first variable delay unit, and the output cathode VO (+) of the fourth variable delay unit is connected with the input cathode VI (+) of the second variable delay unit. The gate circuit INV is an inverter and has the functions of buffering and pulse shaping. The Bias terminal of each delay cell is a current Bias input terminal. The VCO adopts a fully differential structure by each stage of delay units to suppress power supply noise and injection noise of the substrate, and has the capability of providing multiphase signal output.
The oscillation frequency of the voltage controlled oscillator VCO is:
Figure BDA0004149223100000041
wherein N is the number of stages of delay units of the VCO, T d The propagation delay for each stage of delay cells is related to the control voltages VCN, VCP.
In this embodiment, the circuit of the single-stage delay unit is shown in fig. 4. The delay unit is composed of two paths with different delay time, one is a fast path and the other is a slow path, the two paths of output are overlapped to form a single-stage delay unit circuit, the gain of each path is controlled by control voltages VCP and VCN respectively, and the VCP and the VCN are differential signals, so when VCP is>In the case of VCNs, the effect of one of the paths is impaired and the effect of the other path is enhanced; vice versa, the total delay time of the delay unit is equal to the weighted sum of the delay times of the two paths, and in one extreme case, only the fast path is on and the slow path is completely off, the VCO generates the maximum oscillation frequency f max The method comprises the steps of carrying out a first treatment on the surface of the In the other extreme, only the slow path is on and the fast path is completeShut off, the VCO produces a minimum oscillation frequency f min 。
The output frequency produced by the overall ring oscillator can be expressed simply as:
Figure BDA0004149223100000051
in the above equation, the coefficient a is related to the differential control voltage VCP-VCN.
The receiver includes: a PMA layer and a PCS layer, in which an adaptive continuous time linear equalizer is provided for compensating signal distortion due to high frequency attenuation in a physical channel.
Specifically, in this example, the charge pump adopts a differential structure, the charge-discharge current switches are increased from the traditional two pairs to the two pairs, and the switch is similar to the structure of a comparator, so that the switch control signals UP and DOWN can be isolated from the VCN and VCP, no direct coupling path exists, the interference to the VCN and VCP when the level of the switch control signal is turned over is avoided, and the high-frequency noise of the VCO control voltage is effectively reduced.
In a phase locked loop, a charge pump plays a very important role, and its main function is to perform signal conversion, i.e. to convert a digital output signal of a phase frequency detector PFD into an analog signal, so as to control the VCO frequency. When the output signal of the PFD can accurately reflect the phase errors of the two input signals, the charge pump plays a decisive role in the performance of the whole phase-locked loop. When the PLL locks onto a certain frequency, the output voltage of the charge pump must be kept constant.
Ideally, the charge pump should have equal charge and discharge currents, however, when the output voltage of the charge pump changes, the charge and discharge currents also change due to the channel length modulation effect. When the output voltage of the charge pump increases, the charging current decreases and the discharging current increases, whereas when the output voltage decreases, the charging current increases and the discharging current decreases, and therefore, the charging and discharging currents are not equal, resulting in current mismatch, thereby generating ripple of the control voltage.
In order to keep the common mode level stable, so that the charge pump has good symmetry, the key circuit of the charge pump is shown in fig. 5, which is a common mode feedback circuit, wherein Vref and Bias are respectively a reference voltage and a differential control voltage, and the common mode level can be stabilized at about 1/2Vcc voltage. The differential inputs of the charge pump are driven by the output of the PFD. The pull-up pump circuit receives a differential signal from the PFD to raise the output voltage; on the other hand, the pull-down pump reduces the output voltage. The working principle is as follows: when the common mode level of the differential control voltages VCP and VCN is lower than 1/2Vcc, UP0 is higher than UP1, the current I4 is controlled by a MOS tube at the UP0, the common mode feedback circuit controls the MOS tube at the UP0 to generate a pull-UP feedback current which is overlapped with the pull-UP current of the Bias differential control voltage respectively, the injection current of the loop filter capacitor is increased, the common mode level of the control voltage is pulled back to 1/2Vcc upwards, and the longer the common mode level deviates from 1/2Vcc, the larger the generated pull-UP feedback current is, so that the upward pulling of the common mode level is accelerated; when the common mode level of the differential control voltages VCP and VCN is higher than 1/2Vcc, the low-side common mode feedback circuit has the same working process.
In this embodiment, the receiver is configured to convert a low-speed parallel signal into a high-speed serial signal, and then send the serial signal after processing operations such as encoding and emphasis.
The receiving path of the receiver comprises two major parts of a physical medium additional sublayer PMA and a physical coding sublayer PCS, a high-speed serial data stream is introduced into a PMA end from the outside and then flows into a PCS section from the PMA end to reach a user interface, the PMA mainly realizes the analog function of data transmission and mainly comprises Termination, a receiving equalizer, a receiving signal detection, JTAG (joint test action group) function, clock recovery and a deserializing module, wherein the Termination mainly functions are to provide input impedance and common mode voltage; the PCS is mainly a digital logic function part of SerDes, and mainly comprises a calibration module, a receiving equalizer control module, a receiving data path and a receiving signal control module.
In this embodiment, a receiver is provided with a power-efficient adaptive continuous-time linear equalizer (CTLE) as a receiving equalizer to compensate for signal distortion caused by high-frequency attenuation in a physical channel; the clock structure at the receiving end is mainly divided into a serial clock divider for reducing the PLL clock rate to support a lower line rate and a parallel clock divider for generating different parallel data clocks mainly according to the set bit width and whether 8b/10b is used or not. The receive path has two internal parallel clock domains: PMA parallel clock region (XCLK) and PCS parallel clock region (RXUSRCLK). The PMA parallel rate must match the RXUSRCLK clock rate and solve the cross-clock domain problem. The RX phase alignment circuit is used to adjust SIPO parallel clock and XCLK clock domain phase differences to ensure reliable transfer of data from SIPO to PCS components. It also adjusts the RX delay through RXUSRCLK to compensate for delays due to temperature or voltage variations. The accurate receiving of the data is ensured, the same speed is needed, and the phase difference between two clock domains is overcome; and channel bonding in the receiving end can absorb errors between two or more channels and provide data to the end user as if transmission were accomplished over only one link.
A linear equalizer (CTLE) can compensate for signal distortion due to high frequency attenuation in a physical channel, and the CTLE is called a low power consumption mode (LPM). The LPM mode has adaptive low frequency and high frequency enhancement functions as shown in fig. 6. Line rates up to 6.6Gb/s are suitable for short range applications where the channel loss at the Nyquist frequency is 12dB or less.
As shown in fig. 7, in this embodiment, two parallel clock domains are shown: XCLK and RXUSRCLK. In the present application, a special sequence, called a "channel binding sequence", is added to a data stream of a TX transmitting end, and after each receiving end receives the channel binding sequence, one of the receiving ends is designated as a main channel. The 'CHBONDO' communication link exists between the main channel and the slave channels, the main channel sends the position of the channel binding sequence in the buffer area to each slave channel, each slave channel calculates the deviation between the slave channel and the main channel according to the position of the channel binding sequence in the buffer area, and the read pointer of the buffer area is adjusted, so that synchronous output data of each channel is realized, as shown in figure 8.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (6)

1. A phase locked loop based high speed serializer/deserializer driver apparatus comprising: a receiver and a transmitter;
the transmitter includes: the parallel data is input into the shift register when an externally added clock arrives, the parallel data is encoded by the encoding circuit and then sent to the shift register for serial output, the phase-locked loop is used for outputting a first control clock and a second control clock according to a reference clock, the first control clock is a clock with the same frequency and the same phase as the reference clock and is used for controlling the encoding circuit, and the second control clock is a ten-time frequency clock of the reference clock and is used for controlling the shift register to realize high-speed serial shift output of the data;
the receiver includes: a PMA layer and a PCS layer, in which an adaptive continuous time linear equalizer is provided for compensating signal distortion due to high frequency attenuation in a physical channel.
2. A high speed serializer/deserializer driver apparatus based on a phase locked loop as defined in claim 1, wherein said phase locked loop includes a phase frequency detector, a charge pump, a voltage controlled oscillator, a mode tenth frequency device;
and the external reference clock outputs ten times of frequency signals after passing through the phase frequency detector, the charge pump and the voltage-controlled oscillator, and outputs clocks with the same frequency and phase as the reference clock after passing through the phase frequency detector and the mode frequency-tenth device.
3. A phase locked loop based high speed serializer/deserializer driver apparatus as in claim 2 wherein said voltage controlled oscillator is a four level differential ring oscillator architecture.
4. A high-speed serializer/deserializer driver apparatus based on a phase-locked loop according to claim 2, wherein said charge pump adopts a common-mode feedback circuit of differential structure including two pairs of charge-discharge current switches.
5. A phase locked loop based high speed serializer/deserializer driver apparatus as in claim 1 comprising two parallel clocks: PMA parallel clock domain XCLK and PCS parallel clock domain RXUSRCLK.
6. A phase locked loop based high speed serializer/deserializer driver apparatus as described in claim 5 wherein said channel bonding in said receiver achieves a rate and phase agreement of PMA parallel clock domain XCLK and PCS parallel clock domain RXUSRCLK.
CN202310313094.7A 2023-03-28 2023-03-28 High-speed serializer/deserializer driver device based on phase-locked loop Pending CN116346141A (en)

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