CN114141648A - Three-dimensional integrated wafer, test method thereof and three-dimensional integrated chip - Google Patents
Three-dimensional integrated wafer, test method thereof and three-dimensional integrated chip Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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Abstract
The invention provides a three-dimensional integrated wafer, a test method thereof and a three-dimensional integrated chip, wherein the three-dimensional integrated wafer comprises the following components: the wafer assembly comprises a plurality of wafer layers, wherein the wafer layers are stacked and connected through a connecting structure; the wafer assembly comprises a plurality of chip units, the detection loop is arranged around each chip unit, and the detection loop is configured to detect the connection condition of a plurality of wafer layers in each chip unit. The structure can effectively monitor the layering problem of the wafer in the chip, and improves the yield of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional integrated wafer, a test method thereof and a three-dimensional integrated chip.
Background
With the development of semiconductor technology, the cost for reducing the process size is increasingly difficult to bear. With the successful use of TSV (Through Silicon Via ), Hybrid Bonding, Silicon thinning, and other technologies, the 3D chip stacking technology can effectively enhance the functions and performance of electronic products while reducing the chip size, and thus is widely applied.
Currently, a wafer-level Bonding technology is mostly adopted in a 3D chip stacking technology, two or even more wafers are generally stacked, and for example, a Hybrid Bonding technology is used to bond two wafers face to generate inter-metal Bonding, so as to realize corresponding functions. Most of the research in the present stage focuses on how to make the bonding between the wafers more compact by the process technology, however, the complete process technology cannot avoid the problem of delamination at a part of the wafer caused by uncontrollable factors during the bonding process, and if the delamination occurs, the risk of wafer breakage occurs in the subsequent process. In addition, such defects still cause other sources of defects, which seriously affect the manufacturing yield of the wafer. Therefore, how to effectively monitor the wafer delamination problem becomes an important issue at present.
Disclosure of Invention
The invention provides a three-dimensional integrated wafer, a test method thereof and a three-dimensional integrated chip.
In order to solve the above technical problems, a first technical solution provided by the present invention is: provided is a three-dimensional integrated wafer, comprising: the wafer assembly comprises a plurality of wafer layers, wherein the wafer layers are stacked and connected through a connecting structure; the wafer assembly comprises a plurality of chip units, the detection loop is arranged around each chip unit, and the detection loop is configured to detect the connection condition of a plurality of wafer layers in each chip unit.
The wafer assembly comprises a plurality of cutting channels along a first direction and/or a second direction, the cutting channels divide the wafer assembly into a plurality of chip units, part of the detection loops of the wafer assembly are arranged on the cutting channels, and the first direction is perpendicular to the second direction.
The detection loops corresponding to two adjacent chip units are arranged on two sides of the cutting channel, and the detection loops corresponding to any chip unit are mutually independent.
Wherein each of the detection loops further comprises: the first power-on bonding pad is positioned in the cutting channel, and the signal input end of the detection loop is connected with the first power-on bonding pad; the second electrifying welding disc is positioned on the cutting channel, and the signal output end of the detection loop is connected with the second electrifying welding disc; the first powered pad receives a sense current and senses an output signal of the sense loop from the second powered pad.
Wherein each of the detection loops comprises a plurality of detection sub-loops: the signal input end of each detection sub-loop is connected with the first power-on bonding pad; and the signal output end of each detection sub-loop is connected with the second current-carrying pad.
Wherein the first and second power-on pads are pads of a test circuit in the scribe line.
In the adjacent chip units, the detection loops on two sides of the cutting channel are connected with the same group of test bonding pads, the adjacent test bonding pads in the same group of test bonding pads are connected, and the first electrifying bonding pad and the second electrifying bonding pad are respectively one of the same group of test bonding pads.
In the adjacent chip unit, the detection loop circuit on two sides of the cutting channel is connected with two groups of test pads, the two groups of test pads are not connected, the adjacent test pads in each group of test pads are connected, the first electrifying pad is one test pad in one group of test pads, and the second electrifying pad is one test pad in the other group of test pads.
Wherein the detection loop further comprises: the signal input end is connected with the first electrifying bonding pad through the selector switch, and the signal output end is connected with the second electrifying bonding pad through the selector switch.
Wherein a peripheral detection loop is arranged around the wafer assembly and configured to detect connection of the plurality of wafer layers in the wafer assembly.
The plurality of wafer layers comprise a first wafer layer and a second wafer layer; the detection loop comprises: the first conducting layer is positioned on the first wafer layer and comprises at least two first conducting strips; the second conducting layer is positioned on the second wafer layer and comprises at least two second conducting strips; the first conducting strip and the second conducting strip are connected in series through the connecting structure, and then the detection loop is formed.
Wherein, the connection structure includes: one end of the first connecting key is connected with the first conducting strip, and the other end of the first connecting key is close to the second wafer layer; one end of the second connecting key is connected with the second conducting strip, and the other end of the second connecting key is close to the first wafer layer; each first conducting strip is connected with two first connecting keys, each second conducting strip is connected with two second connecting keys, the vertical projection of each second conducting strip and the vertical projection of the two adjacent first conducting strips are provided with a superposition part, each first connecting key is correspondingly connected with one second connecting key, and then the first conducting strips and the second conducting strips are connected in series to form the detection loop.
Wherein, three-dimensional integrated wafer still includes: the isolating ring is positioned between the cutting channel and the chip unit, and the detection loop is positioned on one side of the isolating ring, which is far away from the chip unit; or, the detection loop is positioned between the isolation rings; or, the detection loop is the isolation loop.
In order to solve the above technical problems, a second technical solution provided by the present invention is: there is provided a three-dimensional integrated chip comprising: a chip unit; the periphery of the chip unit comprises at least part of cutting marks, and the cutting marks are marks for detecting loops after the wafer assembly is cut; the detection loop is arranged around each chip unit.
In order to solve the above technical problems, a third technical solution provided by the present invention is: a method for testing a three-dimensional integrated wafer is provided, which comprises the following steps: and detecting the connection condition of a plurality of wafer layers in each chip unit by using the detection loop around each chip unit.
Wherein the step of detecting the connection condition of the plurality of wafer layers in each of the chip units using the detection loop around each of the chip units comprises: inputting a detection current to the detection loop; receiving an output signal output by the detection loop, wherein the output signal comprises a voltage signal; determining a resistance value based on the detection current and the voltage signal; responding to the resistance value within a preset range, and ensuring that the connection condition of the wafer layers in the chip unit is normal; otherwise, the connection condition of the wafer layers in the chip unit is abnormal.
The three-dimensional integrated wafer has the advantages that the three-dimensional integrated wafer is different from the prior art, the detection loop is arranged around the chip units, the connection condition of a plurality of wafer layers in each chip unit is detected through the detection loop, the layering problem of the wafer in the chip can be effectively monitored, and the yield of the chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic structural diagram of a three-dimensional integrated wafer according to an embodiment of the present invention;
FIG. 2 is a partial schematic structural diagram of one embodiment of the three-dimensional integrated wafer shown in FIG. 1;
FIGS. 3 a-3 b are schematic views of the structure at position A in FIG. 2;
FIG. 4 is a partial schematic structural view of another embodiment of the three-dimensional integrated wafer shown in FIG. 1;
FIGS. 5-6 are schematic views of the structure at position B in FIG. 4;
FIG. 7 is a schematic diagram of a cross-sectional view of the three-dimensional integrated wafer shown in FIG. 1;
FIG. 8 is a schematic diagram of the structure of the chip unit in FIG. 1;
FIG. 9 is a schematic structural diagram of a three-dimensional integrated chip according to an embodiment of the present invention;
FIG. 10 is a flowchart illustrating an embodiment of a method for testing a three-dimensional integrated wafer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a three-dimensional integrated wafer according to an embodiment of the invention. The three-dimensional integrated wafer comprises a wafer assembly 100, wherein the wafer assembly 100 comprises a plurality of wafer layers, and the wafer layers are stacked and connected through a connecting structure. The wafer assembly 100 includes a plurality of chip units 110, a detection loop 120 is disposed around each chip unit 110, and the detection loop 120 is configured to detect connection conditions of a plurality of wafer layers in each chip unit 110.
Specifically, the wafer assembly 100 includes a plurality of scribe lines 130 along a first direction and/or a second direction, the scribe lines 130 divide the wafer assembly 100 into a plurality of the chip units 110, a portion of the detection loops 120 are disposed on the scribe lines 130, and the first direction is perpendicular to the second direction. As shown in fig. 1, the detection loops 120 of the chip unit 110 near the edge of the wafer assembly 100 are disposed at non-scribe locations, and as shown in the chip unit 1, the detection loops 120 at the left side and the upper side are disposed at non-scribe locations; as shown in the chip unit 3, the detection loop 120 on the upper side thereof is disposed at a non-scribe line position; as shown in the chip unit 2, the detection loops 120 on the left and lower sides thereof are disposed at the non-dicing lane positions.
It is understood that in one embodiment, the areas of the devices formed by the multiple wafer layers are the same in the same chip unit 110, for example, the chip unit 1 is composed of a logic chip and a memory chip stacked in a stacked arrangement, wherein the areas of the logic chip and the memory chip are the same. In another embodiment, the chip unit 1 may further include a plurality of memory chips, and the plurality of memory chips are disposed in a tiled manner and bonded to the logic chip in a stacked manner, that is, the area of the plurality of memory chips is the same as or smaller than the area of the logic chip. It is to be understood that, in this case, the detection loop is provided at an edge position near the logic chip among the plurality of memory chips.
Specifically, during the chip preparation process, dicing is performed from the dicing streets, so as to cut the wafer assembly 100 into a plurality of chip units 110. In the embodiment of the application, in the wafer-level preparation process, that is, the bonding condition of the wafer layer corresponding to each chip unit 110 is detected through the detection loop, so that the bonding yield of the cut chip can be ensured; furthermore, the method and the device can also position the specific position where the bonding problem occurs in time, are convenient for seeking a corresponding solution to improve in time, further reduce the cost and ensure the yield.
In an embodiment of the present application, the detection loops 120 corresponding to two adjacent chip units 110 are disposed on two sides of the scribe line 130, specifically, as shown in fig. 1, the detection loops 120 of the adjacent chip units 1 and 2 are respectively located on the upper and lower sides of the scribe line 130, and the detection loops 120 of the adjacent chip units 1 and 3 are respectively located on the left and right sides of the scribe line 130. Specifically, the detection loops 120 corresponding to any chip unit are independent of each other. For example, the detection loops 120 corresponding to the chip units 1, 2, and 3 do not interfere with each other, and the connection state of the wafer layers of the corresponding chip units can be detected individually.
In one embodiment, the stacked wafer further comprises: the pad group 140 is tested. The Test pad set 140 is located in the Scribe Line 130 and between the detection loops 120 on both sides of the Scribe Line 130, the Test pad set 140 is a pad of a Test circuit corresponding to the chip unit 110, and the Test circuit is a circuit for testing the function of the chip unit 110, for example, a WAT Test (Wafer Acceptable Test) is a method for measuring a specific Test structure (testkey) at the Scribe Line position of a Wafer during a Wafer manufacturing process by using a specific Test machine and determining whether there is an abnormality in the Wafer manufacturing process. WAT (wafer acceptance test) is widely used by wafer and bond shops to monitor process fluctuations at the wafer flow stage and detect anomalies in the production line, since corresponding tests can be performed at any stage of the wafer manufacturing process.
In one embodiment, as shown in fig. 2, each detection loop 120 further includes a first power-on pad 11 and a second power-on pad 12. The first and second current-carrying pads 11 and 12 are located in the scribe line 130. As shown in fig. 3a, fig. 3a is a schematic diagram of the position a in fig. 2, the signal input terminal n1 of the detection loop 120 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 is connected to the second power-on pad 12. Specifically, referring to fig. 2 and fig. 3a, the signal input terminal n1 of the detection loop 120 of the chip unit 1 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 of the chip unit 1 is connected to the second power-on pad 12. The signal input terminal n1 of the detection loop 120 of the chip unit 3 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 of the chip unit 3 is connected to the second power-on pad 12.
The first current-carrying pad 11 receives a detection current, drives the detection loop 120 by the detection current, and detects an output signal of the detection loop 120 from the second current-carrying pad 12, and determines a connection condition of the plurality of wafer layers in the chip unit based on the output signal.
As shown in fig. 3a, since the detection loops 120 of the chip unit 1 and the chip unit 3 share the same first current-carrying pad 11, when the first current-carrying pad 11 receives the detection current, the chip unit 1 and the chip unit 3 are simultaneously detected. For example, if a connection abnormality is detected, it is impossible to determine whether the connection of the chip unit 1 is abnormal or the connection of the chip unit 3 is abnormal, and therefore, it is necessary to detect the chip units 1 and 3 one by one. There are two ways, the first is to add a diverter switch as shown in fig. 3 a. For example, the signal input terminal n1 of the detection loop 120 of the chip unit 1 is connected to the first power-on pad 11 through the switch T1, and the signal output terminal n2 of the detection loop 120 of the chip unit 1 is connected to the second power-on pad 12 through the switch T3. The signal input terminal n1 of the detection loop 120 of the chip unit 3 is connected to the first power-on pad 11 through the switch T2, and the signal output terminal n2 of the detection loop 120 of the chip unit 3 is connected to the second power-on pad 12 through the switch T4. When the chip unit 1 is detected, the changeover switch T1 and the changeover switch T3 are turned on, the first current-carrying pad 11 receives the current signal to drive the detection loop circuit 120, and the second current-carrying pad 12 receives the output signal of the detection loop circuit 120. When the chip unit 3 is detected, the changeover switch T2 and the changeover switch T4 are turned on, the first current-carrying pad 11 receives the current signal to drive the detection loop circuit 120, and the second current-carrying pad 12 receives the output signal of the detection loop circuit 120. In a second embodiment, as shown in fig. 3b, the sense loops 120 of chip unit 1 and chip unit 3 are connected to different power pads. For example, the signal input terminal n1 of the detection loop 120 of the chip unit 1 is connected to the first power-on pad 11, and the signal output terminal n2 is connected to the second power-on pad 12; the signal input terminal n1 of the detection loop 120 of the chip unit 3 is connected to the first power-on pad 13, and the signal output terminal n2 is connected to the second power-on pad 14. When the chip unit 1 is tested, the first current-carrying pad 11 receives a current signal to drive the detection loop 120, and receives an output signal of the detection loop 120 from the second current-carrying pad 12. When the chip unit 3 is detected, the first current-carrying pad 13 receives a current signal to drive the detection loop 120, and receives an output signal of the detection loop 120 from the second current-carrying pad 14.
The method described above can detect the connection condition of the wafer layer of the chip unit 110, and locate the connection fault to the specific chip unit 110. In another embodiment, the connection fault may also be located to a specific location on the chip unit 110. In this embodiment, detection loop 120 includes multiple sub-detection loops. I.e. the detection loop 120 around the chip unit 110 is divided into a plurality of segments. Each section of detection sub-loop is provided with a signal input end and a signal output end, specifically, the signal input end of each detection sub-loop is correspondingly connected with a first electrifying bonding pad, and the signal output end of each detection sub-loop is correspondingly connected with a second electrifying bonding pad. It will be appreciated that the first power-on pads of each sense sub-loop are independent of each other and the second sense sub-loops are also independent of each other. To reduce wiring, the first and second power-on pads of each sense sub-loop are positioned proximate to the sense sub-loop. By means of the method, the connection condition around the chip unit can be detected in a segmented mode around the chip unit, and then the specific position of the connection fault is accurately located.
In the method described above, the corresponding power-on pad of the detection loop 120 is additionally disposed in the scribe line 130, which increases the number of devices in the scribe line 130. In another embodiment of the present application, energizing of the sense loop 120 may also be accomplished using existing pads within the dicing lane. That is, the first and second power-on pads 11 and 12 are pads of a test circuit in the scribe line 130, and the test circuit is a WAT test circuit.
As shown in fig. 4, the detection loop 120 connects test pads in the test pad group 140. According to the existing product, the test pad group 140 has a plurality of groups, and the test pads in each group are connected to each other, and the test pads in the groups are not connected to each other. In the adjacent chip unit 110, the detection loop 120 on both sides of the scribe line 130 connects two sets of test pads, the two sets of test pads are not connected, and the adjacent test pads in each set of test pads are connected, the first power-on pad is one of a set of test pads, and the second power-on pad is one of another set of test pads. Specifically, as shown in fig. 5, fig. 5 is a schematic diagram of the position B in fig. 4. In this embodiment, the test pad group includes a test pad group 31 and a test pad group 32, the test pads in the test pad group 31 are connected to each other, the test pads in the test pad group 32 are connected to each other, and the test pad group 31 is not connected to the test pad group 32. In the adjacent chip unit 1 and chip unit 3, the signal input terminal n1 of the detection loop 120 of the chip unit 1 is connected to the test pad 310 in the test pad group 31 (the test pad 310 is a first power-on pad), and the signal output terminal n2 is connected to the test pad 320 in the test pad group 32 (the test pad 320 is a second power-on pad). The signal input terminal n1 of the detection loop circuit 120 of the chip unit 3 is connected to the test pad 310 in the test pad group 31 (the test pad 310 is a first power-on pad), and the signal output terminal n2 is connected to the test pad 320 in the test pad group 32 (the test pad 320 is a second power-on pad). It should be noted that, in the existing standard WAT test structure, 22 test pads are usually a group of test pads.
As in the embodiment shown in fig. 3a described above, the detection loop further comprises: the signal input end is connected with the first electrifying bonding pad through the selector switch, and the signal output end is connected with the second electrifying bonding pad through the selector switch.
In another embodiment, the first and second power pads to which the detection loop of the chip unit 1 is connected, and the first and second power pads to which the detection loop of the chip unit 3 is connected may be different test pads.
In another embodiment, in the adjacent chip units, the detection loops on both sides of the scribe line are connected to the same group of test pads, adjacent test pads in the same group of test pads are connected, and the first conduction pad and the second conduction pad are respectively one of the same group of test pads. Specifically, as shown in fig. 5, in the present embodiment, the test loops of the chip unit 1 and the chip unit 3 are connected to two different test pads in the test pad group 31. Specifically, a signal input end n1 of the detection loop of the chip unit 1 is connected to the test pad 310 (first power-on pad) of the test pad group 31, and a signal output end n2 is connected to the test pad 311 (second power-on pad) of the test pad group 31; the signal input terminal n1 of the detection loop of the chip unit 3 is connected to the test pad 310 (first power-on pad) of the test pad group 31, and the signal output terminal n2 is connected to the test pad 311 (second power-on pad) of the test pad group 31.
In a possible embodiment of the present application, a peripheral inspection loop may be further disposed around the wafer assembly, and the peripheral inspection loop is configured to inspect the connection condition of the plurality of wafer layers in the wafer assembly. Specifically, when the three-dimensional integrated wafer is detected, the peripheral detection loop may be first powered by the driving current to detect the connection condition of the wafer layer in the three-dimensional integrated wafer, and if the connection is abnormal, the connection condition of the wafer layer in the chip unit 110 is further detected through the detection loop around the chip unit 110. Therefore, the detection program can be saved, and the efficiency is improved.
The present application is described by taking the example of bonding two wafer layers, and specifically, as shown in fig. 7, the wafer layers include a first wafer layer 71 and a second wafer layer 72. The detection loop 120 includes a first conductive layer and a second conductive layer. The first conductive layer is located on the first wafer layer 71, and the first conductive layer includes at least two first conductive sheets 711; the second conductive layer is located on the second wafer layer 72, and the second conductive layer includes at least two second conductive sheets 721. The first conductive plate 711 and the second conductive plate 721 are connected in series through the connecting structure, so as to form the detection loop 120. Specifically, the connection structure includes: a first connection key 712, and a second connection key 722. A first connection key 712 has one end connected to the first conductive plate 711 and the other end close to the second wafer layer 72; the second bond 722 has one end connected to the second conductive plate 721 and the other end near the first wafer layer 71. Each first conductive sheet 711 is connected to the first connecting key 712, each second conductive sheet 721 is connected to two second connecting keys 722, the vertical projections of each second conductive sheet 721 and the two adjacent first conductive sheets 711 have an overlapped part, each first connecting key 712 is correspondingly connected to one second connecting key 722, and the first conductive sheets 711 and the second conductive sheets 721 are connected in series to form the detection loop 120.
In the embodiment shown in fig. 7, the signal input of the detection loop 120 may be the first connection key 712, and may also be the second connection key 722.
In an embodiment of the present application, the stacked wafer further includes an isolation ring, the isolation ring 81, and the isolation ring 81 is used for blocking a dicing crack when the wafer is diced, so as to protect the chip units from being damaged. As shown in fig. 8, an isolation ring 81 is located between the scribe line 83 and the chip unit 84, and the detection loop 82 is located on a side of the isolation ring 81 away from the chip unit 84. I.e., sensing loop 82 is located within cutting street 83. In this way, the detection loop 82 forms a new isolation ring to further protect the chip unit 84 during dicing.
In another embodiment, the detection loop 82 may be located between the isolation rings 81. Alternatively, in another embodiment, detection loop 82 is an isolation loop 81. That is, when the spacer ring 81 is prepared, the structure of the spacer ring 81 is prepared as the structure of the detection loop 82 described above.
According to the stacked wafer, the chain-shaped metal layer and hybrid bonding through hole connecting structure designed at the connecting position of two wafers is added into a WAT test (wafer acceptance test) structure, and the structure is led out through a WAT test bonding pad, so that the structure capable of being detected through the WAT test (wafer acceptance test) in the production and manufacturing processes of the wafers and bonding is realized, the bonding layering condition in the production and manufacturing processes is represented by monitoring the test result (resistance value), and the bonding process is adjusted and improved in time according to the result. Specifically, the first wafer layer 71 and the second wafer layer 72 shown in fig. 7 are prepared, and then the first wafer layer 71 and the second wafer layer 72 are subjected to hybrid bonding. After the wafer bonding is finished, WAT testing is carried out under a certain current, output signals output by a detection loop are collected, the voltage value of the output signals is determined, corresponding resistance can be calculated through the current and the voltage, resistance data are collected, when the obtained resistance value is larger than a preset resistance value, the fact that a part of the position covered by the detection loop is open-circuited is indicated, the layering problem of the position covered by the WAT testing structure can be known, and the layering position can be determined according to the circuit covering position. The layering reason is confirmed by slicing at the position, the problems of the wafer bonding process in the manufacturing process are found in time, corresponding improvement is carried out, and larger economic loss caused by similar problems is avoided. By using the method, through electrical testing, the precision observed by naked eyes and a microscope is obviously improved, the efficiency is improved, only simple modification is needed to be carried out on the existing factory-end WAT testing structure, the layering condition in the wafer can be accurately judged, and the similar layering problem chips can be effectively ensured not to flow to a client side, so that more serious quality problems are caused. The method can be used for monitoring the layering problem caused by process problems in the 3D laminating process, can position the position of the problem in the wafer, and lays a foundation for subsequent process improvement schemes. Meanwhile, the structure is equivalent to a layer of seal ring (isolating ring) added on the periphery of the chip, so that the problem of layering of the bonding surface of the 3D attaching process of the chip in the subsequent cutting process can be effectively prevented.
Fig. 9 is a schematic structural diagram of a three-dimensional integrated chip according to an embodiment of the invention, which specifically includes a chip unit 91, where the periphery of the chip unit 91 includes at least a part of a dicing mark 92, and the dicing mark corresponds to a mark of a detection loop after a wafer assembly is diced. Wherein a detection loop is arranged around each of the chip units, the detection loop being the detection loop in any of the embodiments shown in fig. 1 to 8.
It can be understood that the detection loop of the present application is disposed at the dicing lane, and the detection loop may be damaged when the wafer assembly is diced, so that the detection loop may remain around the diced chip unit.
Referring to fig. 10, a flow chart of an embodiment of a three-dimensional integrated wafer according to the invention is shown, in which a detection loop around each chip unit is used to detect connection conditions of a plurality of wafer layers in each chip unit. The method specifically comprises the following steps:
step S101: a sense current is input to the sense loop.
Step S102: receiving an output signal output by the detection loop, wherein the output signal comprises a voltage signal.
Step S103: a resistance value is determined based on the sense current and the voltage signal.
Specifically, the current and voltage are known, i.e., the resistance value can be calculated.
Step S104: responding to the resistance value within a preset range, and ensuring that the connection condition of the wafer layers in the chip unit is normal; otherwise, the connection condition of the wafer layers in the chip unit is abnormal.
Specifically, in response to the resistance value being within the preset range, the connection condition of the wafer layer in the chip unit is normal, otherwise, the connection condition of the wafer layer in the chip unit is abnormal. For example, when the resistance value is greater than the preset resistance value, it is determined that the connection condition of the wafer layer in the chip unit is abnormal.
When the abnormality is not detected, the subsequent production and manufacturing processes can be continued to complete the production and manufacturing process of the wafer. If the abnormality is detected, the abnormal position can be sliced, the layering reason is determined, and the subsequent wafer bonding process is improved according to the layering reason.
According to the detection method of the stacked wafer, the chain-shaped metal layer and hybrid bonding through hole connecting structure designed at the connecting position of two wafers is added into a WAT test (wafer acceptance test) structure, and the structure is led out through a WAT test bonding pad, so that the structure which can be detected through the WAT test (wafer acceptance test) in the production and manufacturing processes of the wafers and bonding is realized, the bonding layering condition in the production and manufacturing processes is represented by monitoring the test result (resistance value), and the bonding process is adjusted and improved in time according to the result. Specifically, the first wafer layer 71 and the second wafer layer 72 shown in fig. 7 are prepared, and then the first wafer layer 71 and the second wafer layer 72 are subjected to hybrid bonding. After the wafer bonding is finished, WAT testing is carried out under a certain current, output signals output by a detection loop are collected, the voltage value of the output signals is determined, corresponding resistance can be calculated through the current and the voltage, resistance data are collected, when the obtained resistance value is larger than a preset resistance value, the fact that a part of the position covered by the detection loop is open-circuited is indicated, the layering problem of the position covered by the WAT testing structure can be known, and the layering position can be determined according to the circuit covering position. The layering reason is confirmed by slicing at the position, the problems of the wafer bonding process in the manufacturing process are found in time, corresponding improvement is carried out, and larger economic loss caused by similar problems is avoided. By using the method, through electrical testing, the precision observed by naked eyes and a microscope is obviously improved, the efficiency is improved, only simple modification is needed to be carried out on the existing factory-end WAT testing structure, the layering condition in the wafer can be accurately judged, and the similar layering problem chips can be effectively ensured not to flow to a client side, so that more serious quality problems are caused. The method can be used for monitoring the layering problem caused by process problems in the 3D laminating process, can position the position of the problem in the wafer, and lays a foundation for subsequent process improvement schemes. Meanwhile, the structure is equivalent to a layer of seal ring (isolating ring) added on the periphery of the chip, so that the problem of layering of the bonding surface of the 3D attaching process of the chip in the subsequent cutting process can be effectively prevented.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (16)
1. A three-dimensional integrated wafer, comprising:
the wafer assembly comprises a plurality of wafer layers, wherein the wafer layers are arranged in a stacked mode and are connected through a connecting structure;
the wafer assembly comprises a plurality of chip units, wherein a detection loop is arranged around each chip unit, and the detection loop is configured to detect the connection condition of a plurality of wafer layers in each chip unit.
2. The three-dimensional integrated wafer according to claim 1, wherein the wafer assembly comprises a plurality of scribe lines along a first direction and/or along a second direction, the scribe lines dividing the wafer assembly into a plurality of the chip units, and a portion of the detection loops of the wafer assembly are disposed on the scribe lines, and the first direction is perpendicular to the second direction.
3. The three-dimensional integrated wafer according to claim 2, wherein the detection loops corresponding to two adjacent chip units are disposed on two sides of the scribe line, and the detection loops corresponding to any one of the chip units are independent of each other.
4. The three-dimensional integrated wafer of claim 3, wherein each of the detection loops further comprises:
the first power-on bonding pad is positioned in the cutting channel, and the signal input end of the detection loop is connected with the first power-on bonding pad;
the second electrifying welding disc is positioned on the cutting channel, and the signal output end of the detection loop is connected with the second electrifying welding disc;
the first powered pad receives a sense current and senses an output signal of the sense loop from the second powered pad.
5. The three-dimensional integrated wafer of claim 4, wherein each of the inspection loops comprises a plurality of inspection sub-loops:
the signal input end of each detection sub-loop is connected with the first power-on bonding pad; and the signal output end of each detection sub-loop is connected with the second current-carrying pad.
6. The three-dimensional integrated wafer of claim 5, wherein the first and second powered pads are pads of a test circuit in the dicing street.
7. The three-dimensional integrated wafer according to claim 5, wherein in adjacent chip units, the detection loops on two sides of the scribe line are connected to a same group of test pads, adjacent test pads in the same group of test pads are connected, and the first power-on pad and the second power-on pad are respectively one of the same group of test pads.
8. The integrated wafer of claim 5, wherein in adjacent chip units, the detection loops on two sides of the scribe line connect two groups of test pads, no connection exists between the two groups of test pads, and adjacent test pads in each group of test pads are connected, the first power-on pad is one test pad in one group of test pads, and the second power-on pad is one test pad in the other group of test pads.
9. The three-dimensional integrated wafer of claim 7 or 8, wherein the detection loop further comprises:
the signal input end is connected with the first electrifying bonding pad through the selector switch, and the signal output end is connected with the second electrifying bonding pad through the selector switch.
10. The three-dimensional integrated wafer of claim 1, wherein a peripheral detection loop is disposed around the wafer assembly, and the peripheral detection loop is configured to detect connection of the plurality of wafer layers in the wafer assembly.
11. The three-dimensional integrated wafer of claim 9, wherein the plurality of wafer layers comprises a first wafer layer and a second wafer layer;
the detection loop comprises:
the first conducting layer is positioned on the first wafer layer and comprises at least two first conducting strips;
the second conducting layer is positioned on the second wafer layer and comprises at least two second conducting strips;
the first conducting strip and the second conducting strip are connected in series through the connecting structure, and then the detection loop is formed.
12. The three-dimensional integrated wafer of claim 11,
the connection structure includes:
one end of the first connecting key is connected with the first conducting strip, and the other end of the first connecting key is close to the second wafer layer;
one end of the second connecting key is connected with the second conducting strip, and the other end of the second connecting key is close to the first wafer layer;
each first conducting strip is connected with two first connecting keys, each second conducting strip is connected with two second connecting keys, the vertical projection of each second conducting strip and the vertical projection of the two adjacent first conducting strips are provided with a superposition part, each first connecting key is correspondingly connected with one second connecting key, and then the first conducting strips and the second conducting strips are connected in series to form the detection loop.
13. The three-dimensional integrated wafer of claim 1, further comprising:
the isolating ring is positioned between the cutting channel and the chip unit, and the detection loop is positioned on one side of the isolating ring, which is far away from the chip unit;
or, the detection loop is positioned between the isolation rings;
or, the detection loop is the isolation loop.
14. A three-dimensional integrated chip, comprising:
a chip unit;
the periphery of the chip unit comprises at least part of cutting marks, and the cutting marks are marks for detecting loops after the wafer assembly is cut;
the detection loop is arranged around each chip unit.
15. A method for testing a three-dimensional integrated wafer, the method being based on the three-dimensional integrated wafer of any one of claims 1 to 13, the method comprising:
and detecting the connection condition of a plurality of wafer layers in each chip unit by using the detection loop around each chip unit.
16. The method according to claim 15, wherein the step of detecting the connection of the wafer layers in each of the chip units by the detection loop around each of the chip units comprises:
inputting a detection current to the detection loop;
receiving an output signal output by the detection loop, wherein the output signal comprises a voltage signal;
determining a resistance value based on the detection current and the voltage signal;
responding to the resistance value within a preset range, and ensuring that the connection condition of the wafer layers in the chip unit is normal; otherwise, the connection condition of the wafer layers in the chip unit is abnormal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024016550A1 (en) * | 2022-07-21 | 2024-01-25 | 湖北三维半导体集成创新中心有限责任公司 | Chip system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024016550A1 (en) * | 2022-07-21 | 2024-01-25 | 湖北三维半导体集成创新中心有限责任公司 | Chip system |
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