CN109390304B - Semiconductor structure, memory device, semiconductor device and manufacturing method thereof - Google Patents
Semiconductor structure, memory device, semiconductor device and manufacturing method thereof Download PDFInfo
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- CN109390304B CN109390304B CN201811185603.8A CN201811185603A CN109390304B CN 109390304 B CN109390304 B CN 109390304B CN 201811185603 A CN201811185603 A CN 201811185603A CN 109390304 B CN109390304 B CN 109390304B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 235000012431 wafers Nutrition 0.000 claims description 36
- 238000005520 cutting process Methods 0.000 claims description 19
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000003860 storage Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012467 final product Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000000712 assembly Effects 0.000 description 3
- 238000000429 assembly Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The disclosure relates to a semiconductor structure, a storage device, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors. The semiconductor structure includes a chip, a power line, and a first pad assembly; the power line is arranged on the chip and extends along a preset direction; the first bonding pad assembly is arranged on the chip and positioned on one side of the power line, and is provided with a plurality of gaps distributed along a preset direction so as to divide the first bonding pad assembly into at least four bonding pads; the gaps comprise a first gap, a second gap and a third gap, and the widths of the first gap and the second gap are larger than those of the third gap; the pad of the first pad assembly includes a power supply pad connected to the power supply line and located between the first gap and the second gap; the power supply pad, the first gap and the second gap are all positioned between two ends of the power supply line. The semiconductor structure can avoid product faults caused by partial chip faults, and is beneficial to improving the product yield.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a memory device, a semiconductor device, and a method of manufacturing the semiconductor device.
Background
With the development of semiconductor technology, chip stacking technology has been widely applied to various types of memories, such as DRAM (Dynamic Random Access Memory ) and the like. It is often desirable to stack and attach multiple chips together to form a unitary body to improve performance.
However, for a plurality of chips stacked, some chips may have circuit faults, which cause problems such as functional failure or leakage of the chips, and are difficult to work normally.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor structure, a memory device, a semiconductor device, and a method for manufacturing a semiconductor device, which can avoid product failure caused by failure of a part of chips, and is beneficial to improving product yield.
According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:
a chip;
the power line is arranged on the chip and extends along a preset direction;
a first pad assembly provided at one side of the power line on the chip, the first pad assembly having a plurality of gaps distributed along the preset direction to divide the first pad assembly into at least four pads; the gap comprises a first gap, a second gap and a third gap, and the widths of the first gap and the second gap are larger than those of the third gap; the pad of the first pad assembly includes a power pad connected to the power line and located between the first gap and the second gap; the power supply pad, the first gap and the second gap are all located between two ends of the power supply line.
In an exemplary embodiment of the present disclosure, a width of at least one of the first gap and the second gap is not less than 15 μm.
In an exemplary embodiment of the present disclosure, the pad of the first pad assembly further includes:
the first bonding pad is positioned on one side of the power bonding pad and is adjacent to the power bonding pad, and the first gap is a gap between the first bonding pad and the power bonding pad;
the second bonding pad is positioned on one side, far away from the first bonding pad, of the power bonding pad and is adjacent to the power bonding pad, and the second gap is a gap between the second bonding pad and the power bonding pad;
and the third bonding pad is positioned on one side, far away from the power supply bonding pad, of the first bonding pad, and the third gap is a gap between the third bonding pad and the first bonding pad.
In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:
a second pad assembly provided at a side of the power line away from the first pad assembly, the second pad assembly having a plurality of gaps distributed along the preset direction to divide the second pad assembly into at least three pads; the gaps of the second pad assembly include a fourth gap and a fifth gap, the fourth gap and the fifth gap each have a width greater than the third gap, the fourth gap is disposed opposite to the first gap, and the fifth gap is disposed opposite to the second gap.
In an exemplary embodiment of the present disclosure, a width of at least one of the fourth gap and the fifth gap is not less than 15 μm.
In an exemplary embodiment of the present disclosure, the first gap is the same width as the fourth gap, and the second gap is the same width as the fifth gap.
According to an aspect of the present disclosure, there is provided a semiconductor device including:
a plurality of semiconductor structures as claimed in any preceding claim, each of said semiconductor structures being arranged in a stack.
According to one aspect of the present disclosure, a method of manufacturing a semiconductor device includes:
providing a plurality of wafers, wherein each wafer comprises a plurality of semiconductor structures arranged at intervals;
detecting the chips of the semiconductor structures on each wafer, and determining the chips with circuit faults as target chips;
cutting the power line of the target chip in the first gap and the second gap of the target chip;
and stacking the wafers, wherein the chips of the two adjacent wafers are arranged opposite to each other one by one.
In an exemplary embodiment of the present disclosure, cutting a power line of the target chip at a first gap and a second gap of the target chip includes:
and cutting the power line of the target chip by utilizing laser to pass through the first gap and the second gap respectively.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes:
and cutting each wafer stacked in the gap between two adjacent semiconductor structures to cut each wafer stacked in the gap.
According to an aspect of the present disclosure, there is provided a memory device including the semiconductor device described in any one of the above.
The semiconductor structure, the storage device, the semiconductor device and the manufacturing method of the semiconductor device are characterized in that the widths of the first gap and the second gap are larger than the third gap and are positioned on two sides of the power supply pad, so that a channel is provided for cutting off the power supply line. For the chip with circuit faults, the power line of the chip can be cut off along the first gap and the second gap, the circuit of the fault chip is cut off, and the fault chip does not work when the final product works, so that the problems of electric leakage and the like are avoided, the final product is prevented from faults, and the product yield is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic view of a semiconductor structure according to an embodiment of the present disclosure, with a power line not cut off.
Fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure with a power line cut.
Fig. 3 is a schematic view of a semiconductor device according to an embodiment of the present disclosure.
Fig. 4 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of step S110 of the manufacturing method of fig. 4.
Fig. 6 is a schematic diagram of step S140 of the manufacturing method of fig. 4.
Fig. 7 is a schematic diagram of step S150 of the manufacturing method of fig. 4.
In the figure: 100. a semiconductor structure; 1. a chip; 101. a substrate; 102. an insulating layer; 2. a power line; 3. a first pad assembly; 301. a first gap; 302. a second gap; 303. a third gap; 31. a power supply pad; 32. a first bonding pad; 33. a second bonding pad; 34. a third bonding pad; 4. a second pad assembly; 401. a fourth gap; 402. a fifth gap; 41. a fourth pad; 42. a fifth bonding pad; 43. a sixth bonding pad; 200. a wafer; 300. punching silicon; 400. and a cutting device.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
The disclosed embodiments provide a semiconductor structure 100 that may be used in a semiconductor device that may include a plurality of stacked semiconductor structures 100. As shown in fig. 1, a semiconductor structure 100 of an embodiment of the present disclosure may include a chip 1, a power line 2, and a first pad assembly 3, wherein:
the power line 2 may be disposed on the chip 1 and extends along a predetermined direction.
The first pad assembly 3 may be provided to the chip 1 and located at a side of the power line 2, the first pad assembly 3 having a plurality of gaps distributed along a predetermined direction to divide the first pad assembly 3 into at least three pads; the gaps may include a first gap 301, a second gap 302, and a third gap 303, the first gap 301 and the second gap 302 each having a width greater than the third gap 303; the pads of the first pad assembly 3 include a power supply pad 31, the power supply pad 31 being connected to the power supply line 2 and located between the first gap 301 and the second gap 302; the power supply pad 31, the first gap 301, and the second gap 302 are all located between both ends of the power supply line 2.
The semiconductor structure 100 of the embodiment of the present disclosure provides a channel for cutting off the power line 2 because the first gap 301 and the second gap 302 are each wider than the third gap 303 and are located at both sides of the power pad 31. For the chip with circuit fault, the power line 2 of the chip can be cut off along the first gap 301 and the second gap 302, as shown in fig. 2, the circuit of the fault chip is cut off, and the fault chip does not work when the final product works, so that the problems of electric leakage and the like are avoided, the final product is prevented from being faulty, and the product yield is ensured.
Portions of the semiconductor structure 100 of embodiments of the present disclosure are described in detail below:
as shown in fig. 1, the chip 1 may include a predetermined circuit, and the first pad assembly 3 may be disposed on the chip 1 and connected to the predetermined circuit, and the structure of the predetermined circuit is not particularly limited herein.
For example, the chip 1 may include a substrate 101 and an insulating layer 102, wherein the material of the substrate 101 may be silicon or other semiconductor material, and the shape and size are not particularly limited herein. The insulating layer 102 may be disposed on the substrate 101, and the material may be silicon oxide, silicon nitride, or a mixture of multiple insulating materials.
As shown in fig. 1, the power line 2 may be disposed on the chip 1 and extends along a predetermined direction. The power line 2 may be disposed on the surface of the chip 1, or embedded on the surface of the chip 1, and the predetermined direction may be any direction of a plane where the power line 2 is disposed, for example, the chip 1 may be rectangular, and the predetermined direction may be a direction parallel to one side of the chip 1. The power cord 2 may have a linear structure, i.e. extend along a predetermined direction, and of course, the power cord 2 may have a curved structure, so long as it can extend along the predetermined direction. In addition, the material of the power supply line 2 may be copper or other metal as long as it is capable of conducting electricity.
As shown in fig. 1, the first pad assembly 3 may be disposed on the chip 1 and located at a side of the power line 2, the first pad assembly 3 may have a plurality of gaps distributed along a predetermined direction, the number of the gaps of the first pad assembly 3 may be at least three, or more, and each of the gaps may include a first gap 301, a second gap 302, and a third gap 303, the first gap 301 and the second gap 302 being located between both ends of the power line 2, the third gap 303 may be located at a side of the first gap 301 remote from the second gap 302, and of course, the third gap 303 may be located between the first gap 301 and the second gap 302, or may also be located at a side of the second gap 302 remote from the first gap 301.
The width of each of the first gap 301 and the second gap 302 may be smaller than the width of the third gap 303, for example, the width of each of the first gap 301 and the second gap 302 is not smaller than 15 μm, i.e., is greater than or equal to 15 μm, for example, 15 μm, 16 μm, 17 μm, etc., which are not listed here; the width of the third gap 303 is less than 15 μm. The widths of the first gap 301 and the second gap 302 may be the same or different.
Meanwhile, each gap of the first pad assembly 3 may divide the first pad assembly 3 into a plurality of pads, and since the number of gaps is at least three, the number of pads is at least four. For example, each pad may be disposed on a surface of the insulating layer 102 away from the first substrate 101, and the pad may be embedded in the insulating layer 102 and flush with the surface of the insulating layer 102 away from the first substrate 101. Meanwhile, the material of the bonding pad may be metal, such as copper, aluminum, tungsten, etc., and of course, may be other metal materials, which are not listed here. The pads may be rectangular in shape, although circular or other shapes are also possible.
As shown in fig. 1, a power supply pad 31 may be included in a pad of the first pad assembly 3, and the power supply pad 31 may be located between both ends of the power supply line 2 and connected with the power supply line 2 so as to be connected with a power supply through the power supply line 2. Meanwhile, the power pad 31 may be located between the first gap 301 and the second gap 302, so that two paths with a width larger than that of the third gap 303 are formed at two sides of the power pad 31, when the chip 1 of the semiconductor structure 100 has a circuit fault, the power line 2 may be cut off at the first gap 301 and the second gap 302, so that the faulty chip cannot work, and thus, the problems of leakage, failure and the like caused by the faulty chip are avoided for products where the faulty semiconductor structure is located, and the product yield is ensured.
As shown in fig. 1, the pads of the first pad assembly 3 may further include a first pad 32, a second pad 33, and a third pad 34, wherein:
the first pad 32 may be located at one side of the power supply pad 31 and adjacent to the power supply pad 31, that is, the first pad 32 and the power supply pad 31 are two adjacent pads among the plurality of pads. The first gap 301 may be a gap between the first pad 32 and the power supply pad 31, that is, the first gap 301 is a gap separating the first pad 32 and the power supply pad 31 among the gaps of the first pad assembly 3. The first pad 32 may be used for connection to a signal line for receiving a control signal or a data transmission signal, and the function thereof is not particularly limited. The shape and size of the first pads 32 may be the same as those of the power supply pads 31, but may be different, and are not particularly limited herein.
The second pad 33 may be located at a side of the power supply pad 31 remote from the first pad 32 and adjacent to the power supply pad 31, that is, the first pad 32 and the second pad 33 are adjacent pads at both sides of the power supply pad 31 among the pads of the respective first pad assemblies 3. The second gap 302 may be a gap between the second pad 33 and the power supply pad 31, that is, the second gap 302 is a gap separating the second pad 33 and the power supply pad 31 among the gaps of the first pad assembly 3. The second pad 33 may be used for grounding, but may be used for other functions, and the functions are not particularly limited herein. The shape and size of the second pads 33 may be the same as those of the power supply pads 31, but may be different, and are not particularly limited herein.
As shown in fig. 1, the third pad 34 may be located at a side of the first pad 32 remote from the power supply pad 31 and adjacent to the first pad 32. The third pad 34 may be used for grounding, but may be used for other functions, and the functions are not particularly limited herein. The gap between the third pad 34 and the first pad 32 is a third gap 303, and the width of the third gap 303 may be less than 15 μm, for example, 8 μm, 5 μm, etc., so that the distance between the third pad 34 and the first pad 32 is beneficial to reducing the overall size of the semiconductor structure 100.
As shown in fig. 1, the semiconductor structure 100 according to the embodiment of the present disclosure may further include a second pad assembly 4, the second pad assembly 4 may be disposed on the chip 1 and located at a side of the power line 2 away from the first pad assembly 3, the second pad assembly 4 may have a plurality of gaps distributed along a predetermined direction, the number of the gaps of the second pad assembly 4 may be at least two, or may be three or more, and the gaps of the second pad assembly 4 may include a fourth gap 401 and a fifth gap 402, the fourth gap 401 and the fifth gap 402 are located between two ends of the power line 2, and the widths of the fourth gap 401 and the fifth gap 402 are not less than the width of the third gap 303, for example, the widths of the fourth gap 401 and the fifth gap 402 are not less than 15 μm, that is, are greater than or equal to 15 μm, for example, 15 μm, 16 μm, 17 μm, and the like, which are not listed herein.
The widths of the fourth gap 401 and the fifth gap 402 may be the same or different. Meanwhile, the fourth gap 401 may be disposed opposite to the first gap 301, and the widths of the first gap 301 and the fourth gap 401 may be the same, so that a path for cutting the power line 2 may be formed, the fifth gap 402 may be disposed opposite to the second gap 302, and the widths of the second gap 302 and the fifth gap 402 may be the same, or a path for cutting the power line 2 may be formed, so that cutting from one side of the power line 2 to the other side may be facilitated.
As shown in fig. 1, each gap of the second pad assembly 4 may divide the second pad assembly 4 into a plurality of pads, and since the number of gaps of the second pad assembly 4 is at least two, the number of pads of the second pad assembly 4 is at least three. For example, the pads of the second pad assembly 4 may be disposed on the surface of the insulating layer 102 away from the first substrate 101, and the pads of the second pad assembly 4 may be embedded within the insulating layer 102 and flush with the surface of the insulating layer 102 away from the first substrate 101. Meanwhile, the material of the pads of the second pad assembly 4 may be metal, such as copper, aluminum, tungsten, or the like, and of course, may be other metal materials, which are not listed here. The shape of the pads of the second pad assembly 4 may be rectangular, but may be circular or other shapes.
As shown in fig. 1, in an embodiment, the fourth pad 41, the fifth pad 42, and the sixth pad 43 are included in the pads of the second pad assembly 4, wherein the fourth pad 41 may be opposite to the power supply pad 31 and connected to the power supply line 2; fifth pad 42 may be directly opposite first pad 32; the sixth pad 43 may be directly opposite to the second pad 33. The fourth gap 401 is a gap between the fourth pad 41 and the fifth pad 42, and the fifth gap 402 is a gap between the fourth pad 41 and the sixth pad 43.
As shown in fig. 2, when the power supply line 2 is cut by the laser, the laser can be moved from the first gap 301 to the fourth gap 401 to cut off the power supply line 2 when the power supply line 2 of the semiconductor structure 100 having a failure is cut by the laser; the laser can also be moved from the second gap 302 to the fifth gap 402, cutting off the power line 2, thereby preventing the power line 2 from leaking out. Of course, in the embodiment of the semiconductor structure 100 in which the second pad assembly 4 is not present, the fourth gap 401 and the fifth gap 402 are not present, and the laser light can be moved from the first gap 301 to the power line 2, and the dicing can be stopped until the power line 2 is cut off; the laser may be moved from the second gap 302 toward the power line 2 until the power line 2 is cut off, and the cutting may be stopped.
Embodiments of the present disclosure provide a semiconductor device that may be stacked chips, such as a DRAM, etc., which are not listed here. As shown in fig. 3, the semiconductor device may include a plurality of the semiconductor structures 100 of the above embodiments, and each semiconductor structure 100 may be stacked.
Adjacent two semiconductor structures 100 are bonded and may be connected through a through-silicon-via 300, and in one embodiment, each semiconductor structure 100 includes a pad, and the pads of the second pad assemblies 4 of the adjacent two semiconductor structures 100 are disposed in a one-to-one correspondence, and the pads of the second pad assemblies 4 of the adjacent two semiconductor structures 100 may be connected through a through-silicon-via process, thereby achieving the connection of each semiconductor structure 100.
For example, in the adjacent two-layer semiconductor structure 100, the fourth pad 41 of the upper-layer semiconductor structure 100 and the fourth pad 41 of the lower-layer semiconductor structure 100 are connected by through-silicon vias, the fifth pad 42 of the upper-layer semiconductor structure 100 and the fifth pad 42 of the lower-layer semiconductor structure 100 are connected by through-silicon vias, and the sixth pad 43 of the upper-layer semiconductor structure 100 and the sixth pad 43 of the lower-layer semiconductor structure 100 are connected by through-silicon vias.
Since the semiconductor device according to the embodiment of the present disclosure adopts the semiconductor structure 100 according to the embodiment of the present disclosure, the power line 2 of the chip having the circuit failure can be cut off during the manufacturing process, and the occurrence of the failure such as the leakage of the semiconductor device due to the failed chip can be avoided, thereby improving the yield.
The embodiment of the present disclosure provides a method for manufacturing a semiconductor device, which may be used to manufacture the semiconductor device of the above embodiment, as shown in fig. 4, and may include:
step S110, providing a plurality of wafers, each of which includes a plurality of semiconductor structures in the embodiment of the semiconductor structure of the disclosure disposed at intervals.
Step S120, detecting the chips of the semiconductor structure on each wafer, and determining the chip with the circuit fault as the target chip.
And step S130, cutting the power line of the target chip in the first gap and the second gap of the target chip.
And step 140, stacking the wafers, wherein the chips of the two adjacent wafers are arranged opposite to each other one by one.
The manufacturing method of the embodiment of the disclosure can detect the chips of each semiconductor structure, and cut the power line 2 of the chip with the circuit fault by the first gap 301 and the second gap 302, so that the fault chip cannot generate the problems of electric leakage and the like, thereby avoiding the faults of electric leakage and the like of the semiconductor device caused by the fault chip and improving the yield.
The following describes each step of the manufacturing method according to the embodiment of the present disclosure in detail:
in step S110, each of the wafers includes a plurality of semiconductor structures in an embodiment of the semiconductor structure of the present disclosure disposed at intervals.
As shown in fig. 5, the wafer 200 may be a wafer including a plurality of semiconductor structures 100, and the number of semiconductor structures 100 is not particularly limited herein. The wafer 200 may be circular in shape, although other shapes are possible. The specific structure of each semiconductor structure 100 may refer to the above-mentioned embodiment of the semiconductor structure 100, and will not be described herein.
In step S120, the chips of the semiconductor structure on each wafer are inspected to determine the chip having the circuit failure as the target chip.
The chip 1 of each semiconductor structure 100 may be inspected by a special inspection device to determine whether there is a circuit fault such as leakage or failure, and the specific inspection method is not particularly limited herein, as long as the circuit fault can be inspected. The chip 1 having the circuit failure may be regarded as a target chip, and if none of the chips 1 has the circuit failure, the target chip is not present.
In step S130, the power line of the target chip is cut in the first gap and the second gap of the target chip.
As shown in fig. 2, the power supply line 2 may be cut with the first gap 301 and the second gap 302 as cutting paths. For example, the power line 2 of the target chip can be cut by using the laser in the first gap 301 and the second gap 302, so as to cut off the power line 2, prevent the current from flowing out to two ends of the power line 2, avoid the problem of leakage of the failed chip, and avoid adverse effect on the semiconductor device.
For the chip 1 of the semiconductor structure 100 having the fourth gap 401 and the fifth gap 402, the laser light may be moved from the first gap 301 to the fourth gap 401, the power line 2 may be cut off, the laser light may be moved from the second gap 302 to the fifth gap 402, and the power line 2 may be cut off again.
In addition, the power line 2 may be cut off by LDI (laser direct imaging ) technology, or the power line 2 may be cut off by a photolithography process, which is not listed here.
And step 140, stacking the wafers, wherein the chips of the two adjacent wafers are arranged opposite to each other one by one.
As shown in fig. 6, the wafers 200 may be stacked to form a multi-layer structure, and the chips 1 of the semiconductor structures 100 belonging to two adjacent wafers 200 may be arranged one by one, that is, the projection of any chip 1 of any wafer 200 on the adjacent wafer 200 coincides with one chip 1 of the adjacent wafer 200. Meanwhile, two adjacent wafers 200 may be bonded, and the opposite chips 1 may be connected through the through-silicon vias 300, and in particular, the through-silicon vias 300 may connect pads of the second pad assembly 4 of the opposite chips 1. The specific structure and implementation of the through-silicon via 300 are not particularly limited herein, as long as the respective opposing chips 1 can be connected.
The manufacturing method of the embodiment of the present disclosure may further include:
and step S150, cutting each wafer stacked in the gap between two adjacent chips to cut each wafer stacked in the gap.
As shown in fig. 7, the dicing apparatus 400 may be used to dice the stacked wafers 200 using a laser dicing process to obtain a plurality of semiconductor devices, each including a plurality of stacked semiconductor structures 100. Specifically, the laser may be used to cut each wafer 200 stacked in the gap between two adjacent semiconductor structures 100 until a plurality of individual semiconductor devices are formed.
The embodiment of the present disclosure also provides a storage device, which may include the semiconductor device of the above embodiment, and may be a memory bank of a computer or the like. The detailed structure of the semiconductor device and the beneficial effects of the memory device can refer to the above embodiments, and will not be described herein.
Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order or that all illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
providing a plurality of wafers, wherein each wafer comprises a plurality of semiconductor structures arranged at intervals, and each semiconductor structure comprises a chip, a power line and a first bonding pad component, wherein: the power line is arranged on the chip and extends along a preset direction; the first bonding pad assembly is arranged on the chip and positioned on one side of the power line, and is provided with a plurality of gaps distributed along the preset direction so as to divide the first bonding pad assembly into at least four bonding pads; the gap comprises a first gap, a second gap and a third gap, and the widths of the first gap and the second gap are larger than those of the third gap; the pad of the first pad assembly includes a power pad connected to the power line and located between the first gap and the second gap; the power supply pad, the first gap and the second gap are all positioned between two ends of the power supply line;
detecting the chips of the semiconductor structures on each wafer, and determining the chips with circuit faults as target chips;
cutting the power line of the target chip in the first gap and the second gap of the target chip;
and stacking the wafers, wherein the chips of the two adjacent wafers are arranged opposite to each other one by one.
2. The method of manufacturing according to claim 1, wherein cutting the power supply line of the target chip at the first gap and the second gap of the target chip comprises:
and cutting the power line of the target chip by utilizing laser to pass through the first gap and the second gap respectively.
3. The manufacturing method according to claim 1, characterized in that the manufacturing method further comprises:
and cutting each wafer stacked in the gap between two adjacent semiconductor structures to cut each wafer stacked in the gap.
4. The manufacturing method according to claim 1, wherein a width of at least one of the first gap and the second gap is not less than 15 μm.
5. The method of manufacturing of claim 1, wherein the bonding pad of the first bonding pad assembly further comprises:
the first bonding pad is positioned on one side of the power bonding pad and is adjacent to the power bonding pad, and the first gap is a gap between the first bonding pad and the power bonding pad;
the second bonding pad is positioned on one side, far away from the first bonding pad, of the power bonding pad and is adjacent to the power bonding pad, and the second gap is a gap between the second bonding pad and the power bonding pad;
and the third bonding pad is positioned on one side, far away from the power supply bonding pad, of the first bonding pad, and the third gap is a gap between the third bonding pad and the first bonding pad.
6. The method of manufacturing of claim 5, wherein the semiconductor structure further comprises:
a second pad assembly provided at a side of the power line away from the first pad assembly, the second pad assembly having a plurality of gaps distributed along the preset direction to divide the second pad assembly into at least three pads; the gaps of the second pad assembly include a fourth gap and a fifth gap, the fourth gap and the fifth gap each have a width greater than the third gap, the fourth gap is disposed opposite to the first gap, and the fifth gap is disposed opposite to the second gap.
7. The manufacturing method according to claim 6, wherein a width of at least one of the fourth gap and the fifth gap is not less than 15 μm.
8. The method of manufacturing according to claim 6, wherein the first gap and the fourth gap have the same width, and the second gap and the fifth gap have the same width.
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| CN201811185603.8A CN109390304B (en) | 2018-10-11 | 2018-10-11 | Semiconductor structure, memory device, semiconductor device and manufacturing method thereof |
| PCT/CN2019/110017 WO2020073901A1 (en) | 2018-10-11 | 2019-10-08 | Semiconductor structure, memory device, semiconductor device and method of manufacturing the same |
| US17/106,525 US11282789B2 (en) | 2018-10-11 | 2020-11-30 | Semiconductor structure, memory device, semiconductor device and method of manufacturing the same |
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| WO2020073901A1 (en) * | 2018-10-11 | 2020-04-16 | Changxin Memory Technologies, Inc. | Semiconductor structure, memory device, semiconductor device and method of manufacturing the same |
| CN117425969A (en) * | 2022-05-19 | 2024-01-19 | 京东方科技集团股份有限公司 | Wiring substrate and electronic device |
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